EUROSOI-ULIS 2015
2015 Joint International EUROSOI Workshop and International Conference
on Ultimate Integration on Silicon
January 26-28, 2015 - Bologna, Italy
Monday
Tuesday
Wednesday
Invited Presentation
M. Haond
Session III FDSOI devices
Invited Presentation
M. Becherer
Session VII Memories and
magnetics devices
Coffee Break
Coffee Break
Session IV
Steep-slope devices - I
Session VIII
Steep-slope devices - II
Lunch
Lunch
Invited Presentation
G. Duesberg
Session V
2D materials
Invited Presentation
D. M. Buca
Session IX
Advanced integration
technologies
Coffee Break
Coffee Break
Coffee Break
Session II
Power devices and ESD
protection
Session VI
III-V materials and devices
Session X
Advanced characterization
techniques
Welcome Reception
and Poster Session
Gala dinner
09.00
09.40
10.40
11.00
Workshop on
"III-V semiconductor
materials in
Nanoelectronics"
12.40
14.00
14.20
Conference Opening
14.40
15.20
Invited Presentation
D. Collard
Session I
Nanowires and nanosensors
16.20
16.40
17.00
Workshop on "III-V semiconductor materials in Nanoelectronics"
09:00 Opening, Luca Selmi
9:10 K. Tomioka (Hokkaido University - Japan): III-V nanowire channels and III-V/Si heterojunctions for
low-power switches
9:50 P. Palestri (Univ. of Udine - Italy): Advanced modeling of III-V fully depleted nanoscale devices
10:30 Coffee Break
10.45 O. Penzin (Synopsys - USA): Mobility and quantization modeling in III-V semiconductor materials
from a TCAD perspective
11.25 N. Waldron (IMEC - Belgium): III-V-MOSFET Characterization and integration onto silicon
12.05 F. Bufler and A. Erlebach (Synopsys - Switzerland): Enhancements to TCAD tools for advanced IIIV semiconductor devices
12.45 Live demo of the new features of Synopsys TCAD tools for III-V compound semiconductor devices
Session I: Nanowires and nanosensors
Chairs: Sorin Cristoloveanu (IMEP-LAHC, France)
Enrico Sangiorgi (Univ. Bologna, Italy)
14.40 Invited Presentation - Nano systems and nano scaled devices for new applications in biology and
nanotechnology D. Collard (LIMMS/CNRS-IIS, UTokyo - Japan)
15.20 From Double to Triple Gate: Modeling Junctionless Nanowire Transistors
B. C. Paz, M. Casse, S. Barraud, F. Avila-Herrera, A. Cerdeira, G. Reimbold, O. Faynot, M. A. Pavanello
15.40 350K Operating Silicon Nanowire Single Electron/Hole Transistors Scaled Down to 3.4nm
Diameter and 10nm Gate Length
R. Lavieville, S. Barraud, A. Corna, X. Jehl, M. Sanquer, and M. Vinet
16.00 P-type Trigate Nanowires: Impact of Nanowire Thickness and Si0.7Ge0.3 Source-Drain Epitaxy
L. Gaben, S. Barraud, M.-P. Samson, J.-M. Hartmann, C. Vizioz, F. Aussenac, F. Allain, S. Monfray, F. Boeuf, T.
Skotnicki, F. Balestra, M. Vinet
16.20 Effect of Independently Sized Gates on the Delay of Reconfigurable Silicon Nanowire Transistor
Based Circuits
J. Trommer, A. Heinzig, T. Baldauf, S. Slesazeck, T. Mikolajick, W.M. Weber
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Session II: Power devices and ESD protection
Chairs: Claudio Fiegna (Univ. Bologna, Italy)
Susanna Reggiani (Univ. Bologna, Italy)
17.00 A model for Hot-Carrier Degradation in nLDMOS Transistors Based on the Exact Solution of the
Boltzmann Transport Equation Versus the Drift-Diffusion Scheme
P. Sharma, S. Tyaginov, Y. Wimmer, F. Rudolf, H. Enichlmair, J.-M. Park, H. Ceric, and T. Grasser
17.20 Leakage current and breakdown of GaN-on-Silicon vertical structures
D. Cornigli, F. Monti, S. Reggiani, E. Gnani, A. Gnudi, G. Baccarani
17.40 BIMOS transistor in thin silicon film and new solutions for ESD protection in FDSOI UTBB CMOS
technology
Ph. Galy, S. Athanasiou, S. Cristoloveanu
18.00 A new Latch-free LIGBT on SOI
J. Olsson, L. Vestling, K.-H. Eklund
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Session III: FDSOI devices
Chairs: Francisco Gamiz (Universidad de Granada, Spain)
Sigfried Mantl (Research Center Juelich GmbH, Germany)
9.00 Invited Presentation - Fully depleted SOI: achievements and future developments M. Haond
(STMicroeletronics - France)
9.40 Self-Heating in 28 nm Bulk and FDSOI
S. Makovejev, N. Planes, M. Haond, D. Flandre, J.-P. Raskin, V. Kilchytska
10.00 Impact of Non Uniform Strain configuration on transport properties for FD14+ devices
C. Medina-Bailon, C. Sampedro, F. Gamiz, A. Godoy, L. Donetti
10.20 Modeling study of the mobility in FDSOI devices with a focus on near-spacer-region
F.G. Pereira, D. Rideau, O. Nier, C. Tavernier, F. Triozon, D. Garetto, G. Mugny, B. Sklenard, G. Hublot, M. Pala
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Session IV: Steep-slope devices - I
Chairs: Andrei Vladimirescu (ISEP/UCBerkeley)
Denis Flandre (UC Louvain, Belgium)
11.00 CMOS-compatible abrupt switches based on VO2 metal-insulator transition
W. A. Vitale, C. F. Moldovan, A. Paone, A. Schueler, A. M. Ionescu
11.20 Effects of Dit-induced degradation on InGaAs/InAlAs Nanowire Superlattice-FET using Al2O3 and
HfO2/La2O3 as gate stacks
P. Maiorano, E. Gnani, A. Gnudi, S. Reggiani, G. Baccarani
11.40 Fabrication and Analysis of Vertical p-type InAs-Si Nanowire Tunnel FETs
D. Cutaia, K. E. Moselund, M. Borg, H. Schmid, L. Gignac, C. M. Breslin, S. Karg, E. Uccelli, P. Nirmalrai, H. Riel
12.00 Strained Si Nanowire GAA n-TFETs for low supply voltages
G. V. Luong, S. Trellenkamp, K. K. Bourdelle, Q. T. Zhao and S. Mantl
12.20 Experimental Investigations of SiGe Channels for Enhancing the SGOI Tunnel FETs Performance
C. Le Royer, A. Villalon, S. Martinie, P. Nguyen, S. Barraud, F. Glowacki, S. Cristoloveanu, M. Vinet
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Session V: 2D materials
Chairs: Costin Anghel (ISEP, France)
Antonio Gnudi (Univ. Bologna, Italy)
14.00 Invited Presentation – Investigation of 2D Transition Metal Dichalcogenide Films for Electronic
Devices G.S. Duesberg, T. Hallam, M. O’Brien, R. Gatensby, H.-Y. Kim, K. Lee, N. C. Bemer, N. McEvoy, C. Yim
(Trinity College - Ireland)
14.40 Spectral sensitivity of a graphene/silicon pn-junction photodetector
S. Riazimehr, D. Schneider, C. Yim, S. Kataria, V. Passi, A. Bablich, G. S. Duesberg, M. C. Lemme
15.00 Impact of Hot Carrier Stress on the Defect Density and Mobility in Double-Gated Graphene FieldEffect Transistors
Yu. Yu. Illarionov, M. Walt, A.D. Smith, S. Vaziri, M. Ostling, M.C. Lemme, T. Grasser
15.20 Spatial Variability in Large Area Single and Few-layer CVD Graphene
C. F. Moldovan, K. Gajewski, M. Tamagnone, R. S. Weatherup , H. Sugime, A. Szumska, W. A. Vitale, J. Robertson,
A. M. Ionescu
15.40 Relevance of the physics of off-plane transport through 2D materials on the design of vertical
transistors
G. Iannaccone, Q. Zhang, S. Bruzzone, G. Fiori
16.00 Towards Amplifier Design with a SiC Graphene Field-Effect Transistor
J. D. Aguirre-Morales, S. Fregonese, M. S. Khenissa, M. M. Belhaj, A. D. D. Dwivedi, H. Happy, T. Zimmer
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Session VI: III-V materials and devices
Chairs: Gerben Doornbos (TSMC, Belgium)
Quentin Rafhay (IMEP, France)
16.40 Tri-gate In0.53Ga0.47As-on-insulator Junctionless Field Effect Transistors
V. Djara, L. Czornomaz, N. Daix, D. Caimi, V. Deshpande, E. Uccelli, M. Sousa, C. Marchiori, and J. Fompeyrine
17.00 Modeling approaches for band-structure calculation in III-V FET quantum wells
E. Caruso, G. Zerveas, G. Baccarani, L. Czornomaz, N. Daix, D. Esseni, E. Gnani, A. Gnudi, R. Grassi, M.Luisier, T.
Markussen, P.Palestri, A.Schenk, L.Selmi, M. Sousa, K. Stokbro, M. Visciarelli
17.20 Investigation of Performance Limiting Factors of sub-10nm III-V FinFETs
P. Feng, S. Narayanan, E. Towie, C. Alexander, S. M. Amoroso, A. Asenov, S. M. Pandey, B. Sahu, F. Benistant
17.40 Drift-Diffusion Simulation Without Einstein Relation
F. M. Bufler, A. Erlebach, and A. Wettstein
18.00 Al2O3/InGaAs interface study on MOS capacitors for a 300mm process integration
M. Billaud, J. Duvernay, H. Grampeix, B. Pelissier, M. Martin, T. Baron, H. Boutry, Z. Chalupa, M. Cassé, T. Ernst,
M. Vinet
18.20 On the enhancement of electron mobility in ultra-thin (111)-oriented In0.53Ga0.47As channels
M. Poljak, S. Krivec, T. Suligoj
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Session VII: Memories and magnetic devices
Chairs: Victor Sverdlov (TU Wien, Austria)
Massimo Rudan (Univ. Bologna, Italy)
9.00 Invited Presentation - Low-power 3D integrated ferromagnetic computing M. Becherer, S.
Breitkreutz, I. Eichwald, G. Ziemys, J. Kiermaier, G. Csaba, D. Schmitt-Landsiedel (TU Munich - Germany)
9.40 Modeling of OxRAM Variability from Low to High Resistance State using a Stochastic Trap Assisted
Tunneling-based Resistor Network
D. Garbin, Q. Rafhay, E. Vianello, S. Jeannot, P. Candelier, B. DeSalvo, G. Ghibaudo, L. Perniola
10.00 Schottky barrier height engineering for next generation DRAM capacitors
K. Cho, M. Pesic, S. Knebel, C. Jung, J. Chang, H. Lim, N. Kolomiiets, V. V. Afanas, U. Schroeder, T. Mikolajick
10.20 A new high resolution Random Telegraph Noise (RTN) characterization method for Resistive RAM
M. Maestro, J. Diaz, A. Crespo-Yepes, M.B. Gonzalez, J. Martin-Martinez, R. Rodriguez, M. Nafria, F. Campabadal,
X. Aymerich
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Session VIII: Steep-slope devices - II
Chairs: Benjamin Iñiguez (Universitat Rovira i Virgili, Spain)
Andreas Schenk (ETHZ Zurich, Switzerland)
11.00 Effects of electrical stress and ionizing radiation on Si-based TFETs
L. Ding, E. Gnani, S. Gerardin, M. Bagatin, F. Driussi, L. Selmi, C. Le Royer, A. Paccagnella
11.20 Efficient Quantum Mechanical Simulation of Band-to-band Tunneling
C. Alper, P. Palestri, J. L. Padilla, A. Gnudi, R. Grassi, E. Gnani, M. Luisier, A. M. Ionescu
11.40 Investigation of Ambipolar Signature in SiGeOI Homojunction Tunnel FETs
R. P. Oeflein, L. Hutin, J. Borrel, A. Villalon, C. Le Royer, S. Martinie, C. Tabone, M. Vinet
12.00 Study of Low Frequency Noise in Vertical NW-Tunnel FETs with Different Source Compositions
F. S. Neves, P. G. D. Agopian, J. A. Martino, B. Cretu, A. Vandooren, R. Rooyackers, E. Simoen, A. Thean and C.
Claeys
12.20 New Insights in Z2-FET Mechanisms at Variable Temperature
H. El Dirani, L. Onestas, P. Ferrari, Y. Solaro, P. Fonteneau, S. Cristoloveanu
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Session IX: Advanced integration technologies
Chairs: Maryline Bawedin (IMEP-LAHC, France)
David Leadley (University of Warwick, UK)
14.00 Invited Presentation - GeSn for nanoelectronic and optical applications D. M. Buca, S. Wirths, D.
Stange, N. von den Driesch, T. Stoica, D. Grützmacher, S. Mantl, Z. Ikonic, J-M. Hartmann (Forschungszentrum
Juelich - Germany)
14.40 Mobility improvement of ultrathin-body Germanium-on-insulator (GeOI) MOSFETs on flipped
Smart-CutTM GeOI substrates
X. Yu, J. Kang, R. Zhang, M. Takenaka, and S. Takagi
15.00 Characterization of bonding surface and electrical insulation properties of inter layer dielectrics
for 3D monolithic integration
K. Garidis, G. Jayakumar, A. Asadollahi, P.-E. Hellstrom, M. Ostling
15.20 Study of High-Temperature Smart CutTM: Application to Thin Films of Single Crystal Silicon and
Silicon-On-Sapphire Films
R. Meyer, O. Kononchuck, H. Moriceau, M. Lemiti, M. Bruel
15.40 Reverse terrace graded Si1-x Gex/Ge/Si(001) virtual substrates grown using RP-CVD on on-axis and
6 degree off-axis substrates for future developments in III-V materials integration
V. Sivadasan, M. Myronov, S. Rhead, J. Halpin, D. Leadley
16.00 New Insights on Strained-Si On Insulator Fabrication by Top Recrystallization of Amorphized SiGe
on SOI
A. Bonnevialle, S. Reboh, L. Grenouillet, C. Le Royer, Y. Morand, S. Maitrejean, J.-M. Hartmann, A. Halimaoui, D.
Rouchon, M. Cassé, C. Plantier, R. Wacquez, M. Vinet
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Session X: Advanced characterization techniques
Chairs: Pierpaolo Palestri (Univ. Udine, Italy)
Elena Gnani (Univ. Bologna, Italy)
16.40 Low frequency noise statistical characterization of 14nm FDSOI technology node
E. G. Ioannidis, C. G. Theodorou, S. Haendler, M.-K. Joo1, E. Josse, C. A. Dimitriadis, G. Ghibaudo
17.00 Second Harmonic Generation for non-destructive characterization of silicon-on-insulator
substrates
I. Ionica, L. Pirro, V. Nguyen, J. Changala, M. Kryger, A. Kaminski, G. Vitrant, L. Onestas, S. Cristoloveanu
17.20 Thickness Characterization by Capacitance Derivative in FDSOI p-i-n Gated Diodes
C. Navarro, M. Bawedin, F. Andrieu, J. Cluzel, Y. Solaro, P. Fonteneau, F. Martinez, B. Sagnes, S. Cristoloveanu
17.40 Measurement of the Minimum Energy Point in Silicon on Thin-BOX(SOTB) and Bulk MOSFET
S. Nakamura, J. Kawasaki, Y. Kumagai, K. Usami
18.00 Characterization of Flexible CMOS Technology Transferred onto a Metallic Foil
J. Philippe, A. Lecavelier des Etangs-Levallois, P. Latzel, F. Danneville, J.-F. Robillard, D. Gloria, E. Dubois
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Poster Session
Electron relaxation times and resistivity in metallic nanowires due to tilted grain boundary
planes
K. Moors, B. Soree, Z. Tokei, W. Magnus
Simulation of the Measurement by Scanning Electron Microscopy of Edge and Linewidth
Roughness Parameters in Nanostructures
M. Ciappa, E. Ilgusatiroglu, A. Yu. Illarionov
TFET/CMOS Hybrid Pseudo Dual-Port SRAM for Scratchpad Applications
N. Gupta, A. Makosiej, O. Thomas, A. Amara, A. Vladimirescu, C. Anghel
Analytical Approach to Consider Gaussian Junction Profiles in Compact Models of TunnelFETs
M. Graef, F. Hain, F. Hosenfeld, B. Iniguez, A. Kloes
Toward understanding of donor-traps-related dispersion phenomena on normally-ON
AlGaN/GaN HEMT through transient simulations
S. Strangio, P. Magnone, F. Crupi, C. Fiegna, C. Pace, G. Iannaccone, A. Heiman, D. Shamir
Power Gating for FDSOI using Dynamically Body-Biased Power Switch
Y. Kumagai, M. Kudo, K. Usami
Disilane and trimethylsilane as precursors for RP-CVD growth of Si1-yCy epilayers on Si(001)
G. Colston, M. Myronov, S. D. Rhead, D. R. Leadley
A simulation study of short channel effects with a QET model based on Fermi-Dirac statistics
for Si, Ge and III-V MOSFETs
S. Sho, S. Odanaka, A. Hiroki
Comparison between vertical silicon NW-TFET and NW-MOSFET from analog point of view
P. G. D. Agopian, J. A. Martino, A. Vandooren, R. Rooyackers, E. Simoen, A. Thean, C. Claeys
Static and low frequency noise characterization in standard and rotated UTBOX nMOSFETs
B. Cretu, E. Simoen, J.-M. Routoure, R. Carin, M. Aoulaiche, C. Claeys
Analytical model of thin-body InGaAs-on-InP MOSFET low-field electron mobility for
integration in TCAD tools
G. Betti Beneventi, S. Reggiani, A. Gnudi, E. Gnani, A. Alian, N. Collaert, A. Mokuta, A. Thean, G.
Baccarani
Quantum Simulations of a Heterojunction Inter-layer Tunnel FET based on 2-D gapped
crystals
J. Cao, M. Pala, A. Cresti, D. Esseni
Quasi-static capacitance measurements in pseudo-MOSFET configuration for Dit extraction
in SOI wafers
L. Pirro, I. Ionica, X. Mescot, L. Faraone, S. Cristoloveanu, G. Ghibaudo
Impact of the diameter of vertical Nanowire-Tunnel FETs with Si and SiGe source
composition on analog parameters
C. C. M. Bordallo, V. B. Sivieri, J. A. Martino, P. G. D. Agopian, R. Rooyackers, A. Vandooren, E. Simoen,
A. Thean, C. Claeys
Cu Nanolines in Coplanar Waveguide Transmission Lines
P. Sarafis, A. G. Nassiopoulou
Enhanced Dynamic Threshold UTBB SOI at High Temperature
K. R. A. Sasaki, M. Aoulaiche, E. Simoen, C. Claeys, J. A. Martino
Improved Analog Operation of Junctionless Nanowire Transistors Using Back Bias
R. Trevisoli, R. T. Doria, M. de Souza, M. A. Pavanello
Nanoscale Characterization of MOS Systems by Microwaves: Dopant Profiling Calibration
L. Michalas, A. Lucibello, C. H. Joseph, E. Brinciotti, F. Kienberger, E. Proietti, R. Marcelli
A Simple Analytical Variable Barrier Transistor Drain Current Model
O. Moldovan, F. Lime, S. Barraud, B. Iniguez
A simple compact model for carrier distribution and its application in single-, double- and
triple-gate junctionless transistors
F. Y. Liu, I. Ionica, M. Bawedin, S. Cristoloveanu
Sub-22nm scaling of UTB2SOI devices for Multi-VT applications
C. Diaz-Llorente, C. Medina-Bailon, C. Sampedro, F. Gamiz, A. Godoy, L. Donetti
Dependence of Spin Lifetime on Spin Injection Orientation in Strained Silicon Films
J. Ghosh, D. Osintsev, V. Sverdlov, S. Selberherr
Determination of ad hoc deposited charge on bare SOI wafers
C. Fernandez, N. Rodriguez, C. Marquez, F. Gamiz
High Temperature Influence on Analog Parameters of Bulk and SOI nFinFETs
A.V Oliveira, P. G. D. Agopian, E. Simoen, C. Claeys, J. A. Martino
Experimental demonstration of planar SiGe on Si TFETs with counter doped pocket
S. Blaeser, S. Richter, S. Wirths, S. Trellenkamp, D. Buca, Q. T. Zhao, S. Mantl
Band structure of III-V thin films: an atomistic study of non-parabolic effects in confinement
direction
G. Mugny, F. Triozon, J. Li, Y.-M. Niquet, G. Hiblot, D. Rideau, C. Delerue
SOI/SOS MOSFET Universal Compact SPICE Model with Account for Radiation Effects
K. O. Petrosyants, I. A. Kharitonov, L. M. Sambursky
Systematic study of the palladium-graphene contact
A. Gahoi, V. Passi, S. Kataria, S. Wagner, A. Bablich, M. C. Lemme
Ultra-Low-Power Diodes Using Junctionless Nanowire Transistors
M. de Souza, R. T. Doria, R. Trevisoli, M. A. Pavanello
Impact of Back Plane on the carrier mobility in 28nm UTBB FDSOI devices, for ESD
applications
S. Athanasiou, P.Galy, S. Cristoloveanu
Ovonic Materials for Memory Nano-Devices: Stability of I(V) Measurements
M. Rudan, E. Piccinini, F. Buscemi, R. Brunetti