Reconfigurable Communication
System Design
Anthony Gaught
Advisors:
Dr. In Soo Ahn and Dr. Yufeng Lu
Department of Electrical and Computer Engineering
Bradley University Peoria, Illinois
November 13, 2012
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Outline
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Motivation
Brief Theory of QPSK
Project Overview
Project Description
Project Milestones
Simulation
Project Status
Conclusions
References
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Motivation
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Software defined radio (SDR) has advantages
over traditional communication systems.
Design a reconfigurable digital communication
system using FPGA.
QPSK system is studied for the project.
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Brief Theory of QPSK
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Binary phase shift keying (BPSK) is a modulation scheme
which transmits one bit of data per symbol.
Quadrature phase shift keying (QPSK) cuts the
bandwidth necessary to transmit data in half when
compared to BPSK.
QPSK’s bit error performance is the same as that of
BPSK due to orthogonality of the I and Q carriers used in
QPSK.
QPSK is used in many applications such as cell phones,
satellite communication, cable modems, and others.
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Brief Theory of QPSK
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s(t) = I(t)*cos(2πfot) – Q(t)*sin(2πfot)
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Each symbol represents
two bits of data.
I and Q bits are
determined based on the
phase of the received
symbol.
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Project Overview
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This project implements a QPSK communication
system consisting of both a transmitter and a
receiver.
The system is designed using VHDL and is
implemented on Xilinx Spartan 3E FPGAs.
Allows for flexible transmission data rates.
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Project Description
at the transmitter
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Two-bit random data is generated.
The data is split into In-phase (I) and
quadrature-phase (Q) components.
The data is shaped using raised cosine filters.
The data is over sampled.
The data is modulated by cosine and sine
carriers.
The modulated signals are combined for
transmission.
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Project Description
at the receiver
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The received signal is demodulated by local
cosine and sine carriers.
The data passes through a matched filter.
The data is down sampled.
The data is fed into a threshold device.
The output is displayed on an oscilloscope.
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Milestone One
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The receiver and transmitter will be
implemented on a single FPGA.
The transmitter is connected directly to the
receiver.
A digital to analog converter (DAC) will be used
to display data.
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Milestone One Block Diagram
I = transmitter side in-phase Q = transmitter side quadrature phase
I_r = receiver side in-phase Q_r = receiver side quadrature phase
S(n) = internal signal from transmitter to receiver
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Milestone Two
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The receiver and transmitter will be
implemented on different FPGA boards.
Data will pass through an (ADC) and a DAC in
this milestone.
A carrier recovery circuit and phase locked loop
will be implemented in the receiver.
Adverse affects caused by channel imperfections
will be explored.
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Milestone Two & Three Block
Diagram
I = transmitter side in-phase Q = transmitter side quadrature phase
I_r = receiver side in-phase Q_r = receiver side quadrature phase
S(t) = signal from transmitter to receiver
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Milestone Three
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High speed ADC and DAC modules will be used
to connect the transmitter and receiver for
assessing overall system operations.
Bit error rate of the system will be used to
evaluate the overall system performance.
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Simulation Results
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I and Q data at the transmitter
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Simulation Results
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The I and Q data are shaped using a set of raised cosine
filters for controlling intersymbol interference.
80
60
40
20
0
-20
0
5
10
15
# of Filter coefficients
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25
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Impulse Response of Raised Cosine Filter
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Simulation Results
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The recovered I and Q after being filtered are identical
to theoretical results from MATLAB simulations.
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Simulation Results
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The demodulated I and Q data match up with their
theoretical results.
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Simulation Results
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The demodulated I and Q data are then resized to bring
the amplitude into a usable range for the Spartan 3E.
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Simulation Results
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Received I and Q data appear as a constellation of 4
groups of points which matches the theoretical results
well.
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Simulation Results
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Transmitted and received I and Q data.
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Simulation Results
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The transmitted and received I and Q data after being
cleaned up by using a threshold device.
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Project Status
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Milestone one has been completed.
Preliminary work for Milestone two has begun.
One of the biggest obstacles will be the
implementation of the phase locked loop.
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Schedule
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1/24 - 2/07 phase locked loop and carrier recovery implementation
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2/14 - 2/21 system optimization and evaluation
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2/28 - 3/07 high speed ADC and DAC implementation
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3/14 - 3/28 system evaluation
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4/04 – 5/02 TBA note: the Bradley expo and project presentation
will occur during this period.
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Conclusions
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FPGA design is flexible to build digital
communication systems. The methods used for
modulation can be reconfigurable.
The system has a fast design turn-around time
compared to conventional design using
specialized hardware or DSP processors.
SDR capabilities are to be investigated and
demonstrated in the project.
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References
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Anton Rodriguez, and Michael Mensinger Jr., “Software-defined Radio using Xilinx”,
Senior Project Report, Department of Electrical and Computer Engineering, Bradley
University, Peoria Illinois, May 2011.
Anthony Gaught, “Software-defined Radio Symbol Generator”, Junior Project Report,
Department of Electrical and Computer Engineering, Bradley University, Peoria
Illinois, May 2012.
Anthony Gaught, Alexander Norton, and Christopher Brady., “FPGA-based 16 QAM
communication system”, EE 568 Report, Department of Electrical and Computer
Engineering, Bradley University, Peoria Illinois, April 2012.
Leon Couch, “Digital and analog communication systems”, 8th ed., Boston: Pearson,
2013.
Charles Roth Jr., and Lizy John, “Digital systems design using VHDL”, 2nd ed., United
States: Thomson, 2008.
Spartan-3E Data Manual, Xilinx, San Jose, CA,2009.
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Questions
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