Aatmesh Shrivastava, John Lach, and Benton H.
Calhoun
University of Virginia, Charlottesville
International Symposium on Low Power Electronics and Design

[1] Magen, et. al.
SLIP 2004
• Interconnect consumes >50% of dynamic power in a micro-processor.
• 90% of interconnect power is in 10% of interconnect.
2

• A Exa-byte of data is to be transmitted per second to enable exascale computing.
[2] P. Kogge et. al. DARPA/ITPO 08
• State of the interconnect consumes 1-3pJ/bit/mm. A exabyte/s will need 10-30 Mega-Watt Power. [2]
3

• Voltage Scaling for Interconnect
– Driver
– Receiver
• Literature Review
• Proposed Interconnect Receiver
– Charge Pump
– Complete circuit diagram
– Simulation
• Implementing the interconnect in 4 core
Alpha
• Results
• Design Comparison
4

• Voltage Scaling has been used to reduce interconnect power [4-10].
• Logic runs at rated VDD, wires at reduced VDDI.
Interconnect driver circuits are needed
• Key Question :- Performance overhead vs Power.
5

[4] H. Zhang, et. al.
TVLSI 2000
• Two NMOS transistors are used at output stage
• A signal at logic level ( 1V) is converted to a signal interconnect level (0.3V)
• We use this driver in our proposed interconnect circuit.
6

ON
VDDI
0
• Restores the signal back to the logic level. Poor performance, VDDI > V
T.
• Differential amplifier [8-10] can be used for better performance but have higher power overhead.
• We propose an improved single ended receiver.
7

Schemes B/W
(Ghz)
Swing
(V)
Normalized
Energy
Basic ( no scaling) >1 1
Single-ended [4,5,7] <0.25
0.6
Differential [8-10] >1
Capacitive [6] <0.25
0.05
0.05
1
0.6
0.8
0.2
• In prior art either energy saving is less or performance is poor.
8

• Existing solutions do not address power and performance in conjunction.
9

• Charge-pump is used.
• It boosts the signal to three times the interconnect swing
• Good performance and much lower power
10

• When IN is at 0, A is precharged to 0.3V. So when IN goes high A goes to 0.6V (Ideal case).
• Similarly when IN is at 0.3V, A is precharged to 0V. So when IN goes low A goes to -0.3V (ideal).
• Total swing at A is 0.9V. C swings from V
T to VDD-V
T
11

Charge Pump
0 IN 0
C
CH
C
CL
MP3
LV
T
VDDI=0.3V
MN5
MN4
φ2
MN3
VDD=1V
V
TL
VDD-V
+0.3
TL
LV
T
V
TL
V
TL
VDD=1V
MP2
HV
T
C
1
MP1
HV
T
B
A
MN1
0.6
HV
T
φ1
0.3V
0.3
0
MNX
Weak
Keeper
-0.3
Pulse generator
Delay
1
Delay
0
OUT
0V
φ1
φ2
12

IN OUT
• Reduced swing interconnect signal gets reconstructed with good performance.
13

• Proposed Solution gives very good performance and very low energy.
14

• Data-Bus of alpha was implemented using differential, basic and proposed interconnect circuit.
• Over the set of splash benchmarks, the proposed interconnect saves up to 70% of energy.
15

Schemes B/W
(GHz)
Basic >1
Single Ended
[4,5,7]
Differential
<0.25
>1
[8-10]
Capacitive [6] <0.25
This Work >1
Swing
(V)
Norm. Energy Area of 1 repeater
1
0.6
0.05
0.05
0.3
1
0.6
0.8
0.2
0.3
2X
15-24X
100-250X
NA
22X
• Novel interconnect circuit has best in class PPA
16

17

1.
Nir Magen et. Al. “Interconnect-Power Dissipation in a Microprocessor” Workshop on System Level Interconnect Prediction
2004
2.
P. Kogge, K. Bergman, S Borka
, et. al, “ExaScale Computing Study: Technology Challenges in Achieving Exascale Systems”
DARPA/IPTO, September 2008
3.
E. Kusse and J.M. Rabaey , “Low-Energy Embedded FPGA Structures” IEEE International Symposium on Low Power
Electronics Design, August 1998 .
4.
H. Zhang, V. George and J.M. Rabaey , “Low-Swing On-Chip Signalling Techniques: Effectiveness and Robustness” IEEE
Transactions on Very Large Scale Integration (VLSI), Vol-8 No-3, June 2000
5.
J.C.G. Montesdeoca, J.A. Montiel-Nelson and S. Nooshabadi , “CMOS Driver Receiver Pair for Low Swing Signalling for Low
Energy Onchip Interconnects” IEEE Transactions on Very Large Scale Integration (VLSI), Vol-17 No-2, February 2009.
6.
R. Ho, I. Ono, F. Liu, A. Chow, J. Schauar and R. Drost , “High Speed and Low Energy capacitively driven wires” IEEE
International Solid State Circuits Conference, February 2007.
7.
M. Ferretti and P.A. Beere “Low Swing Signaling Using a Dynamic Diode-Connected Driver” European Solid-State Circuits
Conference, September 2001.
8.
A. Narshimha, M. Kasotiya and R. Sridhar “A Low-Swing Differential signaling Scheme for on-chip Global Interconnects”
International Conference on VLSI Design, January 2005.
9.
N. Tzartzanis
, W.W. Walker “Differential Current Mode Sensing for Efficient On-Chip global Signaling” IEEE Journal of Solid
State Circuits, Vol-40 No-11, November 2005.
10. H. Ito, M. Kimura, K. Miyashita, T. Ishii, K. Okada and K. Masu
, “A Bidirectional and Multidrop Transmission Line Interconnect for Multipoint to Multipoint OnChip Communication” IEEE Journal of Solid State Circuits, Vol-43 No-4, April 2008.
11.
V. Alder and E.G. Friedman, “Repeater Design to Reduce Delay and Power in Resistive Interconnects”. IEEE Transactions on
Circuits and Systems-II, Vol-45 No-45, May 1998.
12. P.E. Allen and D.R. Holberg ., “CMOS Analog circuit design” Oxford Press 2002.
13. R.E. Kessler, E.J. McLellan and D.A. Webb, “The Alpha 21264 Microprocessor Architecture” International Conference on
Computer Design, October 1998.
14. N.L. Binkert, R.G. Dreslinski, L.R. Hsu, K.T. Lim, A.G. Saidi and S.K. Reinhardt, “The M5 Simulator: Modeling Networked
Systems” IEEE Micro, July 2006.
18

19

• When IN goes hi, A goes to 0.6V, bringing B to ground.
• OUT goes high completing the transition.
• It also brings C to VDD-V
T precharges A to 0.6V
and
0.3V
IN
A
0V
0.3V
0.6V
0V
B
1V
0V
OUT
C
V
T
φ1
φ2
1V
T
CRIT
1V
0V
1V-V
T
0.3V
-0.3V
V
T
1V
T
CRIT
20

21

LV
T
C
RESET
RESET
VDDI=0.3V
MNR
A a) RESET implementation in
Receiver ckt of Figure 9
VDD=1V
MP2
HV
T
MP1
HV
T
MN1
HV
T
B
BUS<0>
Rx
BUS<1>
Rx
BUS<N>
Rx
RESET b) RESET implementation in BUS
22

VDD-V
TL
V
TL
C
VDD=1V
MP2
HV
T
MP1
HV
T
B
A
0.6V
0.3V
MN1
HV
T
MNX
HV
T
Weak
Keeper 0.3V
0V
-0.3V
a) First Stage of receiver having high leakage
Mean=66nA
100nA
Mean=125nA
B=0
1
µA
1 µA
B=1 b) Monte Carlo result of leakage for
B=0 and B=1 cases
23

Mean=316nA Mean=165pS
100nA 1 µA
a) leakage at VDDI=0.35V
b) Propagation delay (IN à OUT) at VDDI=0.25V
24