NoC theory part II: Network adapters

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Network-on-Chip
Network Adapter and
Network Issues
System-on-Chip Group, CSE-IMM, DTU
NoC Overview Slide
Network Adapter
Routing Node
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Overview
• Network Adapter
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Session / Transport Layer
Plug and play interface
Traffic encapsulation
• Network
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Topology
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Protocol
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Network Adapter
• Functions
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Encapsulation
Service Management
Interface multiple IPs to a single NoC port
• Sockets
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OCP
VCI
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Encapsulation
• Convert messages into packets
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Header to payload ratio
Header is overhead
 Routing information
 Control information (such as services, flit
number, etc)
 Possible error-correction
• Broadcast, narrowcast services
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Service Management
• Definition: Acquire, retain, use and relinquish
any service in a predictable way!!
• Types of Services:
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BE: not guarantee, only correctness and
completion of transmission is guaranteed
GS: provides bounded guarantees
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Latency
Bandwidth
Power
etc…
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Sockets
• Point-to-point connection (abstraction)
• Abstract away the network details for the IP
cores
• Examples: OCP, VCI, etc
• Limitations (a bus-based view):
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Broadcast, narrowcast, services are not supported
Easy means for GS service request, retention and
teardown not supported
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Network
• Two characteristics
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Topology
Protocol
• Flow-Control
• Quality-of-Service
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Topology
• Form: relates to geometry
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Scalable with area and power
Easy to lay out in 2D chip plane
• Nature of link: relates to unidirectional
or bidirectional links
• Presence of IP core
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Forms of Topology
K-ary 2-cube
• preferred for easy of
layout
• better utilization of
available bandwidth
K-ary tree
• better hardware utilization
for same bandwidth
• good to exploit locality of
traffic
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Nature of Topological Link
Uni-directional
Bi-directional
• Common variations: torus and mesh
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IP Core of Topology
Indirect
network
Direct network
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Irregular Topologies
• Hybrid, asymmetric and hierarchical
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Router Architecture
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Buffering Schemes
• Input
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Head-of-line blocking
• Output
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Expensive in terms of hardware
• Virtual-output
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Moderately buffer cost at very high
improvement in performance
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Crossbar and Arbitration Unit
• Crossbar connects input port to output
port
• Arbitration is used to prioritize, setup
and manage crossbar connections
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Possibly programmable for best-effort and
guaranteed service connections
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Protocol
• Many dimensions
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Circuit vs packet switched
Connectionless or connection-oriented
Adaptive or deterministic
Minimal or non-minimal
Delay or loss
Centralized or decentralized control
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Common Routing Mechanisms
• Store-and-forward
• Virtual-cut through
• Wormhole
Protocol
Router
Stalling
Latency
Storage
Store-andforward
Packet
Packet
At two nodes and link
between them
Virtual-cut
through
Header
Header
At all nodes and links
spanned by the packet
Wormhole
Header
Packet
At the local node
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Flow-Control
• Network-level: NA-to-NA
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In-order delivery
Packet Acknowledgment
Credit based injection schemes
• Link-Level: Node-to-Node
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Congestion look-ahead or stalling
Virtual channel selection
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Quality-of-Service
• End-to-end
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Reserving virtual circuits from source to
destination
One-way, round-trip or just reverse-way
Connection management overhead!!
• Node-to-Node
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Logically independent resource allocation (avoid
contention)
Division of link bandwidth!!
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Conclusion
• Each NoC level offers many parameters such as
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topology, packet size, buffereing, that to optimize the
implementation
Sockets are enable plug’n’play of IP cores, thus
flexibility in placement anywhere within the network
geometry
Topology is influenced by placement of IP cores
Many protocol choices available, with wormhole
costing the least in terms of buffering
Buffers are most area consuming component within
the routers
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References
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BJERREGAARD, T. and MAHADEVAN, S. 2004. “NoC Survey Manuscript”, Submitted.
JANTSCH, A. and TENHUNEN, H. 2003. Networks on Chip. Kluwer Academic Publishers.
BHOJWANI, P. and MAHAPATRA, R. 2003. Interfacing cores with on-chip packet-switched networks. In Proceedings of the
Sixteenth International Conference on VLSI Design.
ANDRIAHANTENAINA, A. and GREINER, A. 2003. Micro-network for SoC : Implementation of a 32-port spin network. In The
Proceedings of Design, Automation and Test in Europe Conference and Exhibition. IEEE.
BANERJEE, N., VELLANKI, P., and CHATHA, K. S. 2004. A power and performance model for network-onchip architectures. In
Proceedings of the 2004 Design, Automation and Test in Europe Conference (DATE’04) . IEEE.
DALLY, W. J. 1990. Performance analysis of k-ary n-cube interconnection networks. IEEE Transactions on Computer.
DALLY, W. J. and SEITZ, C. L. 1987. Deadlock-free message routing in multiprocessor interconnection networks.IEEE
Transactions on Computers.
DUATO, J. 1996. A necessary and sufficient condition for deadlock-free routing in cut-through and store-and forward networks.
IEEE Transactions on Parallel and Distributed Systems.
KUMAR, S., JANTSCH, A., SOININEN, J.-P., FORSELL, M., MILLBERG, M., OBERG, J., TIENSYRJÄ, K., and HEMANI, A. 2002. A
network on chip architecture and design methodology. In Proceedings of the Computer Society Annual Symposium on VLSI,
ISVLSI 2002. IEEE Computer Society.
OCPIP. 2003. Open Core Protocol Specification, Release 2.0. http://www.ocpip.org.
MILLBERG, M., NILSSON, E., THID, R., and JANTSCH, A. 2004. Guaranteed bandwidth using looped containers in temporally
disjoint networks within the nostrum network on chip. In Proceedings of the conference on Design, automation and test in
Europe. IEEE Computer Society.
RADULESCU, A., DIELISSEN, J., GOOSSENS, K., RIJPKEMA, E., and WIELAGE, P. 2004. An efficient on-chip network interface
offering guaranteed services, shared-memory abstraction, and flexible network configuration. In Proceedings of the 2004 Design,
Automation and Test in Europe Conference (DATE’04). IEEE.
RIJPKEMA, E., GOOSSENS, K. G. W., RADULESCU, A., DIELISSEN, J., MEERBERGEN, J. V., WIELAGE, P., and WATERLANDER, E.
2003. Trade offs in the design of a router with both guaranteed and best-effort services for networks on chip. In Proceedings of
the Design, Automation and Test in Europe Conference. IEEE.
TAMIR, Y. and FRAZIER, G. L. 1988. High-performance multiqueue buffers for VLSI communication switches. In Proceedings of
the 15th Annual International Symposium on Computer Architecture . IEEE Computer Society.
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