“Dragonfly”
: A new detectorat
controller
Scientific
CCD characterisation
Universidad
for high
time-resolution
observations
Complutense
LICA Laboratory
High Time Resolution Optical Astrophysics, Royal Astronomical Society, London
April 12, 2013
We are developing a new CCD controller intended for high time-resolution observations using both
conventional and electron-multiplying CCDs. We have tried to incorporate as many features as possible
into our design, such as an integrated data-acquisition PC, a 1GB image store, a microcontroller-based
temperature servo able to directly power Peltier coolers, a shutter controller, a high-voltage clock
generator for EMCCDs and an integrated power supply.
Read-out sequencing and ADC control is
performed using a Xilinx Spartan-3 FPGA. This allows high-speed data acquisition and buffering across
several parallel channels.
The FPGA communicates with the DAS PC over a USB link, the PC then links to the outside world via
gigabit-Ethernet. Our prototype contains just two data acquisition channels that can run at up to
3Mpix/s but we intend to expand this to eight 10Mpix/s channels for our final design. We also intend
to integrate the functions of the DAS PC and FPGA sequencer into a single device such as the Xilinx
Zynq processor. This will also implement a server allowing users to operate the controller via a series of
web pages. We have recently completed the prototype hardware for this controller and are now
looking for partners to allow us to continue the development.
The prototype controller has been built to evaluate our concept of an integrated controller/DAS PC combiation. It will
allow us to investigate potential noise issues, gain experience with FPGA programming and serve as a test bed for highlevel sofware. We also hope to use the controller for GRB observations at the Črni Vrh observatory.
Our next controller will have up to 8 video processor channels and a target pixel rate of 10MHz/Channel. The data
acquisition PC will be incorporated into a “system-on-a-chip” (SOC ) device such as the Xilinx Zync. Both EMCCD and
conventional CCDs will be supported. The same two-level board geometry will probably be used, with a single large
analogue board implementing clock and bias generation with a smaller mezzanine-mounted digital board containing
the SOC and data converters.
Digital interface board
Analogue board
Clamp and sample
video processor
Dual-slope
video processor
EMCCD HV
clock
Bias generators
The controller will provide a high-level communication interface with the observing system. Because
of the fully capable Linux computer serving as a front end to the clocking circuit, the user programs do
not need to worry about any hardware-specific details of the electronics. The default communication
interface will be provided provided by CORBA in addition to the HTTP interface. The front-end
computer contains a web server which serves the pages for camera-status monitoring and the setting
of the working parameters through a customised GUI.
Top view of future controller
Two channels
16-bit 6MHz
ADCs
32-channel
14-bit DACs
Voltage regulators
PSU
Temperature
controller
Backplane
Voltage monitor
12-bit
16 channel
DAC
Bias circuitry
12-bit
16 channel
DAC
Bias circuitry
Voltage Regulator
Clock generators
Data is acquired and buffered from the ADCs by the
FPGA module. This is then transmitted to the
backplane-mounted PC via a USB2 interface.
An FPGA is a programable logic device whose
hardware can be configured to implement
any digital function, from a simple ADC
interface to a complete CPU. The FPGA logic
is described using ether the VHDL or Verilog
languages.
Peltier access hole
Differential analogue inputs
E2V CCD97
16 bit ADCs > 20MHz
with 8-bit
parallel interface
1
ADC
2
ADC
3
ADC
4
ADC
The test camera is cooled by an 8W 2stage Peltier cooler. A specially
machined detector PCB is used to
allow cooling to 50oC below ambient.
The camera is hermetically sealed but
operated at ambient pressure. It
contains an E2V CCD97 which allows
us to evaluate controller performance
with both its conventional low noise
output and also its high-speed
electron-multiplying output.
Video
preamplifiers
window
Jam-nut connector
soldered directly onto
back of the internal PCB.
Prototype
Future
Parameter
controller
controller
Video channels
2
8
Pixel rate /channel
3 MHz
10MHz
CCD clocks
12
24
CCD biases
12
20
Maximum clock rate
3 MHz
10 MHz
EMCCD compatible ?
yes
yes
Integrated DAS ?
yes
yes
Integrated temperature
controller?
yes
yes
Download configuration/waveform
file into controller
HV clock
Voltage monitor
micro-controller
VP8
VP7
VP6
CCD “Engine”
Boot Media
USB2
SD card
FPGA heatsink
EMCCDs are able to give very high
pixel rates with very low noise.
They are easily capable of
detecting single photons at multiMHz pixel rates.
Dr. Simon Tulloch
Dr. Jure Skvarč
VP5
“CCD engine”
digital board.
Mounted below
the analogue board
The backplane not only mounts the DAS
PC and the power-supply but also
contains a shutter driver, powerconditioning circuitry, a high-voltage
generator, a programmable temperature
controller and a Peltier driver.
EMCCD-based test camera attached to controller
The head-board video preamplifiers
produce a differential output i.e.
consisting of two versions of the video
signal of opposing phase. When received
in the controller, these signals are then
recombined in a way that removes any
common-mode noise. This suppresses
pattern-noise in the images.
VP4
Flex-ribbons
Front-panel
Mil-style
connector
2-stage Peltier
Gold-plated
centre
section
Backplane connector
Controller performance parameters
40W Power supply
Underside of detector head-board PCB
Thermal-isolation
slots bridged by
Nichrome wire.
Side view of future controller
Analogue board
1.6GHz Intel Atom based Linux PC
2GB RAM, 8GB Flash disc.
Inter-PCB
connectors
VP3
Spartan-3E FPGA module implementing
clock sequencer and ADC/DAC interface
Controller backplane
Waveform viewer tool
Front-panel
connectors
to CCD head
Power
Clock
Gen.
Ethernet
interface
PHY
ADC
8
ADC
7
SOC
2GB RAM module socketed on under-side
ADC
6
ADC
5
Sequencer outputs Low-speed
(CCD clock outputs) DAC interface
The CCD engine could find many additional
applications in the field of high-speed data acquisition.
It could be piggyback mounted onto other analogue
boards, for example one optimised for the control of
CMOS image sensors. Development of this engine will
comprise the major part of our proposed future
controller.
Differential analogue inputs
The readout waveforms and other FPGA parameters
are loaded into the FPGA through the USB port. The
waveforms consist of clocking units which are
combined and iterated through a sequencer. Each
clocking unit defines a meaningful action of the
waveform generator, such as parallel image shift,
serial shift, etc. The clocking unit can define
up to 64 digital signals within the FPGA, half of
which are available to the CCD clocks and the rest
are used for internal FPGA controls, such as
triggering the ADC conversion.
Analogue
board
The new controller therefore provides a level of abstraction which shields the CCD engineer from
learning FPGA programming yet provides full control over the clocking sequences and the sensor
configuration. Another abstraction exists at the application level where standard communication
protocols are used to command the controller and retrieve images. It is hoped that this approach will
simplify usage of the CCD yet preserve full flexibility for the interfacing and tuning of different
imaging sensors.
Waveform definition file
VP1-8=Video
processor analogue
circuitry
24MB/s USB
interface from
FPGA board to PC
mounted on
backplane
Data can be stored locally within the controller, in
Flash or SSD memory, or sent over a Gigabit
Ethernet interface.
Clock circuitry
Digital interface mounted on base
of the analogue board
Clock circuitry
“stay-alive” power
reserve for orderly
shutdown in event
of power failure.
Clock circuitry
Voltage regulators
VP2
VP1
Digital board
on lower side
The user does not need to know any implementation details of the FPGA design. Instead the clocking
units are defined using a custom controller definition language which allows setting of the clocking
levels and other analog outputs, definition of clocking units and definition of the readout sequences
which define the readout waveform and data readout. The definition language is very minimalistic so
it is easy learn and understand. Before uploading the clocking units to the controller they can be
simulated and verified by a waveform viewer.
SOC or “system on a chip”
devices are a logical choice
for a high speed CCD
controller.They conisist of
one or more CPUs surrounded
by a matrix of programmable
logic. This logic can be
flexibly
configured
to
implement
the
readout
sequencer and ADC/DAC
interfaces whilst leaving the
CPU to implement the highlevel software and controlGUI web servers.
The Xilinx Zynq is a powerful example of an SOC device. It
contains built-in memory controllers , ethernet and USB
interfaces and a huge number of user I/O pins that can be
dedicated to CCD clocks and the control of video
processors.
Peltier power/temperature
servo connector.
QUCAM
Astronomical Detectors
www.qucam.com
smt@qucam.com
+34 663604482