© 2003 Xilinx, Inc. All Rights Reserved

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After completing this module, you will be able to:
Use the FPGA Editor to view device resources
Connect the internal nets of an FPGA to output pins (Insert Probes)
Determine the specific resources used by your design
Make minor changes to your design without re-implementing
FPGA Editor - 18 - 3 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only

Rhett Whatcott: v6.1: Changed the order of the sections - moved
“Viewing Device
Resources…” as
2nd section.
•
•
•
•
•
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FPGA Editor Basics
Viewing Device Resources and Constrained Paths
Adding a Probe
Making Minor Changes
Summary
Appendix: Creating a Macro
FPGA Editor - 18 - 4 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only

Rhett Whatcott: v6.1: Next slide was removed, titled: FPGA
Editor Input Files
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The FPGA Editor is a graphical application
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Displays device resources
Precise layout of chosen device
The FPGA Editor is commonly used to:
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View device resources
Make minor modifications
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Done late in the design cycle
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Does not require reimplementation of the design
Insert Probes
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Used for in circuit testing
© 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only FPGA Editor - 18 - 5

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Use the FPGA Editor to:
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View the design’s layout
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Drive a signal to an output pin for testing (inserting a probe)
Add logic or special architectural features to your design without having to recompile the design
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Do not use the FPGA Editor to:
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Floorplan
Carelessly control the place and route
© 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only FPGA Editor - 18 - 6

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The FPGA Editor cannot:
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Add additional logic from a second netlist
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Because translation (NGDBuild) is completed
Additional logic would need to be hand-placed and routed
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Make modification to design files
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HDL and netlist files will not reflect modifications
FPGA Editor - 18 - 7 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only

Rhett Whatcott: v6.1: Changed notes
Removed next slide.
MAP
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Xilinx implementation flow
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Entry points for FPGA Editor
FPGA Editor NCD & PCF
PAR
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Placing and routing critical components
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Before implementation (Post-MAP)
NCD
BITGEN
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Making minor changes
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After implementation (Post-PAR) BIT
Remember to document the changes to your design, because your netlist will not reflect the changes made by the FPGA Editor!
© 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only FPGA Editor - 18 - 8

Rhett Whatcott: v6.1: Removed next two slides.
Menu
Bar
Array
Window
History
Window
FPGA Editor - 18 - 9
Push
Button
Panel
List
Window
World
Window
© 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only

Rhett Whatcott: v6.1: New slide, replacing the next two.
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Zoom
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Array window resources
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Use the World window to keep track of your location on the die when you are zoomed in
FPGA Editor - 18 - 10 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only

Rhett Whatcott: v6.1: retranslate.
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Easiest way to select objects in your design
Displays
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Components
Nets
Paths
Layers
Constraints
Macros
Name Filter search feature
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Limit the number of elements shown
Use Wildcards (* and ?)
Ability to highlight components
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Choose from 15 different colors
© 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only FPGA Editor - 18 - 11

Rhett Whatcott: v6.1: Viewing
Device
Resources… section moved here.
Changed the order of the sections.
•
•
•
•
•
•
FPGA Editor Basics
Viewing Device Resources and Constrained Paths
Adding a Probe
Making Minor Changes
Summary
Appendix: Creating a Macro
FPGA Editor - 18 - 12 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only

Rhett Whatcott: v6.1: Removed
previous slide.
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Select a slice or IOB
Click the editblock button
View LUT configuration
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LUT
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RAM
ROM
SRL
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View the LUT equations
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Click the Show/Hide Attributes button
© 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only FPGA Editor - 18 - 13

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View constraints in the List window
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Select Constraints in the pulldown menu
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Perform a timing analysis
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Tools  Trace  Setup and Run
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Trace window
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Generates a Timing Analysis report
Select the Type of Report
Click Apply
© 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only FPGA Editor - 18 - 14

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Trace Summary window
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Select the constraint to report on
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Click Details
The Trace Errors window
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Lists the slack on each delay path
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Most-critical path is listed last
Select a delay path to be displayed
Click Hilite
FPGA Editor - 18 - 15 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only

Rhett Whatcott: v6.1: Moved location of this slide… retranslate.
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Determine net delays
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History window shows:
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Net destination
Associated delay
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Click the “attrib” button
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Located on the Push Button Panel
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Select Pins tab
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Determine skew
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(Longest Delay) - (Shortest Delay)
© 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only FPGA Editor - 18 - 16

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Multiple Array windows can be viewed by using the command:
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Window  New  Array
Window
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List, Array, or World window can be selected
Useful for viewing different areas of interest at the same time
View and edit the sources and destinations of routes
© 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only FPGA Editor - 18 - 17

Rhett Whatcott: v6.1: Changed the order of the sections - moved
“Viewing Device
Resources…” as
2nd section.
•
•
•
•
•
•
FPGA Editor Basics
Viewing Device Resources and Constrained Paths
Adding a Probe
Making Minor Changes
Summary
Appendix: Creating a Macro
FPGA Editor - 18 - 18 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only

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Ties an internal signal to an output pin
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Probes are managed in the
Probes GUI
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Click the “probes” button on the Push Button Panel
Tools  Probes
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Probes can be added, deleted, edited, or highlighted
© 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only FPGA Editor - 18 - 19

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Click the Add button
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Opens the Define Probe window
Select desired probes to Delete, Edit, or Hilite
After a Probe has been added:
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Click Bitgen to create new bitfile
Click Download to open iMPACT programmer
Document the change
© 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only FPGA Editor - 18 - 20

Rhett Whatcott: v5.2: Changed
Notes for Demo.
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Enter a Pin Name
Select Net to be probed
Click OK
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Filter feature to limit net options
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Method
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Automatic routing
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Selects the shortest route
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Possible long wait times
Manual routing
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Specific pins can be selected
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Selects the shortest route if multiple pins are selected
FPGA Editor - 18 - 21 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only

Rhett Whatcott: v6.1: Changed the order of the sections - moved
“Viewing Device
Resources…” as
2nd section.
•
•
•
•
•
•
FPGA Editor Basics
Viewing Device Resources and Constrained Paths
Adding a Probe
Making Minor Changes
Summary
Appendix: Creating a Macro
FPGA Editor - 18 - 22 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only

Rhett Whatcott: v6.1: retranslate.
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Adding a Component
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Select the resource (slice, IOB, etc.) from the Array window
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Click the add button
Complete the Component Properties box
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All resources can be added
FPGA Editor - 18 - 23 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only

Rhett Whatcott: v6.1: New slide.
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Adding component pins
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Select pin
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Select “add” in push button panel
Complete Properties box
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Pin name
FPGA Editor - 18 - 24 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only

Rhett Whatcott: v6.1: retranslate.
Added demo.
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Modifying the equations
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Click the Show/Hide Attributes button
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Complete the Component
Properties box
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* (AND), + (OR), ~ (NOT), @
(XOR)
Select Apply changes
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Tool performs a Design Rule
Check (DRC)
Click the Save Changes and Close Window button
© 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only FPGA Editor - 18 - 25

Rhett Whatcott: v6.1: Added demo.
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Add resources
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Select properties of resource
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Click on pin to route signal paths
This will automatically route the signals inside the slice
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Click the Apply button
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Performs a Design Rule Check
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Click the Save Changes and Close Window button
© 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only FPGA Editor - 18 - 26

Rhett Whatcott: v6.1: New slide.
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Routing setup: Tools  Route  Auto Route Setup…
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Auto Route Design: Options used to auto route the entire design (default values)
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Timespec Driven: Auto routes signals to meet timing constraints
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Generally best results
Allow Pin Swap: Allow for pin swapping during auto routing. Enables better use of resources
Auto Route Selection: Options used for a selected route
(pins, nets, components)
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Delay driven: Auto routes selected item as fast as possible
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Generally best results
Resource Driven: Minimizes use of resources (wires and pips) during auto route
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Default
© 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only FPGA Editor - 18 - 27

Rhett Whatcott:
V6.1: new slide.
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Rerouting a signal:
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Select net in Array or List window to reroute
Click  unroute in pushbutton panel
Specify routing options (Auto Route
Setup)
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Click  autoroute in pushbutton panel
FPGA Editor - 18 - 28 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only

Rhett Whatcott: v6.1: Changed
Heading.
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Select site pins
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Click the site pin of a resource
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Hold down the Shift key
Click another site pin
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Route the net
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Click the “route” button
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Automatically chooses the shortest route between site pins
© 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only FPGA Editor - 18 - 29

Rhett Whatcott: v6.1: Changed
Heading.
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Select object to route
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Click the site pin of a resource
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Hold down the Shift key
Click net
Click subsequent nets
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Route the net
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Click the “route” button
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Routes one net segment
© 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only FPGA Editor - 18 - 30

Rhett Whatcott: v6.1: Changed
Heading.
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Select object to route
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Click previously routed segment
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Hold down the Shift key
Click site pin
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Route the net
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Click the “route” button
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Automatically chooses the shortest route from segment to site pins
FPGA Editor - 18 - 31 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only

Rhett Whatcott: v6.1: retranslate.
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Adding an IOB
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Select IOB
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Make certain the IOB is bonded, unbonded IOBs have X in IOB box
Select “add” in pushbutton panel
Edit Properties, click OK
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Use the editblock command to edit resources
FPGA Editor - 18 - 32 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only

Rhett Whatcott: v6.1: Changed heading.
Removed next slide.
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Input/Output registers, output 3-state, I/O standard, drive strength, and slew rate control can be viewed and modified
FPGA Editor - 18 - 33 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only

Rhett Whatcott: v6.1: Changed the order of the sections - moved
“Viewing Device
Resources…” as
2nd section.
•
•
•
•
•
•
FPGA Editor Basics
Viewing Device Resources and Constrained Paths
Adding a Probe
Making Minor Changes
Summary
Appendix: Creating a Macro
FPGA Editor - 18 - 34 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only

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List some of the common uses for the FPGA Editor
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When should the FPGA Editor not be used?
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What are the benefits of inserting a probe?
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If any modifications were made using the FPGA Editor, it is important to
__________ any changes. Why?
FPGA Editor - 18 - 35 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only

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List some of the common uses for the FPGA Editor
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View device resources
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Make minor modification
Insert probes
Generate a new bitstream
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When should the FPGA Editor not be used?
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FPGA Editor should not be used to Floorplan a design or control the place and route
© 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only FPGA Editor - 18 - 36

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What are the benefits of inserting a probe?
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The probes capability makes it possible to route a signal to an output pin for testing, and generate a new bitstream for the design without re-implementing
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If any modifications were made using the FPGA Editor, it is important to
Document any changes. Why?
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It is necessary to document your changes because the netlist will not reflect the changes made by the FPGA Editor
FPGA Editor - 18 - 37 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only

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The FPGA Editor provides you with a tremendous amount of design control
Most customers use this tool for understanding the device utilization or adding test probes
Careful use of this tool is important because indiscriminate movement of logic can severely reduce the likelihood of getting good design performance and utilization
The FPGA Editor allows you to make minor changes to a design without re-implementing your design
Document any changes to your design because your netlist will not reflect the changes made by the FPGA Editor
© 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only FPGA Editor - 18 - 38

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FPGA Editor Help
– http://support.xilinx.com  Software Manuals
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Help  Help Topics
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Tech Tips
– http://support.xilinx.com  Tech Tips  Floorplanner & FPGA Editor
FPGA Editor - 18 - 39 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only