Verification Code Longevity: Learn Expert Techniques

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Verification Code Longevity: Learn
Expert Techniques
Webinar
Created by
Mike Mintz
Trusster, Inc.
mike@trusster.com
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Agenda
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Introduction
What is bit rot?
Adaptable versus Reusable code
Minimizing your assumptions to Maximize Adaptability
Canonical Monitors and Checkers
Aldec RTL Simulators & Design Rule Checking
Question and Answer Session
www.aldec.com
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What is bit rot ?
• Funny term for code that does not continue to work
• All code rots !
• The environment changes : DUT, simulator, protocol,
methodology, etc.
• It’s all a probability game
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Adaptable versus Reusable code
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Focus your thinking on the “core” parts
It’s all a probability game
Reusable code is a myth
Adaptable code means you have to do work to some
existing codebase
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Maximize Adaptability
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Changes are easy – or just plain impossible
Separate interface from Implementation
Keep the abstraction level constant
Make simple utility objects!
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Standard Components
Teal
www.aldec.com
Truss
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The “standard parts”
• A way to wiggle wires, perform randomization, and make
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threads
Orthogonal parameter passing
A memory read/writer system
A logger
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Canonical Monitor
Monitor class
Derived for printing
namespace usb {
struct data {
int type;
std::vector<int> payload;
};
namespace usb {
struct printer: public usb::monitor {
virtual void receive_completed_ (const data& d) {
printf (“Packet Type is %d\n”, d.type);
for (int i(0); i < d.payload.size; ++i) {
printf (“Packet [%d]:0x%x\n”, i,
d.payload[i]);
}
}
};
}
struct interface {
teal::reg d_plus, d_minus;
};
struct monitor : truss::thread {
interface i_;
void start_ ();
virtual void receive_completed_
(const data&) =0;
};
Derived for channel
namespace usb {
typedef truss::channel<data> channel;
struct usb_monitor_agent : public usb_monitor {
virtual void receive_completed_ (const data& d) {
channel_->put (d);
}
usb::channel* channel_;
}
};
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Canonical Checker
class checker {
public:
truss::checker
(const std::string& n) :
truss::checker (n) {}
virtual void start_ () {
do {
data e = get_expected_();
data a = get_actual_();
if (e != a) {
log_ << teal_error << “Expected != actual”
<< teal::endm;
}
note_actual_check_();
note_expected_check_();
} while (! done_());
• Should be simple
• Goals are the “real” meat
• What does done() mean ?
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}
}
protected:
virtual data get_expected_ () = 0;
virtual data get_actual_ () = 0;
virtual bool done_ () = 0;
};
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Sumary
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All code “rots”
It always take some effort to adapt
Box your assumptions!!!
Use a small set of useful components
Monitors/Checkers have a standard form
It’s all a probability game-- but you can rig the odds
www.aldec.com
Aldec RTL Simulators
• Common-Kernel Simulators
• Languages: VHDL, Verilog® , SystemVerilog, SystemC & EDIF 200
• HDL Design Tools: Design Creation, Code2Graphics™, Block and
State Diagram, Waveform editor, stimulus generation, Language and
legacy design support. (Active-HDL)
• Debugging: Advanced Waveform Viewer, Memory Viewer, Xtrace,
Advanced Dataflow, Profiler, HDL/SystemC code level Debugging &
Post-Simulation Debugging.
• Code Coverage: Code/Line, Statement, Branch, Expression,
Condition and Toggle coverage.
• Advanced Verification: ESL, TLM, OVM and VMM
• Assertion-Based Verification: Assertion waveform viewer,
Active-HDL
coverage, breakpoint editor. SystemVerilog IEEE 1800
Assertions/Coverage, PSL & OVA.
• Co-Simulation: MATLAB® and Simulink® Interfaces
• ALINT Design Rule Checking: also available as stand-alone
application with custom rule creation support
• Simulation Regression Manager (SFM)
• Riviera-PRO (Linux 32/64, Windows XP/Vista/2003/2000)
Active-HDL (Windows ONLY.)
www.aldec.com
Riviera-PRO
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Q&A and Contact Info
ALDEC
Website:
http://www.aldec.com
Tel. USA:
+1-702-990-4400
Tel. Canada: +1-613-867-8600
Fax USA/Can: +1-702-990-4414
E-mail:
sales@aldec.com
Tel. Europe:
+33-6-80-32-60-56
Fax Europe:
+33-1-46-34-85-91
E-mail Europe: sales-eu@aldec.com
Trusster Corporation
Website:
http://www.trusster.com/
E-mail:
mike@trusster.com
• To attend additional ALDEC events, go to www.aldec.com/events/.
• To download free HDL Simulator evaluation, go to www.aldec.com/downloads/.
• To see some chapters from the books, go to www.trusster.com/books/.
• To download TealnTruss, go to www.trusster.com/downloads/.
www.aldec.com
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