System Level Design
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Controller
Data path devices
Functional partition
ASM Charts
Application of the One-Hot Method to a Serial
2’s Complementer
 Design of a Parallel-to-Serial Adder/Subtractor
Control System
 One-Hot Design of a Parallel-to-Serial
Adder/Subtractor Controller
 Design of a Stepping Motor Control System
Prepared By
AJIT SARAF
Introduction
 One very common view of a digital system is the
use of an FSM as the controller for a set of
components parts that comprise the controlled
system called the data path.
Controller/data-path architecture for digital system design.
Sanity
 Sanity is an active low reset input for reset purpose
connected to CLR pin of flip-flops.
 Sanity circuit: a circuit that is used to initialize an FSM
Into a particular state, usually a resistor/capacitor (R-C)
type circuit. (Power on Reset circuit)
Data path devices
 Consist of a mixture of both sequential and
combinational logic machines.
 Registers
 Counters
 ALUs
 PLDs of various types
 Decoders
 MUXs
 Shifters
 Comparators
 Digital-to-analog (D/A) converters
Controller for a digital system
 FSM
 “Brains" of the system.
 Coordinate precisely the operation of the
various components of the data path so as to
perform the specific tasks required by the
system.
 Thus, the controller must issue instructions
(control signals) to the data path unit (DPU)
based on the external inputs it receives and on
the feedback information received from the DPU.
 handshake interface: Output of one unit are the
inputs to another, and vice versa.
Controller for a digital system
 Feedback from the DPU is not a requirement for
all systems, but is common in most.
 Controller and data path devices may receive
signals from and issue signals to the outside
world.
Designing a complex digital system
 Requires a "divide-and-conquer" approach.
 The system must be divided into subsystems
that in turn must be broken down into welldefined parts that can be implemented with
available hardware.
 The detailed block diagram that conveys this
information is appropriately called the functional
partition of the system.
Functional partition
 It contains
 Block representation of the controller (FSM)
 All the peripheral devices that constitute the
DPU
 All inputs from and outputs to the outside
world and
 The I/O conditioning circuits.
 Consequently, the functional partition contains all
the information needed for "hookup" and
operation of the system given the details of the
controller design, which must be treated as an
integral part of the design process.
ASM Charts
 Flowchart functions as a useful thinking tool in
the construction of the state diagram.
 ASM chart also serve as a useful thinking tool.
 Both are very similar
 The ASM chart being the more useful in creating
VHDL FSM descriptions.
ASM Charts
 The state block symbol in Fig. is used to give
 The state identifier,
 The state code assignment (if known), and
 A listing of all unconditional (Moore) outputs
associated with that state.
State block symbol and list of unconditional (Moore) Outputs
ASM Charts
 The decision symbol in Fig. a contains the input
conditions on which depend the branching from a
given state.
 To assist in creating a VHDL description of the
FSM, a separate symbol is provided for conditional
(Mealy) outputs. as indicated in Fig. b.
(a) Decision symbol showing true and false exit condition paths.
(b) Conditional output symbol and list of Mealy outputs.
ASM Charts
Example of an ASM block and its link paths
Application of the One-Hot Method to a Serial 2’s Complementer
 The functional partition and a detailed flowchart or
ASM chart (Algorithmic State Machine) for the controller
of a digital system are usually interdependent and must
be developed together.
Block symbol of complementer
ASM Chart
Application of the One-Hot Method to a Serial 2’s Complementer
State Diagram
Output Expressions
Logic circuit for the serial 2's complementer derived
directly from either the ASM chart or the state diagram.
Designing a complex digital system
 For a complex digital system this development
process may require two or more attempts at
representing the functional partition and flowchart
or ASM chart before satisfactory representations
can be found.
 Simple block diagrams are often useful in this
process, since they can provide a physical
picture of the overall system.
Designing a complex digital system
 The use of timing diagrams is usually a
necessary pan of the development stages of the
design process.
 In some designs, timing considerations are of
paramount importance.
Timing Diagram
Designing a complex digital system
 Finally, remember that a flowchart or ASM chart
is considered to be only a "thinking tool" for the
construction of the state diagram or state table
from which the controller is designed.
Designing a complex digital system
 The success of the design will usually depend on
 The engineering creativity,
 Intuition (Something is true even when you
have no evidence or proof of it)
 generally the experience of the digital
designer.
 But the manner in which a digital system is to
operate in a particular environment can also be
an important factor.
 e.g. Stepping motor control system for small
Robotic arm & Elevator. (Mass, time & distance)
Designing
 Design
of-parallel-to-serial
Adder/subtractor
control system.
 Design of stepping motor control system.
 Perspective on system level design.
Design of a Parallel-to-Serial Adder/Subtractor Control System
Functional partition for the Parallel-to-Serial adder/subtractor system (Data Path devices)
Design of a Parallel-to-Serial Adder/Subtractor Control System
Functional partition for the Parallel-to-Serial adder/subtractor system (Data Path devices)
Design of a Parallel-to-Serial Adder/Subtractor Control System
Functional partition for the Parallel-to-Serial adder/subtractor system (Controller)
One-Hot Design of a Parallel-to-Serial Adder/Subtractor Controller
State
State Diagram using one-hot-plus-zero approach
Values or Operation
a
LDCNT
CLREG
Start
b
PSCRY (Sub)
CLCRY (Add)
S1 = 1, S0 = 1 (Parallel load)
Start’
c
S1 = 0, S0 = 1 (Right Shift)
CMPL for complement of B (Sub)
CNT (Up / Down)
FIN (if CNT = 8)
One-Hot Design of a Parallel-to-Serial Adder/Subtractor Controller
Output Expressions
IC Name
IC No.
No of Gates
Input Pins
2 Input AND
7408
9
18
3 Input AND
7409
1
3
2 Input OR
7432
2
4
1
3
13
28
3 Input OR
Total
IC & Gate Requirement
One-Hot Design of a Parallel-to-Serial Adder/Subtractor Controller
Symbolic representation of the fusible bit position patterns for FPLA
Design of a Parallel-to-Serial Adder/Subtractor Controller
Output Expressions
State Diagram suitable for a conventional
controller design
Design of a Parallel-to-Serial Adder/Subtractor Controller
Output Expressions
IC Name
IC No.
No of Gates
Input Pins
2 Input AND
7408
4
8
3 Input AND
7409
2
6
6
14
Total
IC & Gate Requirement
Design of a Parallel-to-Serial Adder/Subtractor Controller
Timing Diagram for 8-bit subtraction showing input signals to and
output signals from the controller
Design of a Parallel-to-Serial Adder/Subtractor Controller
NS K-maps and minimum cover for a JK Flip-Flop design
Design of a Parallel-to-Serial Adder/Subtractor Controller
Output forming logic showing minimum cover.
Parallel-to-Serial Adder/Subtractor controller
Logic minimum design of the Parallel-to-Serial adder/subtractor controller of by using JK flip-flops.
Design of a Stepping Motor Control System
 Stepping motors convert a series of pulses
into angular motion that permits very accurate
positioning of the motor's rotor without feedback
control.
 Stepping motors are useful in systems where
there is space only for a small motor to drive a
relatively massive part.
 Linear angular accelerations and decelerations of
the motor can prevent slippage, chattering, or
jerky motion that could lead to mechanical
failure or adversely affect mechanical operation.
 Stepping motors exhibit zero steady-state error
positioning and can develop torque up to 15 Nm.
Design of a Stepping Motor Control System
 Applications
 Robotics to accurately operate mechanical
parts in some manner.
 Fluid control systems for precise adjustment
of fluid control valves.
 Wire-wrap processing of circuit boards (60’s
and 70’s)
 Stepping motors will accept pulse strings in the
range of 1500 to 2500 pulses per second.
Overall operational characteristics of the stepping motor control system
Angular velocity vs time requirements of the control system.
Overall operational characteristics of the stepping motor control system
Input controls, STEP pulse train required for linear angular acceleration, and register
outputs to stepping motor.
Overall operational characteristics of the stepping motor control system
4-Bit SIPO Shift Register
Overall operational characteristics of the stepping motor control system
Acceptable timing relationships between synchronized external inputs and STEP pulse
signals to the stepping motor.
Functional partition for the stepping motor control system
D flip-flop design of the divide-by-2 counter
ASM Chart
State Diagram
P-term table for the PLA implementation of the NS and output functions of the stepping motor controller
Architecture for the stepping motor controller centered around an FPLA and showing input conditioning
and clock generation Circuitry
Implementation of the 4-bit, data-triggered up/down binary counter with asynchronous
parallel load
(a) Logic circuit for the Jth stage showing the CO and BO output logic, where the NS functions Tj(H)
are given by Eqs (b) Block circuit symbol.
Implementation of the 4-bil up/down binary counter with asynchronous parallel load.
(a) Logic circuit for the Jth stage with CO and BO logic (b) Block circuit symbol.
State diagram for a cascadable up/down binary counter