Entity declaration for the 2-to-4
decoder circuit.
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entity DECODER2×4 is
Port (A, B, ENABLE: in BIT;
Z:out BIT_VECTOR(0 to 3));
end DECODER2×4;
BIT_VECTOR is a predefined
unconstrained array type of BIT.
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Dataflow model of HALF_ADDER
described usig two concurrent
signal assignment statements.
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Architecture of full adder
entity name port names
port mode (direction)
punctuation
port type
reserved words
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In the structural style of modeling, an entity
is described as a set of interconnected
components
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A component instantiation
statement is a concurrent
statement .
The order of these statements is
not important.
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Architecture of the DECODER2×4
using structural representation
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entity DECODER2×4 is
Port (A, B, ENABLE: in BIT;
Z:out BIT_VECTOR(0 to 3));
end DECODER2×4;
BIT_VECTOR is a predefined
unconstrained array type of BIT.
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Dataflow model for the DECODER2×4 entity
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The architecture body consists of
one signal declaration and six
concurrent signal assignment
statements.
If no after clause is used then
default delay of 0 ns is used.
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Behavioral Style of Modeling
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In structural style of modeling and dataflow
style of modeling the behavior of an entity
is specified as a set of statements that are
executed concurrently in the specified
order
But in behavioral style of modeling the behavior
of an entity is specified as a set of statements
that are executed sequentially in the
specified order
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In behavioral style of modeling the
sequential statements specified
inside the process statement do not
explicitly specify the structure of
entity but merely its functionality.
A process statement is a concurrent
statement that can appear within an
architecture body.
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A variable is assigned a value
instantaneously, but a signal is
assigned value after some delay (User
specified or the delta delay)
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A signal can represent not only a wire but
also a place holder for a value and it can be
used to model a D flip flop.
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Mixed Style of Modeling
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The full-adder is represented using one
component instantiation statement, one process
statement and one concurrent signal assignment
statement.
All these statements are concurrent statements;
therefore, their order of appearance within the
architecture body is not important.
Process statement itself is a concurrent
statement; however, statements within a process
statement are always executed sequentially.
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The after clause may be used to
generate a clock signal, as shown
in signal assignment;
CLK <= not CLK after 10 ns;
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Process statement to generate clock with different
on-off period
process
begin
CLK <=‘o’;
wait for 20 ns;
CLK <=‘1’;
wait for 12 ns;
end process;
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