Lecture 11:
Sequential
Circuit
Design
Outline






Sequencing
Sequencing Element Design
Max and Min-Delay
Clock Skew
Time Borrowing
Two-Phase Clocking
11: Sequential Circuits
CMOS VLSI Design 4th Ed.
2
Sequential Logic
11: Sequential Circuits
CMOS VLSI Design 4th Ed.
3
Sequencing
 Combinational logic
– output depends on current inputs
 Sequential logic
– output depends on current and previous inputs
– Requires separating previous, current, future
– Called state or tokens
– Ex: FSM, pipeline
clk
in
clk
clk
clk
out
CL
Finite State Machine
11: Sequential Circuits
CL
CL
Pipeline
CMOS VLSI Design 4th Ed.
4
Sequencing Cont.
 If tokens moved through pipeline at constant speed,
no sequencing elements would be necessary
 Ex: fiber-optic cable
– Light pulses (tokens) are sent down cable
– Next pulse sent before first reaches end of cable
– No need for hardware to separate pulses
– But dispersion sets min time between pulses
 This is called wave pipelining in circuits
 In most circuits, dispersion is high
– Delay fast tokens so they don’t catch slow ones.
11: Sequential Circuits
CMOS VLSI Design 4th Ed.
5
Sequencing Overhead
 Use flip-flops to delay fast tokens so they move
through exactly one stage each cycle.
 Inevitably adds some delay to the slow tokens
 Makes circuit slower than just the logic delay
– Called sequencing overhead
 Some people call this clocking overhead
– But it applies to asynchronous circuits too
– Inevitable side effect of maintaining sequence
11: Sequential Circuits
CMOS VLSI Design 4th Ed.
6
Sequencing Elements
Flop
Latch
 Latch: Level sensitive
– a.k.a. transparent latch, D latch
 Flip-flop (or Register): edge triggered
– A.k.a. master-slave flip-flop, D flip-flop, D register
 Timing Diagrams
clk
clk
– Transparent
D
Q
D
Q
– Opaque
– Edge-trigger
clk
D
Q (latch)
Q (flop)
11: Sequential Circuits
CMOS VLSI Design 4th Ed.
7
Latch versus Register

Latch
stores data when
clock is low

Register
stores data when
clock rises
D Q
D Q
Clk
Clk
Clk
Clk
D
D
Q
Q
CMOS VLSI Design 4th Ed.
Latches
11: Sequential Circuits
CMOS VLSI Design 4th Ed.
9
Timing Definitions
CLK
t
tsu
D
D
thold
DATA
STABLE
Q
CLK
t
tc 2
Q
Register
q
DATA
STABLE
CMOS VLSI Design 4th Ed.
t
Characterizing Timing
11: Sequential Circuits
CMOS VLSI Design 4th Ed.
11
Latch Design
 Pass Transistor Latch
 Pros
+ Tiny
+ Low clock load
 Cons
– Vt drop
– nonrestoring
– backdriving
– output noise sensitivity
– dynamic
– diffusion input
11: Sequential Circuits
CMOS VLSI Design 4th Ed.

D
Q
Used in 1970’s
12
Latch Design
 Transmission gate
+ No Vt drop
- Requires inverted clock

D
Q

11: Sequential Circuits
CMOS VLSI Design 4th Ed.
13
Latch Design
 Inverting buffer
+ Restoring
+ No backdriving
+ Fixes either
• Output noise sensitivity
• Or diffusion input
– Inverted output
11: Sequential Circuits
CMOS VLSI Design 4th Ed.

X
D

Q

D
Q

14
Latch Design
 Tristate feedback
+ Static
– Backdriving risk

X
D

 Static latches are now essential
because of leakage
11: Sequential Circuits
CMOS VLSI Design 4th Ed.
Q


15
Latch Design
 Buffered input
+ Fixes diffusion input
+ Noninverting

X
D

Q


11: Sequential Circuits
CMOS VLSI Design 4th Ed.
16
Latch Design
 Buffered output
+ No backdriving

X
D

 Widely used in standard cells
+ Very robust (most important)
- Rather large
- Rather slow (1.5 – 2 FO4 delays)
- High clock loading
11: Sequential Circuits
CMOS VLSI Design 4th Ed.
Q


17
Latch Design
 Datapath latch
+ smaller
+ faster
- unbuffered input

Q
X
D



11: Sequential Circuits
CMOS VLSI Design 4th Ed.
18
Flip-Flop Design
 Flip-flop is built as pair of back-to-back latches


X
D
Q




X
D

Q


11: Sequential Circuits
Q



CMOS VLSI Design 4th Ed.
19
Enable
 Enable: ignore clock when en = 0
– Mux: increase latch D-Q delay
– Clock Gating: increase en setup time, skew
Symbol
Multiplexer Design
Clock Gating Design
 en
D
1
Q
0
en
Q
D
 en
1
0
Q
Q
D
en
Flop
D
Flop

Flop
Q
en

D
Latch

Latch
D
Latch

Q
en
11: Sequential Circuits
CMOS VLSI Design 4th Ed.
20
Reset
 Force output low when reset asserted
 Synchronous vs. asynchronous

Q
D
reset
Synchronous Reset

Q

reset
D

Q
Q







Asynchronous Reset
Q


Q


reset
reset
D
D






reset
reset

11: Sequential Circuits
Q
reset

reset
D
Flop
Symbol
D
Latch


CMOS VLSI Design 4th Ed.

21
Set / Reset
 Set forces output high when enabled
 Flip-flop with asynchronous set and reset


reset
set
D



Q

set
reset

11: Sequential Circuits

CMOS VLSI Design 4th Ed.
22
Sequencing Methods
clk
clk
Combinational Logic
tnonoverlap
Combinational
Logic
1
Combinational
Logic
Latch
2
Latch
1
Half-Cycle 1
tpw
CMOS VLSI Design 4th Ed.
p
Combinational Logic
Latch
p
Latch
Pulsed Latches
p
tnonoverlap
Tc/2
2
Latch
2-Phase Transparent Latches
1
Half-Cycle 1
11: Sequential Circuits
Flop
clk
Flop
Flip-Flops
 Flip-flops
 2-Phase Latches
 Pulsed Latches
Tc
23
Timing Diagrams
Contamination and
Propagation Delays
A
A
tpd
Logic Prop. Delay
tcd
Logic Cont. Delay
tpcq
Latch/Flop Clk->Q Prop. Delay
tccq
Latch/Flop Clk->Q Cont. Delay
tpdq
Latch D->Q Prop. Delay
tcdq
Latch D->Q Cont. Delay
tsetup
Latch/Flop Setup Time
thold
Combinational
Logic
Y
Y
clk
Flop
clk
D
Q
tcd
tsetup
thold
D
tpcq
Q
Latch
D
tccq
clk
clk
tccq
Q
Latch/Flop Hold Time
11: Sequential Circuits
tpd
tsetup
tpcq
D
tcdq
thold
tpdq
Q
CMOS VLSI Design 4th Ed.
24
Max-Delay: Flip-Flops
sequencing overhead
clk
Q1
Combinational Logic
D2
F2
clk
F1
t pd  T c   t setup  t pcq 
Tc
clk
Q1
tsetup
tpcq
tpd
D2
11: Sequential Circuits
CMOS VLSI Design 4th Ed.
25
Max Delay: 2-Phase Latches
D1
sequencing overhead
Q1
Combinational
Logic 1
D2
1
Q2
Combinational
Logic 2
D3
L3
pdq
2
L2
 2t 
L1
t pd  t pd 1  t pd 2  T c 
1
Q3
1
2
Tc
D1
Q1
tpdq1
tpd1
D2
tpdq2
Q2
tpd2
D3
11: Sequential Circuits
CMOS VLSI Design 4th Ed.
26
Max Delay: Pulsed Latches
D1
p
Q1
D2
Combinational Logic
L2
p
L1
t pd  T c  m ax  t pdq , t pcq  t setup  t pw 
Q2
sequencing overhead
Tc
D1
(a) tpw > tsetup
tpdq
Q1
tpd
D2
p
tpcq
Q1
Tc
tpd
tpw
tsetup
(b) tpw < tsetup
D2
11: Sequential Circuits
CMOS VLSI Design 4th Ed.
27
Min-Delay: Flip-Flops
clk
F1
t cd  t hold  t ccq
Q1
CL
clk
F2
D2
clk
Q1 tccq
D2
11: Sequential Circuits
tcd
thold
CMOS VLSI Design 4th Ed.
28
Min-Delay: 2-Phase Latches
1
L1
t cd 1, t cd 2  t hold  t ccq  t nonoverlap
1
L2
D2
Paradox: hold applies
twice each cycle, vs.
only once for flops.
tnonoverlap
tccq
2
Q1
D2
11: Sequential Circuits
CL
2
Hold time reduced by
nonoverlap
But a flop is made of
two latches!
Q1
tcd
thold
CMOS VLSI Design 4th Ed.
29
Min-Delay: Pulsed Latches
p
Q1
CL
p
D2
p
L2
Hold time increased
by pulse width
L1
t cd  t hold  t ccq  t pw
tpw
thold
Q1 tccq
tcd
D2
11: Sequential Circuits
CMOS VLSI Design 4th Ed.
30
Itanium 2 ALU
11: Sequential Circuits
CMOS VLSI Design 4th Ed.
31
Combinational Logic Delays
Element
Propagation Delay
Contamination Delay
Adder
590 ps
100 ps
Result Mux
60 ps
35 ps
Early Bypass Mux
110 ps
95 ps
Middle Bypass Mux
80 ps
55 ps
Late Bypass Mux
70 ps
45 ps
2 mm Wire
100 ps
65 ps
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CMOS VLSI Design 4th Ed.
32
Time Borrowing
 In a flop-based system:
– Data launches on one rising edge
– Must setup before next rising edge
– If it arrives late, system fails
– If it arrives early, time is wasted
– Flops have hard edges
 In a latch-based system
– Data can pass through latch while transparent
– Long cycle of logic can borrow time into next
– As long as each loop completes in one cycle
11: Sequential Circuits
CMOS VLSI Design 4th Ed.
33
Time Borrowing Example
1
2
Combinational Logic
Borrowing time across
half-cycle boundary
Combinational
Logic
Borrowing time across
pipeline stage boundary
2
Combinational Logic
Latch
(b)
Latch
1
1
Latch
2
Latch
(a)
Latch
1
Combinational
Logic
Loops may borrow time internally but must complete within the cycle
11: Sequential Circuits
CMOS VLSI Design 4th Ed.
34
How Much Borrowing?
2
  t setup  t nonoverlap 
D1
L1
t borrow 
Tc
1
2
Q1
Combinational Logic 1
D2
L2
2-Phase Latches
Q2
1
Pulsed Latches
2
t borrow  t pw  t setup
tnonoverlap
Tc
Tc/2
Nominal Half-Cycle 1 Delay
tborrow
tsetup
D2
11: Sequential Circuits
CMOS VLSI Design 4th Ed.
35
Clock Skew
 We have assumed zero clock skew
 Clocks really have uncertainty in arrival time
– Decreases maximum propagation delay
– Increases minimum contamination delay
– Decreases time borrowing
11: Sequential Circuits
CMOS VLSI Design 4th Ed.
36
Skew: Flip-Flops
sequencing overhead
Q1
F1
t pd  T c   t pcq  t setup  t skew 
clk
Combinational Logic
D2
F2
clk
Tc
clk
tpcq
t cd  t hold  t ccq  t skew
Q1
tskew
tpdq
tsetup
D2
F1
clk
Q1
CL
D2
F2
clk
tskew
clk
thold
Q1 tccq
D2
11: Sequential Circuits
tcd
CMOS VLSI Design 4th Ed.
37
Skew: Latches
 2t 
2
c
D2
Q2
Combinational
Logic 2
D3
Q3
2
  t setup  t nonoverlap  t skew 
Pulsed Latches
t  T  m ax  t , t
pd
Combinational
Logic 1
1
t cd 1 , t cd 2  t hold  t ccq  t nonoverlap  t skew
Tc
Q1
1
pdq
sequencing overhead
t borrow 
2
L3
D1
L1
t pd  T c 
1
L2
2-Phase Latches
pdq
pcq
 t setup  t pw  t skew 
sequencing overhead
t cd  t hold  t pw  t ccq  t skew
t borrow  t pw   t setup  t skew 
11: Sequential Circuits
CMOS VLSI Design 4th Ed.
38
Two-Phase Clocking
 If setup times are violated, reduce clock speed
 If hold times are violated, chip fails at any speed
 In this class, working chips are most important
– No tools to analyze clock skew
 An easy way to guarantee hold times is to use 2phase latches with big nonoverlap times
 Call these clocks 1, 2 (ph1, ph2)
11: Sequential Circuits
CMOS VLSI Design 4th Ed.
39
Safe Flip-Flop
 Past years used flip-flop with nonoverlapping clocks
– Slow – nonoverlap adds to setup time
– But no hold times
 In industry, use a better timing analyzer
– Add buffers to slow signals if hold time is at risk


X
D

Q


11: Sequential Circuits
Q



CMOS VLSI Design 4th Ed.
40
Adaptive Sequencing
p
X
 Designers include timing margin
ERR
– Voltage
D
Q
– Temperature

– Process variation
D
Q
– Data dependency
X
– Tool inaccuracies
ERR
 Alternative: run faster and check for near failures
– Idea introduced as “Razor”
• Increase frequency until at the verge of error
• Can reduce cycle time by ~30%
p
11: Sequential Circuits
CMOS VLSI Design 4th Ed.
41
Conventional CMOS Latches
11: Sequential Circuits
CMOS VLSI Design 4th Ed.
42
More CMOS Latches
11: Sequential Circuits
CMOS VLSI Design 4th Ed.
43
Clocked CMOS Latches
 Sometimes called C2MOS
 Actually, similar to (d) in that it is tristate
11: Sequential Circuits
CMOS VLSI Design 4th Ed.
44
Conventional CMOS Flip-Flops
11: Sequential Circuits
CMOS VLSI Design 4th Ed.
45
CMOS Flip-Flops
 This design has a potential race condition.
 Is more likely if there is skew between the two
phases of the clock.
 One alternative is NORA (NO Race) flip-flop.
 The other alternative is to use non-overlapping
clocks.
11: Sequential Circuits
CMOS VLSI Design 4th Ed.
46
NORA Flip-flops
11: Sequential Circuits
CMOS VLSI Design 4th Ed.
47
NORA Flip-flops
11: Sequential Circuits
CMOS VLSI Design 4th Ed.
48
Pulse Generators
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CMOS VLSI Design 4th Ed.
49
Pulsed Latches
 The Naffziger pulsed latch is used in Itanium 2
processors. It consists of the latch from (k) and the
generator from (b). The pulse width is 1/6 the clock
cycle.
 The pulse generator of (d) is used in the NEC RISC
processor.
 Note that pulses are very fast and have to be
distributed in the latch.
 The Partovi pulsed latch (used on the AMD K6 and
Athlon) builds the pulse generator into the latch.
11: Sequential Circuits
CMOS VLSI Design 4th Ed.
50
Pulsed Latches
11: Sequential Circuits
CMOS VLSI Design 4th Ed.
51
Resettable Latches and Flip-flops
 There are two types of reset:
– Asynchronous
– Synchronous
 Settable latches and flip-flops force the output high
rather than low.
11: Sequential Circuits
CMOS VLSI Design 4th Ed.
52
Resettable Latches and Flip-flops
11: Sequential Circuits
CMOS VLSI Design 4th Ed.
53
Asynchronous Set and Reset
11: Sequential Circuits
CMOS VLSI Design 4th Ed.
54
Enabled Latches and Flip-flops
11: Sequential Circuits
CMOS VLSI Design 4th Ed.
55
Logic in Latches
 The sequencing overhead can be reduced by
incorporating logic into latches.
 The DEC Alpha 21164 used a whole assortment of
such latches.
11: Sequential Circuits
CMOS VLSI Design 4th Ed.
56
Klass Semidynamic FF (SDFF)
 A cross between pulsed latch and a flip-flop.
 Used in Sun UltraSparc III along with built in logic.
11: Sequential Circuits
CMOS VLSI Design 4th Ed.
57
SDFF




Similar to the Partovi pulsed latch.
However, it uses a dynamic NAND gate.
Faster than the Partovi pulsed latch.
Worse skew tolerance and time borrowing capability.
11: Sequential Circuits
CMOS VLSI Design 4th Ed.
58
Differential Flip-flops
11: Sequential Circuits
CMOS VLSI Design 4th Ed.
59
Differential Flip-flops
 The design in (a) was used in the Alpha 21164.
 The SR latch formed by the NAND gates is just a
salve and can be replaced by inverters if necessary.
 The StrongArm 110 processor adds the weak nMOS
transistor to reduce the risk when the inputs switch
while the clock is high.
 The AMD K6 uses the design in (b) at the interface
between static and domino logic.
11: Sequential Circuits
CMOS VLSI Design 4th Ed.
60
Dual Edge Triggered FFs
 DET flip flops have a similar thoroughput at half the
clock frequency.
11: Sequential Circuits
CMOS VLSI Design 4th Ed.
61
DET FFs
 Zhao implicitly pulsed DET FF.
11: Sequential Circuits
CMOS VLSI Design 4th Ed.
62
Radiation Hardened FFs
11: Sequential Circuits
CMOS VLSI Design 4th Ed.
63
Some Design Guides
 Dynamic latches and registers have been avoided
since the 0.35 mm technology node.
– Use static latches and register.
 Include provisions for testing
– We will study these later.
 Clock distribution, especially multiple phases are
problematic.
– We will study later.
 Unless required performance is at the cutting edge,
use registers.
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CMOS VLSI Design 4th Ed.
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Some Design Guides
 Pulsed latches are best in terms of performance.
– Remember that they have long hold times.
 Extra circuitry may be necessary for short logic
paths.
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CMOS VLSI Design 4th Ed.
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Characterizing Delays
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CMOS VLSI Design 4th Ed.
66
Characterizing Delays
 The set-up time cannot be crisply defined.
 If the data changes slightly less than a set-up time
before the clock edge, the register will still capture
the correct value, but its clock-Q delay will be high.
 Note that t DQ  t DC  t CQ
 tDQ has a minimum when the slope of tCQ is -1.
 tsetup is defined as the tDC at this point.
 The
 propagation delay is the tCQ at this point.
 The contamination delay tccq is the minimum tCQ that
occurs when the input arrives early.
 The hold time is the minimum delay from clock to D
11: Sequential Circuits
CMOS VLSI Design 4th Ed.
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Characterizing Delays
11: Sequential Circuits
CMOS VLSI Design 4th Ed.
68
Characterizing Delays
 The aperture width, ta is the width of the window
around the clock edge during which the data must
not transition if the register is to produce the correct
output with a propagation delay less than tpcq.
t ar  t setup 1  t hold 0
t af  t setup 0  t hold 1

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Characterizing Delays
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CMOS VLSI Design 4th Ed.
70
Characterizing Delays
 If the data arrives before the clock rises (tDCr > 0), it
must wait for the clock.
 In this region, tCrQ is nearly constant and tDQ
increases as the data arrives earlier.
 If the data arrives after the clock rises, tDQ is
essentially independent of arrival time.
 The data must set up before the falling edge of the
clock.
 If the data arrives too close to the falling edge, tDQ
increases.
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CMOS VLSI Design 4th Ed.
71
Characterizing Delays
 Choose the setup time before the knee of the curve,
for example 5% greater than its minimum value.
 Pulsed latches have different definitions, but they
can be converter to ordinary latches by adding or
subtracting pulse widths.
t setup  virtual  t setup  t pw

t pcq  virtual  t pdq  t pw  t setup

t pdq  virtual  t setup  virtual  t pcq  virtual  t pdq
t hold  virtual  t hold  t pw
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Delay Trade-offs
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CMOS VLSI Design 4th Ed.
73
State Retention Registers
11: Sequential Circuits
CMOS VLSI Design 4th Ed.
74
Level Conversion
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CMOS VLSI Design 4th Ed.
75
Design Margins
 Designers derate their circuits by about 30% to cope
with variations.
 Adaptive sequential elements seek to reduce this
margin.
 Dynamic voltage scaling
– Precharacterize the circuit
– Canary circuit
– Double sampling the input
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Adaptive Sequencing
11: Sequential Circuits
CMOS VLSI Design 4th Ed.
77
Adaptive Sequencing
 (a) shows the conceptual diagram of a razor flip-flop,
while (b) is the timing diagram.
 The razor flip-flop has the drawback that it may
become metastable if D changes during the
aperture.
 An improvement is double sampling with time
borrowing (DSTB).
 (d) shows the Razor II pulsed latch.
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CMOS VLSI Design 4th Ed.
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Synchronizers
 A synchronizer is a circuit that accepts an input that
can change at arbitrary times and produces an
output aligned to its clock.
 This is impossible to do in a finite time.
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CMOS VLSI Design 4th Ed.
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Metastability
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CMOS VLSI Design 4th Ed.
80
Metastability
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CMOS VLSI Design 4th Ed.
81
Metastability
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CMOS VLSI Design 4th Ed.
82
Metastability
 The cross-coupled inverters behave like an amplifier
with gain G when A is near the metastable voltage
Vm.
 The delay can be modeled with an RC network.
 Let the initial voltage be A and a small offset from
the metastable point be a(0).
A 0   V m  a 0 
Ga  t   a t 
C
R
a  t   a 0 e
s 
11: Sequential Circuits
t
da  t 
dt
s
RC
G 1
CMOS VLSI Design 4th Ed.
83
Metastability
 Assume that the node reaches a legal logic level
when a t    V
 The time to reach this level is

t DQ   s ln V  ln a 0 
 Note that the speed is given by the RC time
constant.
 GBW is required.
 High
T0  t  s
P t DQ  t  
e
Tc

11: Sequential Circuits

CMOS VLSI Design 4th Ed.
84
Synchronizers
11: Sequential Circuits
CMOS VLSI Design 4th Ed.
85
Synchronizers
11: Sequential Circuits
CMOS VLSI Design 4th Ed.
86
Synchronizers
 The probability of a synchronizer failure is
P  failure
 N
T0
Tc

T c  t setup 
s
e
 The mean time between failures is
T c  t setup

MTBF 
1
P  failure


Tc e
s
NT 0

11: Sequential Circuits
CMOS VLSI Design 4th Ed.
87
Degrees of Synchrony
Classification
Periodic

f
Description
Synchronous
Yes
0
0
Signal has same frequency and phase
as clock.
Example: register to register on chip.
Mesosynchronous
Yes
Constant
0
Signal has same frequency, but is out
of phase with clock. Safe to sample by
delaying.
Example: chip tp chip where both
chips are using the same clock.
Plesiosynchronous
Yes
Varies
slowly
Small
Signal has nearly the same frequency.
Phase drifts slowly with time. Safe to
sample signal if it is delayed by a
variable, but predictable amount.
Example: Board to board with same
frequency but different crystals.
Periodic
Yes
Varies
rapidly
Large
Signal is periodic at arbitrary
frequency. Board to board with
different crystals.
Asynchronous
No
Unknown
Unknown
Signal changes arbitrarily.
11: Sequential Circuits
CMOS VLSI Design 4th Ed.
88
Asynchronous Domains
11: Sequential Circuits
CMOS VLSI Design 4th Ed.
89
Asynchronous Domains
11: Sequential Circuits
CMOS VLSI Design 4th Ed.
90
Two-Phase Handshake
11: Sequential Circuits
CMOS VLSI Design 4th Ed.
91
Arbiters
 An arbiter decides which of the two inputs came first.
11: Sequential Circuits
CMOS VLSI Design 4th Ed.
92
Pipelining
11: Sequential Circuits
CMOS VLSI Design 4th Ed.
93
Wave Pipelining
11: Sequential Circuits
CMOS VLSI Design 4th Ed.
94
Schmitt Triggers
11: Sequential Circuits
CMOS VLSI Design 4th Ed.
95
Noise Suppression
11: Sequential Circuits
CMOS VLSI Design 4th Ed.
96
CMOS Schmitt Trigger
11: Sequential Circuits
CMOS VLSI Design 4th Ed.
97
Schmitt Trigger Simulated VTC
2.5
2.5
2.0
2.0
VM1
1.5
(V)
1.0
X
V
1.5
(V)
1.0
x
V
VM2
0.5
0.0
0.0
k=1
k=3
k=2
0.5
0.5
1.0
1.5
Vin (V)
2.0
2.5
Voltage-transfer characteristics with hysteresis.
k=4
0.0
0.0
0.5
1.0
1.5
2.0
2.5
Vin (V)
The effect of varying the ratio of the
PMOS device M4. The width is k* 0.5 m.
m
CMOS VLSI Design 4th Ed.
CMOS Schmitt Trigger 2
11: Sequential Circuits
CMOS VLSI Design 4th Ed.
99
Multivibrator Circuits
R
S
B is ta b le M u ltiv ib ra to r
flip -flo p , S ch m itt T rig g e r
T
M o n o s ta b le M u ltiv ib ra to r
o n e -sh o t
A s ta b le M u ltiv ib ra to r
o scilla to r
CMOS VLSI Design 4th Ed.
Transition-Triggered Monostable
In
DELAY
Out
td
td
CMOS VLSI Design 4th Ed.
Monostable Trigger (RC-based)
VD D
R
In
A
B
O ut
(a ) T r ig ge r c ir cu it.
C
In
B
VM
Out
(b) W av efo r m s.
t
t1
t2
CMOS VLSI Design 4th Ed.
Astable Multivibrators (Oscillators)
11: Sequential Circuits
CMOS VLSI Design 4th Ed.
103
Relaxation Oscillator
O u t1
O u t2
I2
I1
R
C
In t
T = 2 (log3) R C
CMOS VLSI Design 4th Ed.
Voltage Controller Oscillator (VCO)
VDD
VD D
M6
M4
S chm itt T rigger
restores signal slopes
M2
In
M1
Ir e f
V c on tr
Ir e f
M3
M5
C u rren t s tarved inve rter
t p H L ( ns ec )
6
4
2
0.0
0.5
1.5
2.5
propagation delay as a function
of control voltage
V c o n t r (V )
CMOS VLSI Design 4th Ed.
Differential Delay Element and VCO
in 2
Vo 2
v3
V o1
v1
in 1
v2
Vctrl
v
4
two stage VCO
3.0
delay cell
2.5
V1 V 2 V 3 V4
2.0
1.5
1.0
0.5
0.0
2 0.5
0.5
1.5
2.5
3.5
time (ns)
simulated waveforms of 2-stage VCO
CMOS VLSI Design 4th Ed.
Pitfalls and Fallacies
 Incompletely reporting flip-flop delay.
 Failing to check hold times.
 Choosing a sequencing method too late in the
design.
 Failing to synchronize asynchronous inputs.
 Building faulty synchronizers.
11: Sequential Circuits
CMOS VLSI Design 4th Ed.
107
Summary
 Flip-Flops:
– Very easy to use, supported by all tools
 2-Phase Transparent Latches:
– Lots of skew tolerance and time borrowing
 Pulsed Latches:
– Fast, some skew tol & borrow, hold time risk
11: Sequential Circuits
CMOS VLSI Design 4th Ed.
108