Digital Integrated Circuits for
Communication
Class 01
Course Contents
• Dynamic CMOS design; dynamic logic: Basic
principles, speed and power dissipation of
dynamic logic, issues in dynamic design,
cascading dynamic gates.
• Static latches and registers; bistability
principle;
Course Contents
• Multiplexer-based latches; low-voltage static
latches;
• Static SR Flip-Flops – writing data by pure
force;
• dynamic latches and registers; dynamic
transmission; C2MOS – clock-skew insensitive
approach; true single-phase clocked register
(TSPCR); alternative register styles;
Course Contents
• Pulse registers,
• Sense-amplifier based registers; pipelining: an
approach to optimize sequential circuits;
• Latch- vs. register-based pipelines; NORACMOS – logic style for pipelined structures;
• Non-bistable sequential circuits; Schmitt
trigger; monostable sequential circuits;
astable circuits;
Course Contents
• Memory core; read-only memories;
nonvolatile read-write memories; read write
memories (RAM);
• Contents-addressable or associative memory
(CAM); memory peripheral circuitry; address
decoders; sense amplifiers;
Course Contents
• Voltage references; drivers/buffers; timing and
control; memory reliability and yield;
• signal-to-noise ratio; memory yield; power
dissipation in memories.
Dynamic Logic Circuits
• Dynamic logic is temporary (transient) in that output levels will
remain valid only for a certain period of time
– Static logic retains its output level as long as power is applied
• Dynamic logic is normally done with charging and selectively
discharging capacitance (i.e. capacitive circuit nodes)
– Precharge clock to charge the capacitance
– Evaluate clock to discharge the capacitance depending on
condition of logic inputs
* Kang and Leblebicic, chapter 9
R. W. Knepper
SC571, page 5-55
Dynamic Logic
• Advantages over static logic:
– Avoids duplicating logic twice as both N-tree and P-tree, as in
standard CMOS
– Typically can be used in very high performance applications
– Very simple sequential memory circuits; amenable to
synchronous logic
– High density achievable
– Consumes less power (in some cases)
• Disadvantages compared to static logic:
– Problems with clock synchronization and timing
– Design is more difficult
Dynamic Logic
• The largest difference between static and
dynamic logic is that in dynamic logic,
• a clock signal is used to evaluate
combinational logic.
• in dynamic logic, there is not always a
mechanism driving the output high or low. In
the most common version of this concept, the
output is driven high or low during distinct
parts of the clock cycle.
Dynamic Logic
• Dynamic logic requires a minimum clock rate
fast enough that the output state of each
dynamic gate is used before it leaks out of the
capacitance holding that state, during the part
of the clock cycle that the output is not being
actively driven.
Dynamic Logic
• Dynamic logic, when properly designed, can
be over twice as fast as static logic. It uses
only the faster N transistors, which improve
transistor sizing optimizations.
• Static logic is slower because it has twice the
capacitive loading, higher thresholds, and uses
slow P transistors for logic.
Dynamic Logic
• Dynamic logic can be harder to work with, but
it may be the only choice when increased
processing speed is needed.
• In general, dynamic logic greatly increases the
number of transistors that are switching at
any given time, which increases power
consumption over static CMOS
Dynamic Logic
• The dynamic logic circuit requires two phases.
The first phase, when Clock is low, is called the
setup phase or the precharge phase and the
second phase, when Clock is high, is called the
evaluation phase.
Dynamic Logic
CLK
Mp
Out
A
Me
Evaluate
VOut
Precharge
Leakage sources
Conditions on Output
• Once the output of a dynamic gate is discharged, it
cannot be charged again until the next precharge
operation.
• Inputs to the gate can make at most one transition
during evaluation.
• Output can be in the high impedance state during
and after evaluation
Dynamic Logic
• CMOS Dynamic Two-Phase Flip-Flops
Dynamic Logic
• Disadv: 2 non-overlapping clocks required (4 if
transmission gates are used
• These implementations MUST be simulated at
all process corners (under worst-case
conditions).
Dynamic Logic
• Dynamic CMOS circuits rely on the temporary
storage of signal values on the capacitance of
high-impedance circuit nodes.
• These circuits also have no static power
dissipation and uses a sequence of precharge
and conditional evaluation phases with the
addition of a clock input.
Dynamic Logic (Clock)
Dynamic Logic
• The main advantages of the Dynamic CMOS
logic are increased speed and reduced
implementation area.
• Fewer devices are used to implement a given
logic, this reduces the overall load capacitance
and thus increases the speed.
Static Logic
• The speed of the static CMOS circuit depends
on the transistor sizing and the various
parasitics that are involved with it.
Static Logic
• A Static CMOS gate is a combination of two
networks - the pull-up netowrk (PUN) and the
pull-down network (PDN).
• The function of the PDN is to provide a
connection between the output and Vdd
anytime the output of the logic gate is
supposed to be 1.
• Similarly, the PDN connects the output to Vss
anytime the output is supposed to be 0.
Static Logic
• In Static CMOS design, at every point in time,
each gate output is connected to either Vdd or
Vss via a low-resistance path.
• Also, the outputs of the gate assume at all
times the value of the Boolean function
implemented by the circuit.
Static v.s. Dynamic
• Static Logic Gates
– Valid logic levels are steady-state operating points
– Outputs are generated in response to input voltage levels
after a certain time delay, and it can preserve its output
levels as long as there is power.
– All gate output nodes have a conducting path to VDD or
GND, except when input changes are occurring.
• Dynamic Logic Gates
– The operation depends on temporary storage of charge in
parasitic node capacitances.
– The stored charge does not remain indefinitely, so must
be updated or refreshed. This requires establishment of an
update or recharge path to the capacitance frequently
enough to preserve valid voltage levels.
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Static v.s. Dynamic (Continued)
• Advantages of Dynamic Logic Gates
– Allow implementation of simple sequential circuits
with memory functions.
– Use of common clock signals throughout the
system enables the synchronization of various
circuit blocks.
– Implementation of complex circuits requires a
smaller silicon area than static circuits.
– Often consumes less dynamic power than static
designs, due to smaller parasitic capacitances.
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Pass Transistor Logic Circuits
 nMOS Pass transistor – transmission properties
 Transmission Gates
 Transmission Gate Applications
 Mux
 XOR
 D Latch
 D Flip Flop
 Clock Skew management
 Pass Transistor Logic Families