ECE260B – CSE241A Winter 2005 Testing Website: http://vlsicad.ucsd.edu/courses/ece260b-w05 ECE 260B – CSE 241A Testing 1 http://vlsicad.ucsd.edu Outline Defects and Faults ATPG for Combinational Circuits ATPG for Sequential Circuits ECE 260B – CSE 241A Testing 2 http://vlsicad.ucsd.edu Fault models Fault types: Functional. Timing. Abstraction level: Transistor. (layout) Gate. (netlist) Macro ( functional blocks ). Doping l Open Short Parameter R Source Drain ECE 260B – CSE 241A Testing 3 w G D Gate gm Delay S C 1/2 1 2 Vt http://vlsicad.ucsd.edu Fault Models Most Popular - “Stuck - at” model sa0 (output) 0 1 sa1 (input) Covers many other occurring faults, such as opens and shorts. Z x1 x2 ECE 260B – CSE 241A Testing 4 x3 , : x1 sa1 : x1 sa0 or x2 sa0 http://vlsicad.ucsd.edu Fault Models a To detect an and-bridging Detect a s-a-0 and b = 0 Detect b s-a-0 and a = 0 and b c To detect a transition fault Pattern 1: c = 1 good 1 bad Pattern 2: detect c s-a-1 ECE 260B – CSE 241A Testing 5 http://vlsicad.ucsd.edu Problem with stuck-at model: CMOS open fault x1 x2 Z x1 x2 Sequential effect Needs two vectors to ensure detection! Other options: use stuck-open or stuck-short models This requires fault-simulation and analysis at the switch or transistor level - Very expensive! ECE 260B – CSE 241A Testing 6 http://vlsicad.ucsd.edu Problem with stuck-at model: CMOS short fault ‘0’ ‘0’ C D A B ‘0’ A C ‘1’ B D ECE 260B – CSE 241A Testing 7 Causes short circuit between Vdd and GND for A=C=0, B=1 Possible approach: Supply Current Measurement (IDDQ) but: not applicable for gigascale integration http://vlsicad.ucsd.edu Exhaustive Algorithm For n-input circuit, generate all 2n input patterns Infeasible, unless circuit is partitioned into cones of logic, with < 15 inputs Perform exhaustive ATPG for each cone Misses faults that require specific activation patterns for multiple cones to be tested N inputs N inputs Combinational K outputs Logic Module K outputs Combinational Logic Module M state regs (a) Combinational function 2N patterns ECE 260B – CSE 241A Testing 8 (b) Sequential engine 2N+M patterns http://vlsicad.ucsd.edu Random Pattern Generation Flow chart for method Use to get tests for 60-80% of faults, then switch to Dalgorithm or other ATPG for rest ECE 260B – CSE 241A Testing 9 http://vlsicad.ucsd.edu Fault simulation Fault coverage found by fault simulations Test patterns Good simulation model Reference response Single fault simulation model Compare response Repeat for all possible stuck at zero/one faults Requires long simulation times !. Toggle test ( counts how many times each node has changed) can be used to get a first impression of fault coverage. ECE 260B – CSE 241A Testing 10 http://vlsicad.ucsd.edu Boolean Difference Symbolic Method (Sellers et al.) g = G (X1, X2, …, Xn) for the fault site fj = Fj (g, X1, X2, …, Xn) 1 j m Xi = 0 or 1 for 1 ECE 260B – CSE 241A Testing 11 i n http://vlsicad.ucsd.edu Boolean Difference (Sellers, Hsiao, Bearnson) Shannon’s Expansion Theorem: F (X1, X2, …, Xn) = X2 F (X1, 1, …, Xn) + X2 F (X1, 0, …, Xn) Boolean Difference (partial derivative): Fj g = Fj (1, X1, X2, …, Xn) Fj (0, X1, …, Xn) Fault Detection Requirements (for g s-a-0): G (X1, X2, …, Xn) = 1 Fj g = Fj (1, X1, X2, …, Xn) Fj (0, X1, …, Xn) = 1 ECE 260B – CSE 241A Testing 12 http://vlsicad.ucsd.edu Basic Terms, Path Sensitization Controllability: the ease of controlling the state of a node in the circuit Observability: the ease of observing the state of a node in the circuit Goals: Determine input pattern that makes a fault controllable (triggers the fault, and makes its impact visible at the output nodes) Fault enabling 1 1 1 1 Fault propagation 0 sa0 1 Out 1 0 Techniques Used: D-algorithm, Podem ECE 260B – CSE 241A Testing 13 http://vlsicad.ucsd.edu 5-Value Logic 0 – binary 0 in both good and fault circuit 1- binary 1 in both good and fault circuit X – don’t care D – binary 1 in good circuit, 0 in bad circuit D – binary 0 in good circuit, 1 in bad circuit ECE 260B – CSE 241A Testing 14 http://vlsicad.ucsd.edu Primitive D-Cube of Failure Models circuit faults: Stuck-at-0 Stuck-at-1 Bridging fault (short circuit) Arbitrary change in logic function AND Output sa0: “1 1 D” AND Output sa1: “0 X D ” “X 0 D ” Wire sa0: “D” Propagation D-cube – models conditions under which fault effect propagates through gate ECE 260B – CSE 241A Testing 15 http://vlsicad.ucsd.edu Forward Implication Results in logic gate inputs that are significantly labeled so that output is uniquely determined AND gate forward implication table: ECE 260B – CSE 241A Testing 16 http://vlsicad.ucsd.edu Backward Implication Unique determination of all gate inputs when the gate output and some of the inputs are given ECE 260B – CSE 241A Testing 17 http://vlsicad.ucsd.edu Path Sensitization Method Circuit Example 1 Fault Sensitization 2 Fault Propagation 3 Line Justification ECE 260B – CSE 241A Testing 18 http://vlsicad.ucsd.edu Path Sensitization Method Circuit Example Try path f – h – k – L blocked at j, since there is no way to justify the 1 on i 1 1 D D D D 1 0 D 1 ECE 260B – CSE 241A Testing 19 http://vlsicad.ucsd.edu Path Sensitization Method Circuit Example Try simultaneous paths f – h – k – L and g – i – j – k – L blocked at k because of D or D) disappears 1 1 D-frontier (chain D D 1 D D D 1 ECE 260B – CSE 241A Testing 20 http://vlsicad.ucsd.edu Path Sensitization Method Circuit Example Final try: path g – i – j – k – L – test found! 0 1 0 D D D D D 1 1 ECE 260B – CSE 241A Testing 21 http://vlsicad.ucsd.edu D-Algorithm – Top Level 1. Number all circuit lines in increasing level order from PIs to POs; 2. Select a primitive D-cube of the fault to be the test cube; 3. D-drive (); 4. Consistency (); 5. return (); ECE 260B – CSE 241A Testing 22 http://vlsicad.ucsd.edu D-Algorithm – Propagation D-frontier: all gates whose output is X, at least one input is D or D J-frontier: all gates whose output is defined, but is not implied by the input values ECE 260B – CSE 241A Testing 23 http://vlsicad.ucsd.edu Example 7.2: Fault A sa0 1 Step 1 – D-Drive – Set A = 1 D ECE 260B – CSE 241A Testing 24 D http://vlsicad.ucsd.edu Step 2 -- Example 7.2 Step 2 – D-Drive – Set f = 0 0 1 D ECE 260B – CSE 241A Testing 25 D D http://vlsicad.ucsd.edu Step 3 -- Example 7.2 Step 3 – D-Drive – Set k = 1 1 D 0 1 D ECE 260B – CSE 241A Testing 26 D D http://vlsicad.ucsd.edu Step 4 -- Example 7.2 Step 4 – Consistency – Set g = 1 1 1 D 0 1 D ECE 260B – CSE 241A Testing 27 D D http://vlsicad.ucsd.edu Step 5 -- Example 7.2 Step 5 – Consistency – f = 0 Already set 1 1 D 0 1 D ECE 260B – CSE 241A Testing 28 D D http://vlsicad.ucsd.edu Step 6 -- Example 7.2 Step 6 – Consistency – Set c = 0, Set e = 0 1 1 0 1 D ECE 260B – CSE 241A Testing 29 0 D 0 D D http://vlsicad.ucsd.edu D-Chain Dies -- Example 7.2 Step 7 – Consistency – Set B = 0 D-Chain dies X 1 0 0 1 D 0 1 D 0 D D Test cube: A, B, C, D, e, f, g, h, k, L ECE 260B – CSE 241A Testing 30 http://vlsicad.ucsd.edu Example 7.3 – Fault s sa1 Primitive D-cube of Failure 1 sa1 ECE 260B – CSE 241A Testing 31 D http://vlsicad.ucsd.edu Example 7.3 – Step 2 s sa1 Propagation D-cube for v 1 1 sa1 0 D D D ECE 260B – CSE 241A Testing 32 http://vlsicad.ucsd.edu Example 7.3 – Step 2 s sa1 Forward & Backward Implications 0 1 1 1 1 1 sa1 0 D D D ECE 260B – CSE 241A Testing 33 http://vlsicad.ucsd.edu Example 7.3 – Step 3 s sa1 Propagation D-cube for Z – test found! 0 1 1 1 1 1 sa1 0 D D D D 1 ECE 260B – CSE 241A Testing 34 http://vlsicad.ucsd.edu PODEM High-Level Flow 1. Assign binary value to unassigned PI 2. Determine implications of all PIs 3. Test Generated? If so, done. 4. Test possible with more assigned PIs? If maybe, go to Step 1 5. Is there untried combination of values on assigned PIs? If not, exit: untestable fault 6. Set untried combination of values on assigned PIs using objectives and backtrace. Then, go to Step 2 ECE 260B – CSE 241A Testing 35 http://vlsicad.ucsd.edu Example 7.3 -- Step 1 s sa1 Select path s – Y for fault propagation sa1 ECE 260B – CSE 241A Testing 36 http://vlsicad.ucsd.edu Example 7.3 -- Step 2 s sa1 Initial objective: Set r to 1 to sensitize fault 1 sa1 ECE 260B – CSE 241A Testing 37 http://vlsicad.ucsd.edu Example 7.3 -- Step 3 s sa1 Backtrace from r 1 sa1 ECE 260B – CSE 241A Testing 38 http://vlsicad.ucsd.edu Example 7.3 -- Step 4 s sa1 Set A = 0 in implication stack 1 0 sa1 ECE 260B – CSE 241A Testing 39 http://vlsicad.ucsd.edu Example 7.3 -- Step 5 s sa1 Forward implications: d = 0, X = 1 1 0 1 0 sa1 ECE 260B – CSE 241A Testing 40 http://vlsicad.ucsd.edu Example 7.3 -- Step 6 s sa1 Initial objective: set r to 1 1 0 1 0 sa1 ECE 260B – CSE 241A Testing 41 http://vlsicad.ucsd.edu Example 7.3 -- Step 7 s sa1 Backtrace from r again 1 0 1 0 sa1 ECE 260B – CSE 241A Testing 42 http://vlsicad.ucsd.edu Example 7.3 -- Step 8 s sa1 Set B to 1. Implications in stack: A = 0, B = 1 1 0 1 0 1 ECE 260B – CSE 241A Testing 43 sa1 http://vlsicad.ucsd.edu Example 7.3 -- Step 9 s sa1 Forward implications: k = 1, m = 0, r = 1, q = 1, Y = 1, s = D, u = D, v = D, Z = 1 1 1 0 0 0 1 1 sa1 D 1 1 D D ECE 260B – CSE 241A Testing 44 1 http://vlsicad.ucsd.edu Backtrack -- Step 10 s sa1 X-PATH-CHECK shows paths s – Y and v – Z blocked (D-frontier disappeared) 1 0 s–u– 1 0 sa1 ECE 260B – CSE 241A Testing 45 http://vlsicad.ucsd.edu Step 11 -- s sa1 Set B = 0 (alternate assignment) 1 0 0 ECE 260B – CSE 241A Testing 46 sa1 http://vlsicad.ucsd.edu Backtrack -- s sa1 Forward implications: d = 0, X = 1, m = 1, r = 0, s = 1, q = 0, Y = 1, v = 0, Z = 1. Fault not sensitized 1 0 0 0 0 1 1 sa1 1 0 1 0 ECE 260B – CSE 241A Testing 47 1 http://vlsicad.ucsd.edu Step 13 -- s sa1 Set A = 1 (alternate assignment) 1 1 sa1 ECE 260B – CSE 241A Testing 48 http://vlsicad.ucsd.edu Step 14 -- s sa1 Backtrace from r again 1 1 sa1 ECE 260B – CSE 241A Testing 49 http://vlsicad.ucsd.edu Step 15 -- s sa1 Set B = 0. Implications in stack: A = 1, B = 0 1 1 0 ECE 260B – CSE 241A Testing 50 sa1 http://vlsicad.ucsd.edu Backtrack -- s sa1 Forward implications: d = 0, X = 1, m = 1, r = 0. Conflict: fault not sensitized. Backtrack 1 0 1 0 0 1 1 sa1 1 0 1 0 ECE 260B – CSE 241A Testing 51 1 http://vlsicad.ucsd.edu Step 17 -- s sa1 Set B = 1 (alternate assignment) 1 1 1 ECE 260B – CSE 241A Testing 52 sa1 http://vlsicad.ucsd.edu Fault Tested -- Step 18 s sa1 Forward implications: d = 1, m = 1, r = 1, q = 0, s = D, v = D, X = 0, Y = D 0 1 1 1 1 1 D sa1 D 0 D D X ECE 260B – CSE 241A Testing 53 http://vlsicad.ucsd.edu Comparison Path sensitization: multiply SAT problems D-algorithm: decisions are made at the J-frontier PODEM: decisions are made at the PIs FAN: Multiply paths are traced back simultaneously A decision can be made at a headline ECE 260B – CSE 241A Testing 54 http://vlsicad.ucsd.edu History of Algorithm Speedups Algorithm D-ALG PODEM FAN TOPS SOCRATES Waicukauski et al. EST TRAN Recursive learning Tafertshofer et al. ECE 260B – CSE 241A Testing 55 Est. speedup over D-ALG (normalized to D-ALG time) 1 7 23 292 1574 2189 8765 3005 485 25057 Year 1966 1981 1983 1987 1988 1990 1991 1993 1995 1997 http://vlsicad.ucsd.edu Sequential Circuits: State! Combinational circuit testing is relatively easy Sequential circuit testing needs to drive sequential elements to specific state to test a fault N inputs N inputs Combinational K outputs K outputs Combinational Logic Logic Module Module M state regs (a) Combinational function 2N patterns ECE 260B – CSE 241A Testing 56 (b) Sequential engine 2N+M patterns http://vlsicad.ucsd.edu Sequential Circuit Controllability and Observability CONTROLABILITY: The ease of controlling the state of a node in the circuit. OBSERVABILITY: The ease of observing the state of a node in the circuit Example: 4 bit counter with clear Control of q3: Set low: perform clear = 1 vector clr q3 q2 q1 q0 Set high : perform clear + count to 1000B = 9 vectors Testing a node in a circuit A: Apply sequence of test vectors to circuit which sets node to demanded state. B: Apply sequence of test vectors to circuit which enables state of node to be observed. C: The observing test vector sequence must not change state of node. ECE 260B – CSE 241A Testing 57 http://vlsicad.ucsd.edu Ad-hoc Test data address data test address Memory Memory select Processor Processor I/O bus I/O bus Inserting multiplexer improves testability ECE 260B – CSE 241A Testing 58 http://vlsicad.ucsd.edu Scan-based Test ScanIn ECE 260B – CSE 241A Testing 59 Combinational Logic A Register Register In ScanOut Combinational Out Logic B http://vlsicad.ucsd.edu Scan-based Test —Operation In 0 Test In1 Test ScanIn Test In2 Test Test In 3 Test Test Test ScanOut Latch Latch Latch Latch Out0 Out1 Out2 Out3 Test 1 2 N cycles scan-in ECE 260B – CSE 241A Testing 60 1 cycle evaluation N cycles scan-out http://vlsicad.ucsd.edu Scan-Path Testing A B REG[1] REG[0] REG[2] REG[3] SCANIN + REG[4] COMPIN COMP REG[5] SCANOUT OUT Partial-Scan can be more effective for pipelined datapaths ECE 260B – CSE 241A Testing 61 http://vlsicad.ucsd.edu Boundary Scan (JTAG) Printed-circuit board Logic Scan-out si so scan path normal interconnect Scan-in Packaged IC Bonding Pad Board testing becomes as problematic as chip testing ECE 260B – CSE 241A Testing 62 http://vlsicad.ucsd.edu Self-test (Sub)-Circuit Stimulus Generator Under Response Analyzer Test Test Controller Rapidly becoming more important with increasing chip-complexity and larger modules ECE 260B – CSE 241A Testing 63 http://vlsicad.ucsd.edu Design verification testing (10- 50% of total development costs) Does model comply with specification ? Specification (text) Does design have same behaviour as model ? Behavioural model (Verilog, Spice, etc.) Design: Full custom, Standard cell, Gate array Low quantity Does design work ? Does chip work as specified ? ( 50 % ) Produced chip Does chip work in application ? (50 % * 50 % = 25 %) Sufficient margins for production variations ? Is it testable in production ? Does specification comply with application ? (50 %) (Can be improved by System - IC behavioural modelling) Imperfect designs are often accepted in HEP if ways around bugs can be found. ECE 260B – CSE 241A Testing 64 Application Reliability ? How do we find out what’s wrong ? http://vlsicad.ucsd.edu Production testing Wafer (Production test pattern development 5 - 25 % of development costs) (Production test 20 - 50% of final chip cost) Bare die Packaged Burn-in ? Functional test: fault coverage, stuck at 0/1 Internal speed test: clocking speed Margins ? (noise, measurement accuracy, etc.) Temperature ?. Supply voltage ? External loads ? MCM Analog parameters: gain, noise, time constants, precision, etc. I/O level test: output levels, input thresholds External speed test: setup time, hold time, delay Monitoring of radiation resistance (destructive test) ECE 260B – CSE 241A Testing 65 http://vlsicad.ucsd.edu Cost of finding failing chip LEVEL Specification FAILURE MECHANISM Functionality, Performance Testability, reliability 1$ Interoperability Design Prototype Wafer Chip Verification, Qualification, Production margins Yield, speed, noise, gain Cutting, bonding PRICE Design verification testing 1000$ 100 $ 100.000$ GOLD ( price per design) 100K$ - ? $ (if not sufficient design verification performed) 1$ 10$ (MCM) Module Soldering, ESD 100$ 100 $ Production testing (Sub) System Cables, connectors 1000$ 100 $ (price per chip) At customer ECE 260B – CSE 241A Testing 66 Reliability of components, 10.000$ vibrations, corrosion, radiation, high voltage GOLD http://vlsicad.ucsd.edu Thanks ECE 260B – CSE 241A Testing 67 http://vlsicad.ucsd.edu