ECE260B – CSE241A
Winter 2005
Parasitic Extraction
Website: http://vlsicad.ucsd.edu/courses/ece260b-w05
ECE 260B – CSE 241A Parasitic Extraction 1
http://vlsicad.ucsd.edu
Conventional Design Flow
Funct. Spec
RTL
Behav. Simul.
Logic Synth.
Stat. Wire Model
Front-end
Gate-level Net.
Gate-Lev. Sim.
Back-end
Floorplanning
Parasitic Extrac.
Place & Route
ECE 260B – CSE 241A Parasitic Extraction 2
Layout
http://vlsicad.ucsd.edu
Technology Scaling
 Process technology evolves with shrinking feature sizes
 Parasitic effects become more significant with smaller
feature sizes

Increasing wire resistance, fringing and coupling capacitances...
 Interconnect delay dominates VLSI system performance
 The performance of today’s DSM ICs is strongly
determined by the parasitic effects of the passive
structures interconnecting active devices
 Accurate, high-speed tools and methods are needed to
extract and simulate these parasitic effects in order to
perform precise timing analysis to the circuit
ECE 260B – CSE 241A Parasitic Extraction 3
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Layout Parasitic Extraction
 Necessary step after routing

Back-annotation
 Account for non-ideal nature of interconnect


Wire capacitance
Wire and via resistance
 Parasitic information is used in post-layout verification


Timing verification of synchronous circuits
Functional verification of asynchronous circuits
 Design performance is ultimately limited by parasitics
ECE 260B – CSE 241A Parasitic Extraction 4
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Parasitic Extraction: Why do we need it?
2
 Example: to produce RC
tree network for elmore
delay analysis
s
R1 1
4
R3
C1
3
C3
Ri
i
Ci
 Example: to produce RC
tree network for
capacitive cross-talk
analysis
ECE 260B – CSE 241A Parasitic Extraction 5
Slide courtesy L. Daniel
http://vlsicad.ucsd.edu
Parasitic Extraction
thousands of wires
e.g. critical path
e.g. gnd/vdd grid
 identify some ports
 produce equivalent circuit that
Parasitic
Extraction
models response of wires at those
ports
ECE 260B – CSE 241A Parasitic Extraction 6
Slide courtesy L. Daniel
tens of circuit
elements for
gate level spice
simulation
http://vlsicad.ucsd.edu
Parasitic Extraction (the two steps)
Electromagnetic
Analysis
thin volume
filaments
with constant
current
small surface
panels
with constant
charge
million of elements
Model Order
Reduction
tens of elements
ECE 260B – CSE 241A Parasitic Extraction 7
Slide courtesy L. Daniel
http://vlsicad.ucsd.edu
Parasitic Extraction / Back-Annotation
 Input data

Technology data
- Metal and via resistances
- Capacitance coefficients

Library data
- Input pin capacitances

Design data
- Routing
- Boundary conditions (load and drive information)
 Output data

Parasitic information:
- DSPF
- RSPF
- Set_load

Interpreted parasitic information
- Custom WLM
- LEF coefficients
ECE 260B – CSE 241A Parasitic Extraction 8
http://vlsicad.ucsd.edu
Active Device Parasitics
 Gate output capacitance mainly from gate oxide tox
 Substrate coupling resistances and capacitances
 Characterized by cell libraries
ECE 260B – CSE 241A Parasitic Extraction 9
Figure courtesy, A. Nardi
http://vlsicad.ucsd.edu
Interconnect Parasitics
 Wires are not ideal.
Parasitics:



Resistance
Capacitance
Inductance
 Why do we care?




Impact on delay
noise
energy consumption
power distribution
Picture from “Digital Integrated Circuits”,
Rabaey, Chandrakasan, Nikolic
ECE 260B – CSE 241A Parasitic Extraction 10
Slide courtesy L. Daniel
http://vlsicad.ucsd.edu
SEMATECH Prototype BEOL stack, 2000
Wire
Global (up to 5)
Via
Passivation
Dielectric
Etch Stop Layer
Dielectric Capping Layer
Copper Conductor with
Barrier/Nucleation Layer
Intermediate (up to 4)
Local (2)
ECE 260B – CSE 241A Parasitic Extraction 11
Pre Metal Dielectric
Tungsten Contact Plug
•Slide courtesy of Chris Case, BOC Edwards
http://vlsicad.ucsd.edu
Interconnect Resistance
R=
Sheet Resistance
R
L
T
W

r L
TW
R1
R2
Resistance seen by current going from left to right is
same in each block
ECE 260B – CSE 241A Parasitic Extraction 12
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Resistance Scaling
• Resistance scales badly
• True scaling would reduce width and thickness by S each node
• R ~ S2 for a fixed line length and material
• Reverse scaling  wires get smaller and slower, devices get
smaller and faster
• At higher frequencies, current crowds to edges of conductor
(thickness of conduction = skin depth)  increased R
ECE 260B – CSE 241A Parasitic Extraction 13
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Interconnect Capacitance
Lateral cap
w


S
Line dimensions: W, S, T, H
Sometimes H is called T in the literature, which can be
confusing
ECE 260B – CSE 241A Parasitic Extraction 14
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Capacitance Estimation
• Empirical capacitance models are easiest and fastest
• Handle limited configurations (e.g., range of T/H ratio)
• Some limiting assumptions (e.g., no neighboring wires)
Cwire
 W
  ox 
 H ILD

 W
  0.77  1.06

 H ILD



0.25
T
 1.06 wire
 H ILD



0.5



Capacitance per
unit length
• Rules of thumb: e.g., 0.2 fF/um for most wire widths < 2um
• Cf. MOSFET gate capacitance ~ 1 fF/um width
• Pattern-matching approaches applied to multilayer crosssections
ECE 260B – CSE 241A Parasitic Extraction 15
http://vlsicad.ucsd.edu
Inductance




Inductance is the flux induced by current variation
Measures ability to store energy in the form of a magnetic field
Consists of self-inductance and mutual inductance terms
At high frequencies, can be significant portion of total impedance
Z = R + jwL (w = 2pf = angular freq)
S1
S2
I
11   B1  ds1
S1
d 11
Self Inductance 
d
ECE 260B – CSE 241A Parasitic Extraction 16
I
12   B1  ds2
S2
d 12
Mutual Inductance 
d
I
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Coil Inductance


V = L d I/d t
V2 = M12 d I1/d t
Faraday’s law
V = N d (B A) / d t
B = m (N / l) I
L = m N2 A / l
V = voltage
N = number of turns of the coil
B = magnetic flux
A = area of magnetic field circled by the coil
l = height of the coil
t = time
ECE 260B – CSE 241A Parasitic Extraction 17
http://vlsicad.ucsd.edu
Filament Inductance
li l j
m
Lij 
dV ' dV


4pai a j V V | r  r ' |
i
'
j
Where the integral is over the volume of the conductors,


r is the position in a given filament, and
li is the unit vector in the direction of current flow for
conductor i
ECE 260B – CSE 241A Parasitic Extraction 18
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Inductance Scaling
wL  R
 1 
w  2pf  2p  
 pt r 

If




Copper interconnects  R is reduced

Frequency of interest is determined by signal rise time,
not clock frequency
where
Faster clock speeds
Thick, low-resistance (reverse-scaled) global lines
Chips are getting larger  long lines  large current
loops
Massoud/Sylvester/Kawa,
Synopsys
ECE 260B – CSE 241A
Parasitic Extraction 19
•Slide courtesy of Massoud/Sylvester/Kawa, Synopsys
http://vlsicad.ucsd.edu
Inductance Trends

Inductance = weak (log) function of conductor dimensions

Inductance = strong function of distance to current return path (e.g.,
power grid)


Want nearby ground line to provide a small current loop (cf. Alpha 21164)
Inductance most significant in long, low-R, fast-switching nets

Clocks are most susceptible
ECE 260B – CSE 241A Parasitic Extraction 20
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Inductance is Important …
 On-chip inductance is negligible, and usually alleviate performance
degradation due to the presence of capacitance


Package inductance is significant when coupled with large
magnitude of currents in the same frequency range


Seesaw effect between inductance and capacitance
Complete analysis needs to include package inductance since signals
cannot be assumed ideal at pads
For the idealized case of a lossless homogeneous dielectric with an
array of conductors, the inductance matrix [L] can be derived directly
from the capacitance matrix [C] by
1
1
[ L]  2 [C ]
v0
where v0 is the phase velocity of the medium

However in the IC domain, these assumptions do not hold up and we
need inductance extraction
ECE 260B – CSE 241A Parasitic Extraction 21
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Inductance Return Path
 Inductance is a loop quantity
 Knowledge of return path is required, but hard to
determine
Signal Line
Return Path
 For example, the return path depends on the frequency
Massoud/Sylvester/Kawa,
Synopsys
ECE 260B – CSE 241A
Parasitic Extraction 22
•Slide courtesy of Massoud/Sylvester/Kawa, Synopsys
http://vlsicad.ucsd.edu
Frequency-Dependent Return Path

At low frequency,



minimize impedance
minimize resistance
use as many returns as possible (parallel resistances)
Gnd

( R  wL) and current tries to
Gnd
At high frequency,




Gnd
Signal
Gnd
( R  jwL)
Gnd
Gnd
( R  wL)and current tries to
minimize impedance
( R  jwL)
minimize inductance
use smallest possible loop (closest return path)  L dominates, current
returns “collapse”
Power and ground lines always available as low-impedance current returns
Gnd
Gnd
ECE 260B – CSE 241A Parasitic Extraction 23
Gnd
Signal
Gnd
•Slide courtesy of Massoud/Sylvester/Kawa, Synopsys
Gnd
Gnd
http://vlsicad.ucsd.edu
Extracting Inductance vs. Capacitance

Capacitance




Locality problem is easy: electric field lines “suck up” to nearest
neighbor conductors
Boundary element approach requires discretization of only the
surfaces of conductors
Charge density over the conductor is rarely uniform, needs to solve
the integral form of Laplace’s equation for many times
Inductance




Locality problem is hard: magnetic field lines are not local; current
returns can be complex
Local calculation is easy: no strong geometry dependence;
analytic formulae work very well
Current density and direction is constant in each conductor when
the frequency is low enough to ignore the skin effect
Conductors are divided into bundles of filaments each with a
constant current density, compute a circuit solution for return current
distribution
ECE 260B – CSE 241A Parasitic Extraction 24
http://vlsicad.ucsd.edu
Outline
 Problem Statement
 Parasitics
 Extraction Methods





Resistance extraction
Capacitance Extraction (electrostatic)
RL Extraction (MQS)
Combined RLC Extraction (EMQS)
Electromagnetic Interference Analysis (fullwave)
 Future Trends
ECE 260B – CSE 241A Parasitic Extraction 25
http://vlsicad.ucsd.edu
Interconnect Resistance Extraction


Sheet resistance R□
Series resistance
R = R□ * Length / Width / Thickness

Inaccuracies arise in irregular geometries, e.g., corners of a route

Apply Laplace’s equation 2=0, or
 2  2  2


0
x 2 y 2 z 2

Discretize an interconnect conductor into grids

ijE


Vi  V j
Rij
0
Solve a partial differential equation with known boundary conditions
Table Lookup for better efficiency
ECE 260B – CSE 241A Parasitic Extraction 26
http://vlsicad.ucsd.edu
Outline
 Problem Statement
 Parasitics
 Extraction Methods





Resistance extraction
Capacitance Extraction (electrostatic)
RL Extraction (MQS)
Combined RLC Extraction (EMQS)
Electromagnetic Interference Analysis (fullwave)
 Future Trends
ECE 260B – CSE 241A Parasitic Extraction 27
http://vlsicad.ucsd.edu
Parasitic Extraction Accuracy
 Above 0.5μm feature size, wire cross-section was
rectangular
 Interconnect modeled as parallel plate over ground plane


Parallel plate capacitance
Fringe capacitance
 2-D extraction accurate enough:
Area + Fringe
C_parallel
C_fringe
ECE 260B – CSE 241A Parasitic Extraction 28
C_fringe
http://vlsicad.ucsd.edu
Capacitance Extraction
 2-D extraction





Wire cap includes parallel plate (area), fringing, and coupling cap
C = k1 Area + k2 Perimeter + k3 Coupling_length / Coupling_spacing
These coefficients are fit in for an average environment of a wire
Table Lookup
Intra-layer capacitances are not well modeled
 3-D extraction

Solve for real 3-D geometries of wiring
 2.5-D extraction



Compromise between speed and
accuracy
Models 3-D effects by a combination
of two orthogonal 2-D structures
E.g., two cross-section views on the
x-z and y-z planes, z is the vertical
axis going through layers
ECE 260B – CSE 241A Parasitic Extraction 29
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How Capacitance Extractor Works
 Technology pre-characterization





generates coefficients through solving the 3-D equations for
“representative” sample of topologies
Really, cross-sections through “tunnel” that contains a section of
the victim net
Creates look-up table
Time consuming, but only done once
Each layer of interconnect added roughly doubles time for
coefficient generation
 Pattern compression

Reduces the total number of pre-characterization patterns
 Geometric parameter extraction

Reduce the number of geometric parameters considering the
shielding effect
 Extraction matches topologies to entries in look-up table
ECE 260B – CSE 241A Parasitic Extraction 30
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Extraction to Floating Metal
Dummy fills (as floating metals) are required by modern
CMP process
Extraction to floating metal similar to extraction for cross
talk analysis




Net to net capacitance required
Effective capacitance to floating metal dependent on potential of
floating metal
E.g., Cadence HyperExtract models floating metal as grounded
If we model floating metal as grounded, this is pessimistic
Below 0.18mm with “local fill” requirements, fill metal can
impact timing
ECE 260B – CSE 241A Parasitic Extraction 31
Floating
metal
http://vlsicad.ucsd.edu
Capacitive Extraction
Example: Intel 0.25 micron Process
5 metal layers Ti/Al - Cu/Ti/TiN Polysilicon dielectric.
Taken from “Digital Integrated Circuits”, 2nd Edition, Rabaey, Chandrakasan, Nikolic
fringing
parallel
Consider only electric field (capacitive)
coupling
http://vlsicad.ucsd.edu
ECE 260B – CSE 241A Parasitic Extraction 32
Slide courtesy L. Daniel
Capacitive Extraction
Why? E.g. Analysis of Delay of Critical Path
ECE 260B – CSE 241A Parasitic Extraction 33
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Capacitance Extraction
Problem Formulation
 Given a collection of N conductors (of any shape and
dimension)
Calculate the coupling
capacitance matrix C
fringing
parallel
ECE 260B – CSE 241A Parasitic Extraction 34
Slide courtesy L. Daniel




C ?
   
 v    q 
   
    
http://vlsicad.ucsd.edu
Capacitance Extraction
Solution Procedure
 For i = 1 to N,

apply one volt to conductor i and ground all the others

solve the electrostatic problem and find the resulting vector of charges
on all conductors
that is the i-th column of the conductance matrix

q?
q ?
qi  ?
q ?
q ?
vi  1  C1,i
 0  q1 
 C
 1  q 
2 ,i

      2 


 0   

   
C
N ,i

     qN 
r


2
ECE 260B – CSE 241A Parasitic Extraction 35
q?
Slide courtesy L. Daniel
http://vlsicad.ucsd.edu
Overview
 Problem Statement
 Parasitics
 Extraction Methods




Capacitance Extraction (electrostatic)
RL Extraction (MQS)
Combined RLC Extraction (EMQS)
Electromagnetic Interference Analysis (fullwave)
 Future Trends
ECE 260B – CSE 241A Parasitic Extraction 36
http://vlsicad.ucsd.edu
Inductance and Resistance Extraction
Example: IC package
Picture Thanks to Coventor
wire
lead
bonding
frames
IC
package
Slide courtesy L. Daniel
ECE 260B – CSE 241A Parasitic Extraction 37
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Inductance and Resistance Extraction
Where do we need to account for inductance?
 chip to package and package to board connections are highly
inductive



inductance can create Ldi/dt noise on the gnd/vdd network
inductance can limit communication bandwidth
inductive coupling between leads or pins can introduce noise
pins or solder balls
from package to PCB
wire bonding and lead frames
or solder balls from IC to package
IC
PCB
package
on-package
decoupling
capacitors
on-board
decoupling
capacitors
ECE 260B – CSE 241A Parasitic Extraction 38
Slide courtesy L. Daniel
http://vlsicad.ucsd.edu
Inductance and Resistance Extraction
Why also resistance? Skin and Proximity effects
Simple Example
proximity effect:
opposite currents in
nearby conductors attract
each other
skin effect:
high frequency currents
crowd toward the surface
of conductors
ECE 260B – CSE 241A Parasitic Extraction 39
Slide courtesy L. Daniel
http://vlsicad.ucsd.edu
Inductance and Resistance Extraction
Skin and Proximity effects (cont.)
 Why do we care?



Skin and proximity effects change interconnect resistance and
inductance
hence they affect performance (propagation delay)
and noise (magnetic coupling)
 When do we care?





frequency is high enough that wire width OR thickness are less than
two “skin-depths”
e.g. on PCB at and above 100MHz
e.g. on packages at above 1GHz
e.g. on-chip at and above 10GHz
note. clock at 3GHz has significant harmonics at 10GHz!!
ECE 260B – CSE 241A Parasitic Extraction 40
Slide courtesy L. Daniel
http://vlsicad.ucsd.edu
Inductance and Resistance Extraction
Problem Formulation
 Given a collection of
interconnected N wires of any
shape and dimension
 Identify the M input ports
 Calculate the MxM resistance and the
Picture by
M. Chou
inductance matrices for the ports,
 that is the real and immaginary part of the
impedance matrix





R?


  jw 




ECE 260B – CSE 241A Parasitic Extraction 41
L?
Slide courtesy L. Daniel
    
   i   v 
    
     
http://vlsicad.ucsd.edu
Inductance and Resistance Extraction
Solution Procedure
 Typically instead of
calculating impendance we
calculate the admittance
matrix.
 For each pair of input
terminals,


apply a unit voltage source and
solve magneto quasit-static
problem (MQS) to calculate all
terminal currents
that is one column of the
admittance matrix [R+jwL]-1
R  jwL v   i 
Z 1v   i 
Y v   i 
1
2 A  mJ
J

 jwA  
 J  0
Y1,i

 Y
2 ,i




YM ,i

Slide courtesy L. Daniel
ECE 260B – CSE 241A Parasitic Extraction 42







0  i1 
1  i 
  2
0   
   
   iM 
http://vlsicad.ucsd.edu
Overview
 Problem Statement
 Parasitics
 Extraction Methods




Capacitance Extraction (electrostatic)
RL Extraction (MQS)
Combined RLC Extraction (EMQS)
Electromagnetic Interference Analysis (fullwave)
 Future Trends
ECE 260B – CSE 241A Parasitic Extraction 43
Slide courtesy L. Daniel
http://vlsicad.ucsd.edu
Combined RLC Extraction
Example: current distributions on powergrid
input terminals
ECE 260B – CSE 241A Parasitic Extraction 44
Slide courtesy L. Daniel
http://vlsicad.ucsd.edu
Combined RLC Extraction
Example: analysis of resonances on powergrid
* 3 proximity templates per cross-section
- 20 non-uniform thin filaments per cross-section
ECE 260B – CSE 241A Parasitic Extraction 45
Slide courtesy L. Daniel
http://vlsicad.ucsd.edu
Combined RLC Extraction
Extraction Example: analysis of substrate coupling
ECE 260B – CSE 241A Parasitic Extraction 46
Slide courtesy L. Daniel
http://vlsicad.ucsd.edu
Combined RLC Extraction
Example: resonance of RF microinductors
 At frequency of operation
the current flows in the spiral
and creates magnetic
energy storage (it works as
an inductor: GOOD)
 But for higher frequencies the
impedance of the parasitic
capacitors is lower and current
prefers to “jump” from wire to
wire as displacement currents
(it works as a capacitor: BAD)
Picture thanks to Univ. of Pisa
ECE 260B – CSE 241A Parasitic Extraction 47
Slide courtesy L. Daniel
http://vlsicad.ucsd.edu
Combined RLC Extraction
Problem Formulation
 Given a collection of
interconnected N wires of any
shape and dimension
 Identify the M input ports
 Calculate the MxM IMPEDANCE matrix
Picture by
M. Chou
for the ports,
 that is the real and immaginary part of the
impedance matrix




Z ?
ECE 260B – CSE 241A Parasitic Extraction 48
   
  i   v 
   
    
Slide courtesy L. Daniel
http://vlsicad.ucsd.edu
Combined RLC Extraction
Solution Procedure
 Same as RL extraction.
 Typically calculate admittance matrix
 For each pair of input terminals,


apply a unit voltage source and solve
electro-magneto quasit-static problem
(EMQS) to calculate all terminal currents
that is one column of the admittance matrix
[R+jwL]-1
Y1,i

 Y
2 ,i




 YM ,i







ECE 260B – CSE 241A Parasitic Extraction 49
0  i1 
1  i 
  2
0   
   
   iM 
Slide courtesy L. Daniel
Y v  i
r


2 A  mJ
2
J

 jwA  
 J  0
nˆ  J  jwr
http://vlsicad.ucsd.edu
Outline
 Problem Statement
 Parasitics
 Extraction Methods




Capacitance Extraction (electrostatic)
RL Extraction (MQS)
Combined RLC Extraction (EMQS)
Electromagnetic Interference Analysis (fullwave)
 Future Trends
ECE 260B – CSE 241A Parasitic Extraction 50
Slide courtesy L. Daniel
http://vlsicad.ucsd.edu
The Electromagnetic Interference (EMI)
Problem description

Electronic circuits produce and are subject to
Electromagnetic Interference (EMI).


in particular when wavelengths ~ wire lengths
EMI is a problem because it can severely and
randomly affect analog and digital circuit
functionality!!!
IC
PCB
IC
PCB
ECE 260B – CSE 241A Parasitic Extraction 51
Slide courtesy L. Daniel
http://vlsicad.ucsd.edu
EMI analysis
EMI at board, package and IC level
 Traces on PCB can pick up
EMI and transmit it to IC’s
 IC’s can produce high
frequency conducted
emissions that can radiate
from PCB’s
 IC’s themselves can directly
IC
IC
PCB
produce radiated emissions

high-frequency current loops
Vdd-decap-gnd on package or
inside IC’s.

high-frequency current loops
inside IC (near future)

IC radiation amplified by heat
sinks!
ECE 260B – CSE 241A Parasitic Extraction 52
Slide courtesy L. Daniel
IC
PCB
http://vlsicad.ucsd.edu
EMI a problem for ICs design?

So far: dimensions too small and wavelengths too
large

Trend: larger chip dies and higher frequencies
Today’s PCB:
• clocks
• harmonics
• wavelengths
• dimensions
~ 300MHz
~ 3GHz
~ 10cm
~ 10cm
d
this gives resonances on PCB today,
hence it might on IC tomorrow!
Future’s IC:
• clocks
• harmonics
• wavelengths
• dimensions
ECE 260B – CSE 241A Parasitic Extraction 53
Slide courtesy L. Daniel
~ 3GHz
~ 30GHz
~ 1cm
~ 1cm
d
http://vlsicad.ucsd.edu
EMI analysis
Solution Procedure
 Typically, EMI analysis is a two-step process:
1) determine accurate current distributions on conductors
I1
I2
 2) calculate radiated fields from the current distributions
E
I1
I2
ECE 260B – CSE 241A Parasitic Extraction 54
Slide courtesy L. Daniel
http://vlsicad.ucsd.edu
Need for full-board analysis
 Interconnect impedances depend on complicated return
paths.
 Unbalanced currents generate most of the interference.
I1
I 2  I1
 Hence need FULL-BOARD analysis
ECE 260B – CSE 241A Parasitic Extraction 55
Slide courtesy L. Daniel
http://vlsicad.ucsd.edu
Need for full-wave analysis
 Circuit dementions are not negligible compared to wavelength
v j  Li , j
dI i
dt
dIi
dt
c

t  
d

d
coupling NOT instantaneus,
speed of light creates retardation
r
   w m 

 2 A  w 2 m  mJ
2
Need to solve FULLWAVE equations
(same as for RLC extraction plus
wave term)
J

ECE 260B – CSE 241A Parasitic Extraction 56
Slide courtesy L. Daniel
2
 jwA  
 J  0
nˆ  J  jwr
http://vlsicad.ucsd.edu
Industry
 Mentor – xCalibre
 Synopsys – Raphael
 Cadence – Simplex Fire & Ice, Celestry Nautilus
 Frequency – Columbus
 MIT – FastCap, FastHenry, etc.

http://rel-vlsi.mit.edu/fastcap
ECE 260B – CSE 241A Parasitic Extraction 57
Slide courtesy L. Daniel
http://vlsicad.ucsd.edu
Outline
 Problem Statement
 Parasitics
 Extraction Methods




Capacitance Extraction (electrostatic)
RL Extraction (MQS)
Combined RLC Extraction (EMQS)
Electromagnetic Interference Analysis (fullwave)
 Future Trends
ECE 260B – CSE 241A Parasitic Extraction 58
Slide courtesy L. Daniel
http://vlsicad.ucsd.edu
Future Trends
 Accuracy and efficiency improvement to handle
increasing large designs and increasing complex
structures
 Growing inductance effect

What happen on PCB today will be in ASIC tomorrow
 Combining parasitic extraction and model order
reduction to characterize interconnect in Laplace
domain transfer function parameters (poles, residues)
directly
ECE 260B – CSE 241A Parasitic Extraction 59
Slide courtesy L. Daniel
http://vlsicad.ucsd.edu
Parasitic Extraction (the two steps)
Electromagnetic
Analysis
thin volume
filaments
with constant
current
small surface
panels
with constant
charge
million of elements
Model Order
Reduction
tens of elements
ECE 260B – CSE 241A Parasitic Extraction 60
Slide courtesy L. Daniel
http://vlsicad.ucsd.edu
Thanks
ECE 260B – CSE 241A Parasitic Extraction 61
http://vlsicad.ucsd.edu