Lab1 : CPU sim Lab2 : Memory Extended Chips Using Proteus Simulator Lab 1: CPU Sim Objectives : 1 - To create a new machine on CPU Sim with a given set of specifications in a correct way 2- To create an instruction set on a simulated machine on CPU Sim in a correct way 3- To write an assembly language program using a given instruction set on a given machine on CPU Sim in a correct way • The main points should be revised for Lab - A program consist of some instructions , each instruction consist of some microinstructions which is the atomic operation of a CPU. - instruction is executed in two cycles : (Fetch cycle ) and ( execute cycle) Fetch cycle : fetch instruction from memory to instruction register . Execute cycle : execute the instruction in IR . Fetch cycle MAR PC MBR IR Mem C.U Fetch Microinstructions : T1 T2 T3 T4 T5 - MAR IR (Address field) MDR (Memory) IR (MDR) PC PC + 1 decode – ir Execute Cycle example LOAD microinstructions : MAR MDR ACC LOAD IR (Address field) (Memory) (MDR) Address field MAR ACC MBR Mem 1. construct Hardware modules : 2. set registers and main memory 3. setting the microinstructions required 4. design the microinstruction that transfer data between registers 5. Design the microinstruction that transfer data between registers and memory 6. Design the microinstruction that increment the PC with 2 because memory is byte addressable 7. Design the microinstruction that decode the IR registers 8. Design fetch sequence 9. Design jmpz instruction: jump if last Arithmetic operation is zero 10. Design the microinstructions of Jmpz Lab2: Memory Extended Chips Using Proteus Simulator Objectives: - learn how to use Proteus simulation to simulate memory using chip 7489 Tools: - Proteus version 7.4 - Memory chips 16 X 4 bit “No 7489” - 7 SEG display 1. Fetch 7489 memory chips from pick devices 2. The basic memory chip connection