55:035
Computer Architecture and
Organization
Lecture 1
Introduction

Introduction
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
Description
Course Outline
Administrative
 Brief History of Computers
 Overview of Computer Organization
 Overview of Computer Performance
 Case Study: Intel Processors

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Introduction

Description from ISIS

Basic concepts; computer evolution, register transfer
level design, simulation techniques, instruction sets
(CISC and RISC), assembly language programming,
ALU design, arithmetic algorithms and realization of
arithmetic functions, hardwired and microprogrammed control, memory hierarchies, virtual
memory, cache memory, interrupts and DMA,
input/output; introduction to high-performance
techniques, pipelining, multiprocessing; introduction
to hardware description languages (Verilog, VHDL);
students design and simulate a simple processor.
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Introduction

Course Outline

Introduction [chap 1] (2)
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Brief History
Overview of Computer Organization
Architecture: Instruction Set Design [chap 2] (6)
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Information representation & arithmetic operations
Instruction Formats, Addressing Modes
Assembly language Programming
Basic input/output operations
Subroutine linkage
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Introduction
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Course Outline, cont’d
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Case Studies of Instruction Set Architecture [chap. 3]
(4)
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Motorola M68000
ARM
Intel Pentium
Computer Arithmetic and ALU Design [chap. 6] (6)
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Addition (Subtraction)
Multiplication (Division)
Shifting and Rotating
Floating Point Arithmetic
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Introduction
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Course Outline, cont’d
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Verilog / VHDL Tutorials [Supplemental material] (6)
Memory [chap 5] (6)
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Semiconductor Memory Technology
Cache Memory
Virtual Memory
Memory Management and Case Studies
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Introduction
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Course Outline, cont’d
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Processor Design [chap 7] (6)
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Input/Output [chap 4] (4)
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Datapath design
Control Unit Design
Microprogramming
Exception Handling
Device Interfacing and Addressing
Interrupts
Bus Design
Additional topics [selected from chapters 8-12]
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Administrative

Lectures
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Instructor
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Time: M/W/F 8:30 - 9:20 AM
Room: 4030 SC
James Maxted: jmaxted@engineering.uiowa.edu
Design engineer for Rockwell Collins (35 years)
Office: 1126 SC, hours M/W/F 9:30 - 10:20 AM
TA


Dakai Jin: dakai-jin@uiowa.edu
Office: 1313 SC, hours
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Administrative (cont’d)
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Grading
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Approximately 1 homework per week
1 multi-part project
2 exams (1 mid-term, final)
Weighting
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Homework 14%
Project 36%
Midterm 20%
Final 30%
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Administrative (cont’d)
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Course webpage
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Place to find syllabus, lecture notes, homework, etc
http://www.engineering.uiowa.edu/~carch/
Project
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
Design and simulate a simple processor
Mentor Graphics tools
VerilogHDL
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Administrative (cont’d)
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Collaboration
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Discussion of the material is encouraged, but…
All students are expected to do their own work
Disabilities

Please contact me (office hours or email)
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Brief History of Computers

Computing Aids
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Abacus and Counters
 Abacus: Greek for board or slab
 Probably originated in Middle East
 Invented 2000+ years ago

Napier’s Rods (Bones)
 Assisted multiplication, square roots, and
cube roots
 Invented around 1600


Chalk Board
Interest Table
 Shows interest for varying principles and
periods of time
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Brief History of Computers

Machines that Calculate or Control

Adding machines
 Blaise Pascal’s “Pascaline”
 1642

Automatic loom
 Punch cards used to control a
manufacturing process
 1800

Cash register
 “Incorruptible cashier”
 1900
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Brief History of Computers

Electromechanical Devices

Hollerith 1890 Census Tabulator
 Punch, tabulator and sorting box
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International Business Machines (IBM)
 Accounting Machines
 Changed circuits by moving cables in
plugboards
 Early 1900s

Ciphering and deciphering
 Encode and decode secret messages
during World War II
 Enigma and Bombe
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Brief History of Computers

Electronic Computers

Vacuum tube
 ENIAC: 17,000 tubes, 30 tons, 1800 ft2
 1945

Transistor
 IBM System/360 Family
 Compatible processors, Standardized
peripherals and connections
 1962

Integrated circuit
 IBM PC
 Intel 8088
 1981
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Brief History of Computers
The First
Programmer
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
Ada Augusta or Charles Babbage
Robert Campbell, Richard Bloch, Grace
Murray Hopper, or Howard Aiken
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John von Neumann - IAS
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von Neumann Architecture
Sequential operation
 Automatic (without human intervention)
 Five elements:
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Input
Output
Memory
Arithmetic Unit
Control
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Revised von Neumann Architecture
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The Stored Program Concept
Programming the Harvard Mark I was by
external paper tape
 The ENIAC was “programmed” by rewiring it
completely!

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The First Business Computer
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LEO — Lyons Electronic Office — 1950
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UNIVAC — Universal Automatic Computer —
1951 for the Census Bureau
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Modeled after the EDSAC
Perhaps the first mass produced machine
ERMA — Electronic Recording Means of
Accounting —1957 for Bank of America
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The First Bug
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Basic functional units of a computer
Arithmetic
and
logic
Input
Memory
Output
Control
Processor
I/O
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Connections between the processor and the memory
Memory
MAR
MDR
Control
PC
R0
R1
Processor
IR
ALU
R
n- 1
n general purpose
registers
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Single-bus structure
Input
Output
Memory
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Processor
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Sharing the processor
Printer
Disk
OS
routines
Program
t
0
t1
t2
t3
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t4
Time
t5
26
The processor cache
Main
memory
Cache
memory
Processor
Bus
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Basic Performance Equation
N S
T
R
N is the actual number of instruction executions
S is the average number of basic steps needed to
execute one machine instruction
R is the clock rate
T is the processor time required to execute a program
that has been prepared in some high-level language
Instruction Sets: CISC and RISC
RISC – Reduced Instruction Set Computers
(smaller S likely leads to larger N)
 CISC – Complex Instruction Set Computers
(larger S likely leads to smaller N)

N S
T
R
Performance Measurement
System Performance Evaluation Corporation
SPEC rating for a benchmark =
Running time on the ethalon reference computer
Running time on the computer under test
 n

SPEC raiting    SPECi 
 i 1

1
n
n is the number of the benchmarks programs in the
suite
Intel Processors: 4004
 First microprocessor (1971)
 For Busicom calculator
 Characteristics
 10 mm process
 2300 transistors
 400 – 800 kHz
 4-bit word size
 16-pin DIP package
 Masks hand cut from Rubylith
 Drawn with color pencils
 1 metal, 1 poly (jumpers)
 Diagonal lines (!)
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Intel Processors: 8008
 8-bit follow-on (1972)
 Dumb terminals
 Characteristics
 10 mm process
 3500 transistors
 500 – 800 kHz
 8-bit word size
 18-pin DIP package
 Note 8-bit datapaths
 Individual transistors visible
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Intel Processors: 8080
 16-bit address bus (1974)
 Used in Altair computer
 (early hobbyist PC)
 Characteristics
 6 mm process
 4500 transistors
 2 MHz
 8-bit word size
 40-pin DIP package
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Intel Processors: 8086 / 8088
 16-bit processor (1978-9)
 IBM PC and PC XT
 Revolutionary products
 Introduced x86 ISA
 Characteristics
 3 mm process
 29k transistors
 5-10 MHz
 16-bit word size
 40-pin DIP package
 Microcode ROM
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Intel Processors: 80286
 Virtual memory (1982)
 IBM PC AT
 Characteristics
 1.5 mm process
 134k transistors
 6-12 MHz
 16-bit word size
 68-pin PGA
 Regular datapaths and
ROMs
Bitslices clearly visible
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Intel Processors: 80386
 32-bit processor (1985)
 Modern x86 ISA
 Characteristics
 1.5-1 mm process
 275k transistors
 16-33 MHz
 32-bit word size
 100-pin PGA
 32-bit datapath,
microcode ROM,
synthesized control
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Intel Processors: 80486
 Pipelining (1989)
 Floating point unit
 8 KB cache
 Characteristics
 1-0.6 mm process
 1.2M transistors
 25-100 MHz
 32-bit word size
 168-pin PGA
 Cache, Integer datapath,
FPU, microcode,
synthesized control
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Intel Processors: Pentium
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Superscalar (1993)
 2 instructions per cycle
 Separate 8KB I$ & D$
Characteristics
 0.8-0.35 mm process
 3.2M transistors
 60-300 MHz
 32-bit word size
 296-pin PGA
Caches, datapath,
FPU, control
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Intel Processors: Pentium Pro/II/III
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Dynamic execution (1995-9)
 3 micro-ops / cycle
 Out of order execution
 16-32 KB I$ & D$
 Multimedia instructions
 PIII adds 256+ KB L2$
Characteristics
 0.6-0.18 mm process
 5.5M-28M transistors
 166-1000 MHz
 32-bit word size
 MCM / SECC
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Intel Processors: Pentium 4
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Deep pipeline (2001)
 Very fast clock
 256-1024 KB L2$
Characteristics
 180 – 90 nm process
 42-125M transistors
 1.4-3.4 GHz
 32-bit word size
 478-pin PGA
Units start to become
invisible on this scale
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Intel Processors: Core 2 Duo
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2006
Characteristics
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65nm and 45nm
291 million transistors
2.5 GHz+ operation
32-bit word size
LGA775
Dual core
14 stage pipeline
Each gets L1 instruction
and data caches
Shared L2 cache
Source: Intel
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Transistors in Intel Processors
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Clock Frequencies of Intel uP
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Intel Summary

104 increase in transistor count, clock frequency
over 30 years!
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Clock Increases Have Slowed
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Levels of Abstraction
DEVICE
RTL
+
A <= B + C;
GATE
TRANSISTOR
S
n+
PHYSICAL
G
D
n+
Adapted from “Digital Integrated Circuits” copyright 2003 Prentice Hall/Pearson
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Levels of Abstraction (cont’d)
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