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ISA I
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CPU
Time
= Seconds
Program
= Instructions x Cycles
Program
Instruction
x Seconds
Cycle
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CPI
“Average cycles per instruction”
CPIave = (CPU Time * Clock Rate) / Instruction Count
= Clock Cycles / Instruction Count
n
CPU time = ClockCycleTime *
CPI i
i =1
* Ii
n
CPI =
 CPI i
i =1
*
F
i
where F
i
=
I
i
Instruction Count
"instruction frequency"
Invest Resources where time is Spent!
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MIPS Assembly Language
I/O
CPU
Control
Datapath
Memory
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MIPS Assembly Language
• CPU Datapath (extremely simplified)
Operation
Operand 1
Registers Operand 2
ALU
Result
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Basic Architecture Model
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Software Layer
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MIPS Assembly Language Notation
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Register (32 bits)
r0
r1
°
°
°
r31
PC
lo
hi
0
Memory Organization
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32 bits register  8 bits memory
how do byte addresses map onto words?
Can a word be placed on any byte boundary?
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Addressing Objects: Endianess and Alignment
• Big Endian: address of most significant byte = word address (xx00 = Big End of
word)
– IBM 360/370, Motorola 68k, MIPS, Sparc, HP PA
• Little Endian: address of least significant byte = word address (xx00 = Little End of
word)
– Intel 80x86, DEC Vax, DEC Alpha (Windows NT)
3
2
1
little endian byte 0
0
lsb
msb
0
big endian byte 0
1
2
3
Alignment: require that objects fall on address
that is multiple of their size.
Aligned
Not
Aligned
0
1
2
3
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Executing an Assembly Instruction
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Register File Execution
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Register File Execution
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Register File Execution
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Data Access
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Memory Load Operation
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Loading data from Memory
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Loading data from Memory
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MIPS Fields
•
•
•
•
op – operation to be performed
rs – first source operand
rt – second source operand
rd – register destination operand, gets the
result of the operation.
• shamt – shift amount – used in shift instructions.
• funct – selects specific operation of opcode
in op field – R-type……..
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MIPS Assembly Language:
Instruction Set
• 3 different instruction formats
– I-type,
– R-type, &
– J-type (we’ll discuss first two for now)
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R-type instructions
• R-type
– Three register operands
– Arithmetic & logical opcodes
– Format:
6 bits
5 bits
5 bits
5 bits
5 bits
6 bits
Opcode
Rs
Rt
Rd
shamt
function
– Rd = destination operand (output)
– Rs = source operand (input)
– Rt = source operand (input)
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R-type contd..
Page 90
• R-type: 6 fields
6 bits
5 bits
5 bits
5 bits
5 bits
6 bits
Opcode
Rs
Rt
Rd
shamt
function
• R-type at work
– ADD $3,$1,$2
– SUB
$7,$4,$5
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More R-type examples……
• jr $31
• sltu $3, $8, $9
• mult $5, $6
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I-type instructions.
• I-type
– Two registers and an immediate
– Format:
6 bits
5 bits
5 bits
Opcode
Rs
Rt
5 bits
5 bits
6 bits
address
– Rt = destination operand
– Rs = source operand
– Immediate = a constant, also a source operand
• Note: immediate operand must fit into 16
bits! (Why?)
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!Loads & stores are
the data transfer
instructions!
I-type instructions contd…
• I-type: 4 fields
6 bits
5 bits
5 bits
Opcode
Rs
Rt
• I-type at work
– ADDI $2,$1,32
– LUI $7,OxABCD
5 bits
5 bits
address
6 bits
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More I-type examples
• lw $5, 60($4)
• sw $5, 60($4)