 Want sequential circuit with particular behavior over time clk b
Controller x laser patient
 Example: Laser timer


Push button: x=1 for 3 clock cycles
How? Let’s try three flip-flops


 b=1 gets stored in first D flip-flop
Then 2nd flip-flop on next cycle, then 3rd flip-flop on next
OR the three flip-flop outputs, so x should be 1 for three cycles b
D Q clk
D Q D Q x


Trial and error is not a good design method


Will we be able to “guess” a circuit that works for other desired behavior?
 How about counting up from 1 to 9? Pulsing an output for 1 cycle every 10 cycles? Detecting the sequence 1 3 5 in binary on a 3-bit input?
And, a circuit built by guessing may have undesired behavior
 Laser timer: What if press button again while x=1? x then stays one another
3 cycles. Is that what we want?


Combinational circuit design process had two important things :
1.
A formal way to describe desired circuit behavior
2.
 Boolean equation, or truth table
A well-defined process to convert that behavior to a circuit
We need those things for sequential circuit design


Outputs: x
Finite-State Machine (FSM) x=0
 A way to describe desired behavior of sequential circuit
Off clk ^

 Akin to Boolean equations for combinational behavior
List states, and transitions among states




Example: Make x change toggle (0 to
1, or 1 to 0) every clock cycle
Two states: “Off ” (x=0), and “On”
(x=1)
Transition from Off to On, or On to
Off, on rising clock edge
Arrow with no starting state points to initial state (when circuit first starts) clk ^ x=1
On
4

Outputs: x x=0 clk ^ clk ^ 

Want 0, 1, 1, 1, 0, 1, 1, 1, ...
 Each value for one clock cycle
Can describe as FSM


Four states
Transition on rising clock edge to next state
Off clk x=1
On1 clk ^ x=1
On2
State clk ^ x=1
On3
Off On1On2 On3 Off On1 On2 On3 Off
Outputs: x
5






Four states
Wait in “Off ” state while b is 0 (b’)
When b is 1 (and rising clock edge), transition to On1
 Sets x=1
 On next two clock edges, transition to On2, then On3, which also set x=1
So x=1 for three cycles after button pressed
Description is explicit about what happens in “repeat input” case!
Inputs: b; Outputs: x x=0
Off b ’*clk ^ clk ^ b*clk ^ x=1 clk ^
On1 x=1
On2 clk ^ x=1
On3
6

 Showing rising clock on every transition: cluttered
 Make implicit -- assume every edge has rising clock, even if not shown
Inputs: b; Outputs: x x=0
Off b’ *clk ^ clk ^ b *clk ^ x=1 clk ^
On1 x=1
On2 clk ^ x=1
On3
 What if we wanted a transition
without a rising edge


We don’t consider such asynchronous
FSMs -- less common, and advanced topic
Only consider synchronous FSMs -rising edge on every transition
Inputs: b; Outputs: x x=0
Off b ’ b x=1
On1 x=1
On2 x=1
On3
Note: Transition with no associated condition thus
7

 FSM consists of





Set of states
 Ex: {Off, On1, On2, On3}
Set of inputs, set of outputs
 Ex: Inputs: {b}, Outputs: {x}
Initial state
 Ex: “Off ”
Set of transitions


Describes next states
Ex: Has 5 transitions
Set of actions


Sets outputs while in states
Ex: x=0, x=1, x=1, and x=1
Inputs: b; Outputs: x x=0
Off b ’ b x=1
On1 x=1
On2 x=1
On3
We often draw FSM graphically, known as state diagram
Can also use table (state table), or textual languages
8



Many new car keys include tiny computer chip
 When car starts, car’s computer
(under engine hood) requests identifier from key
 Key transmits identifier


4-bits, one bit at a time
If not, computer shuts off car
FSM
 Wait until computer requests ID
(a=1)
 Transmit ID (in this case, 1101)
Wait r=0 a
K1 r=1 a ’
K2 r=1
Inputs: a; Outputs: r
K3 r=0
K4 r=1
9

 Nice feature of FSM


Can evaluate output behavior for different input sequence
Timing diagrams show states and output values for different input waveforms clk
Inputs a
State
Outputs r
Wait Wait K1 K2 K3 K4 Wait Wait
Wait r=0 a
K1 r=1 a ’
K2 r=1
Inputs: a; Outputs: r
K3 r=0
K4 r=1
Q: Determine states and r value for given input waveform: clk
Inputs a
Wait Wait K1 K2 K3 K4 Wait K1 State
Output r
10




Unlock door (u=1) only when buttons pressed in sequence:
 start, then red , blue , green , red
Start
Red s r g
Code detector u
Door lock
Input from each button: s, r, g, b
 Also, output a indicates that some colored button is being pressed
Green
Blue b a
FSM
 Wait for start (s=1) in “Wait”
 Once started (“Start”)




 u=0
Wait s s ’ ar ’ ab ’ ag ’
Inputs: s,r,g,b,a; ar ’
Outputs: u
If see red, go to “Red1”
Then, if see blue, go to “Blue”
Then, if see green, go to “Green”
Then, if see red, go to “Red2”
 In that state, open the door (u=1)
Wrong button at any step, return to “Wait”, without opening door
Start u=0 ar
Red1 u=0 a ’ ab a ’
Blue u=0 ag a ’
Green u=0 ar a ’
Red2 u=1
Q: Can you trick this FSM to open the door, without knowing the code?
A: Yes, hold all buttons simultaneously
11

Inputs: s,r,g,b,a;
Outputs: u
Wait u=0 s s’ ar’ ab’ ag’ ar’
Start u=0 ar a ’
Red1 u=0 ab a ’
Blue u=0 ag a ’
Green u=0 ar a ’
Red2 u=1
Note: small problem still remains; we’ll discuss later


New transition conditions detect if wrong button pressed, returns to “Wait”
FSM provides formal, concrete means to accurately define desired behavior
12

a
 Only one condition should be true
 For all transitions leaving a state
 Else, which one?
b ab=11 – next state?
a a ’b
 One condition must be true


For all transitions leaving a state
Else, where go?
13

 Can verify using Boolean algebra



Only one condition true: AND of each condition pair (for transitions leaving a state) should equal 0  proves pair can never simultaneously be true
One condition true: OR of all conditions of transitions leaving a state) should equal 1  proves at least one condition must be true
Example a a ’b
Answer: a * a’b
= (a * a’) * b
= 0 * b
= 0
OK!
a + a’b
= a*(1+b) + a’b
= a + ab + a’b
= a + (a+a’)b
= a + b
Fails! Might not be 1 (i.e., a=0, b=0)
Q: For shown transitions, prove whether:
* Only one condition true (AND of each pair is always 0)
* One condition true (OR of all transitions is always 1)
14

 Recall code detector FSM


We “fixed” a problem with the transition conditions
Do the transitions obey the two required transition properties?
 Consider transitions of state Start, and the “only one true” property ar * a’ a’ * a(r’+b+g)
= (a*a’)r = 0*r
= 0 = 0
Wait u=0 s
Start u=0ar
Red1 u=0 s ’ a
’ ab a
’ ar * a(r’+b+g)
= (a’*a)*(r’+b+g) = 0*(r’+b+g)
= (a*a)*r*(r’+b+g) = a*r*(r’+b+g)
= arr’+arb+arg
Blue u=0 ag a
’
Green u=0 ar a
’
Red2 u=1
Intuitively: press red and blue buttons at same time: conditions ar, and a(r’+b+g) will both be true. Which one should be taken?
= 0 + arb+arg
= arb + arg
Q: How to solve?
= ar(b+g)
Fails! Means that two of Start’s transitions could be true
A: ar should be arb’g’
(likewise for ab, ag, ar)
Note: As evidence the pitfall is common, the author of this example admitted the mistake was not intentional
– A reviewer of his book caught it.
15

1.

Determine what needs to be remembered
What will be stored in memory?
2.
Encode the inputs and outputs in binary (if necessary)
3.

Construct a state diagram of the behavior of the desired device
Optionally – minimize the number of states needed
4.
Assign each state a binary number (code)
5.

Choose a flip-flop type to use
Derive the flip-flop input maps
6.
Produce the combinational logic equations and draw the schematic from them




Design a circuit that has input w and output z
All changes are on the positive edge of the clock
The output z = 1 only if w = 1 for both of the two preceding clock cycles
 Note: z does not depend on the current w
 cycle: t
0 w: 0 z: 0
Sample timing: t
1
1
0 t
2
0
0 t
3
1
0 t
4
1
0 t
5
0
1 t
6
1
0 t
7
1
0 t
8
1
1 t
9
0
1 t
10
1
0




What needs to be remembered?
Previous two input values
If both are 1, then z = 1 at next positive clock edge




Possible “states” are
A: seen 10 or 00  output z = 0
B: seen 01  output z = 0, but we’re almost there!
C: seen 11  output z = 1
 Step 2 is trivial since the inputs and outputs are already in binary

 Corresponding state diagram w = 1 w = 0 A
 z = 0 w = 0 w = 0
B
 z = 0 w = 1
C
 z = 1 w = 1




Assign binary numbers to states
Since there are 3 states, we need 2 bits
2 bits  2 flip-flops


Many assignments are possible



One obvious one is to use:
A: 00 (or 10 instead)
B: 01
C: 11


This choice may not be “optimal”
State assignment is a complex topic all to itself!

w = 0
w = 1

= 0

= 0 w = 0 w = 0 w = 1

= 1 w = 1 current state
Q2 Q1
0 0
0 1
1 0
1 1 w = 0
Q2 Q1
0 0
0 0 x x
0 0 next state w = 1
Q2 Q1
0 1
1 1 x x
1 1 z x
1
0
0

 A 2 flip-flop design now has the form w
Combinational circuit
Combinational circuit z
Clock




Choose a flip-flop type
The choice DOES impact the cost of the circuit
The choice need not be the same for each flip-flop



Regardless of type of flip-flop chosen


Need to derive combinational logic for each flip-flop input in terms of w and current state
Use K-maps for minimum SOP for each
Need to derive combinational logic for z in terms of w and current state
Use K-map for this also
 Suppose we choose D type …

current state
Q2 Q1
0 0
0 1
1 0
1 1
w = 0
Q2 Q1
0 0
0 0 x x
0 0 next state w = 1
Q2 Q1
0 1
1 1 x x
1 1
0 x z
0
1
Q2Q1 w
0
00 01 11 10
0 0 1 x
1 0 0 1 x z = Q2
Q2Q1 w
0
00 01 11 10
0 0 0 x
1 0 1 1 x
D2 = w Q1
Q2Q1 w
0
00 01 11 10
0 0 0 x
1 1 1 1 x
D1 = w

w = 0
w = 1

= 0

= 0 w = 0 w = 0

= 1 w = 1
Different state assignments can have quite an effect on the resulting implementation cost next state w = 1 current state
Q2 Q1
0 0
0 1
1 0
1 1 w = 0
Q2 Q1
0 0
0 0
0 0 x x w = 1
Q2 Q1
0 1
1 0
1 0 x x z
1 x
0
0

current state
Q2 Q1
0 0
0 1
1 0
1 1
w = 0
Q2 Q1
0 0
0 0
0 0 x x next state w = 1
Q2 Q1
0 1
1 0
1 0 x x z
0
0
1 x
Q2Q1 w
0
00 01 11 10
0 0 x 0
1 0 1 x 1
Q2Q1 w
0
D2 = w Q1 + w Q2
= w (Q1+Q2)
00 01 11 10
0 0 x 0
1 1 0 x 0
D1 = w Q2' Q1'

 Cost increases due to extra combinational logic



A finite state machine in which the outputs do not directly depend on the input variables is called a Moore machine
Outputs are usually associated with the state, since they do not depend on the input values


Also note that the choice of flip-flop does not change the output logic
Only one K-map need be done regardless of the choice of flipflop type



If the output does depend on the input, then the machine is a Mealy machine
This is more general than a Moore machine
If required, then Mealy machine.
If not required, then Moore machine.
W
Combinational circuit
Clock
Flip-flops
Q
Combinational circuit
Z

 Redesign the “sequence of two 1's” example so that the output z = 1 in the same cycle as the second 1
 cycle: t
0 w: 0 z: 0

Compare the Moore and Mealy model outputs:
Moore model t
1
1
0 t
2
0
0 t
3
1
0 t
4
1
0 t
5
0
1 t
6
1
0 t
7
1
0 t
8
1
1
 Mealy model cycle: t
0 w: 0 z: 0 t
1
1
0 t
2
0
0 t
3
1
0 t
4
1
1 t
5
0
0 t
6
1
0 t
7
1
1 t
8
1
1 t
9
0
0 t
9
0
1 t
10
1
0 t
10
1
0



Mealy machines have outputs associated with the transitions
Moore machines have outputs associated with the states – that's why the output does not depend on the input w = 1
 z = 0 w = 0
 z = 0 A B w = 1
 z = 1 w = 0
 z = 0




Only 2 states needed, so only 1 flip-flop required
State A: 0
State B: 1 w = 1
 z = 0 w = 0
 z = 0 w = 1
 z = 1 A B w = 0
 z = 0 next state output current state
Q
0
1 w = 0 w = 1 w = 0 w = 1
Q Q z z
0
0
1
1
0
0
0
1

 The outputs still do not depend on the choice of flipflops, but they do depend on the inputs next state output current state
Q
0
1 w = 0 w = 1 w = 0 w = 1
Q Q z z
0
0
1
1
0
0
0
1 w
0
Q 0 1
0 0 w
0
Q 0 1
0 0
1 1 1
D = w
1 0 1 z = w Q

z = 1since w = 1 on both sides of posedge clock z = 0 since w = 0 even though no posedge clock has occurred – level sensitive output!



Mealy machines often require fewer flip-flops and/or less combinational logic
But output is level sensitive
 To modify a Mealy design to behave like a Moore design, just insert a D flip-flop to synchronize the output





As usual, CAD tools can automate much of the design process, but not all of it
Deriving the state diagram is still an art and requires human effort
 Obviously, we could design everything and then just implement the design using schematic capture


Or … we can use Verilog to represent the FSM and then allow the CAD tool to convert that FSM into an implementation
Automates state assignment, flip-flop selection, logic minimization, and target device implementation

 The design process is about determining the two combinational circuits below and linking them by flipflops next state current state
Y y w
Combinational circuit
Combinational circuit z
Y y
Clock

w = 0
ResetN=0
A
 z 0 w = 0 w = 1
B
 z 0 w = 0 w = 1
C
 z 1 w = 1 state transition logic flip-flops required z = 1 if previous two consecutive w inputs were 1 – Moore machine style output logic




The Verilog coding style is very important
You need to code in such a way that the Verilog compiler can effectively use FSM techniques to create good designs
Use of the parameter statement or `define is a must for detecting FSM specifications


Also, note that testing whether your design is correct can be a challenge
The two faces of CAD: synthesis and verification
 How much testing is enough testing?


What does “testing” look like?
Use input test vectors and check the outputs for correctness

 Same example, but only one always block
 Both approaches work well in CAD tools

A
Enable=0
Enable=1
B
Rout
2
=1
Rin
3
=1
Enable=0,1
C
Rout
1
=1
Rin
2
=1
Enable=0,1
D
Rout
3
=1
Rin
1
=1
Done=1
Enable=0,1



Bus controller receives requests for access to a shared bus
Requests on separate lines: R0, R1, R2, R3


Controller grants request via a one-asserted output
4 separate grant lines G0, G1, G2, G3 : one asserted


Priority given to lowest numbered device device 0 > device 1 > device 2 > device 3


No interrupts allowed
Device uses bus until it relinquishes it







5 states
A: bus idle
B: device 0 using the bus
C: device 1 using the bus
D: device 2 using the bus
E: device 3 using the bus
R[0:3] = 0000
A / G[0:3] = 0000
0000 notation used
A/ 0000

0000
A/ 0000
1xxx
B/ 1000
1xxx
0xxx
01xx x0xx
001x xx0x 0001 xxx0 x1xx
C/ 0100 xx1x
D/ 0010 xxx1
E/ 0001

 Note that when a device de-asserts its request line, a cycle is wasted in returning to the idle state (A)



If another request were pending at that time, why can't the bus controller simply transfer control to that device?
It can, but we need a more complex FSM for that
Same number of states, just many more transitions



Once a device is granted access, it controls the bus until it relinquishes control
Higher priority devices must wait


Can we change the behavior so that high priority devices can preempt lower priority devices and take over control?
Of course!


Can we combine preemption with the removal of the idle cycle?
Yes ….

0000
A/ 0000
1xxx
B/ 1000
1xxx
0xxx
01xx x0xx
001x xx0x 0001 xxx0 x1xx
C/ 0100 xx1x
D/ 0010 xxx1
E/ 0001

0000
A/0000
1xxx
B/1000
1xxx
0000
1xxx
01xx
01xx
01xx
0000
001x
0000 0001
0000
001x
C/0100
01xx
001x
D/0010
001x
0001
1xxx
0001
001x
01xx
0001
1xxx
E/0001
0001



Deliver one pack of gum for 15 cents
So it’s cheap gum. So what! Maybe it's just one stick.



One slot for all coins
Can detect nickels and dimes separately
We’ll assume that you can’t insert BOTH a nickel and a dime in the same clock cycle
 No change given!
nickel detected dime detected clock vending machine controller release gum

w = 0
 z = 0 w = 1
 z = 0
A w = 0
 z = 0
B w = 1
 z = 1
Mealy outputs are associated with the transitions