Implementation of a Low Leakage Standard Cell Library
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Implementation of a Low Leakage Standard Cell Library based on materials from UMC 65nm technology Theodoros Simopoulos Comp. Engineering & Informatics University of Patras Greece Themistokles Haniotakis Comp. Engineering & Informatics University of Patras Greece George Alexiou Comp. Engineering & Informatics University of Patras Greece simopoulos@ceid.upatras.gr haniotak@ceid.upatras.gr alexiou@ceid.upatras.gr CEID STD LIB There are others Reasons to implement a Standard Cell Library 1.To have the know how 2.To alter the layout 3.Able to implement custom cells CEID STD LIB MACRO CHARACTERISTICS The CEID STD LIB is: Complete Combinational Cells LATCHES DFFs Cell Name Cell Description QDLATE QDFFC Positive clock Enable triggered triggered DD type type Flip-Flop Latch QDLATNE QDFFNC Negative clock Enable triggered triggered DD type type Flip-Flop Latch Positive clock Enable triggered triggered DD type type Flip-Flop Latch with QDFFCR QDLATER Driving Driving Reset Reset Driving Name Cell Name with Cell Name Sequential Cell Cells Strength Strength Strength Cell Driving Negative clock Enable triggered triggered DD type type Flip-Flop Latch with Cell Description QDLATNENR QDFFNCNR X1 X2 X4 Name X1 X2 X4 Strength X1 X2 X4 negative with negative ResetReset Support Cells INV XOR2 X1 QDLATENS QDFFCS INVEN XNOR2 TIE0 BUF FA1 Ready to synthesis TIE1 QDLATNENS QDFFNCNS BUFEN HA1 NAND2 FILL MUX2 Timing characterized QDLATESR QDFFCSR AND2 MUX4 Total 81Cells NOR2 MUX2B QDLATNESR QDFFNCNSR Area characterized OR2 AOI21D Dtype Flip-Flop with X2 X4 clock Positive Enable triggered triggered type Latch negative with AOI211 Set Set Output is tight to logic‘0’ Negative Enable triggered triggered DD type type Flip-Flop Latch AOI22 clock Output is tight to logic ‘1’ with negative with negative Set Set OAI21gap filler cells Placement Positive clock Enable triggered triggered DD type type Flip-Flop Latch with OAI211 Set and with SetReset and Reset OAI22 with Negative clock Enable triggered triggered DD type type Flip-Flop Latch Set and with negative Reset Set and Reset CEID STD LIB MICRO CHARACTERISTICS The CEID STD LIB CELLS: Are implemented on CMOS Logic Support 6 Views Most have 3 driving strengths X1 => nmos 150nm, pmos 300nm X2 => nmos 300nm, pmos 600nm X4 => nmos 600nm, pmos 1.2um INVX2 INVX4 AOI22 INV X1 1/2 CEID STD LIB MICRO CHARACTERISTICS The CEID STD LIB CELLS: Have height 2.3 um (snap bounding box) 2.52um (from rail to rail) Height is smallest possible to support only two metal layers to support horizontal & vertical expantion 2/2 CEID STD LIB CELL EXPANTION INVERTER •Vertical expantion from X1 to X2 •Horizontal expantion from X2 to X4 (Due to LIB usage target) CEID STD LIB CELL ABUTMENT •Horizontal abutment •Vertical abutment Layout grid result 0.14um (1 pitch = 28nm) CEID STD LIB MACRO GENERATION •Macro Synthesis •Placing and Routing a Macro •Importing the Layout of a Macro 1616Bit 32 Bit Cortex M0DS, unit, BitAdder-Subtracter Shift functions unit, Set-Reset register, 22 2 744um 0.046 mm Area: Area:0.0012mm 222um (c) (f) (e) (a) CEID STD LIB LIBRATY VERIFICATION Test design : a Hierarchical 16 Bit ALU DOWNLOAD THE LIBRARY http://www.ceid.upatras.gr/webpages/courses/vlsilab/ceidStdLib.html OUR FUTURE WORK 1. Second Variation • Cells expands only horizontaly • More metal levels inserted • v2 Lib targets projects 2. A Memory Library is on the way (First results are estimated)
