EE 5323 – VLSI Design I
Adders
Kia Bazargan
University of Minnesota
Fall 2008
EE 5323 - VLSI Design I - © Kia Bazargan
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References and Copyright
• Textbooks referenced
 [WE92] N. H. E. Weste, K. Eshraghian
“Principles of CMOS VLSI Design: A System Perspective”
Addison-Wesley, 2nd Ed., 1992.
 [Rab96] J. M. Rabaey
“Digital Integrated Circuits: A Design Perspective”
Prentice Hall, 1996.
 [Par00] B. Parhami
“Computer Arithmetic: Algorithms and Hardware Designs”
Oxford University Press, 2000.
Fall 2008
EE 5323 - VLSI Design I - © Kia Bazargan
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References and Copyright (cont.)
• Slides used
 [©Hauck] © Scott A. Hauck, 1996-2000;
G. Borriello, C. Ebeling, S. Burns, 1995,
University of Washington
 [©Prentice Hall] © Prentice Hall 1995, © UCB 1996
Slides for [Rab96]
http://bwrc.eecs.berkeley.edu/Classes/IcBook/instructors.html
 [©Oxford U Press] © Oxford University Press,
New York, 2000
Slides for [Par00]
With permission from the author
http://www.ece.ucsb.edu/Faculty/Parhami/files_n_docs.htm
Fall 2008
EE 5323 - VLSI Design I - © Kia Bazargan
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Why Adders?
• Addition: a fundamental operation
 Basic block of most arithmetic operations
 Address calculation
• Faster, faster and faster
• How?
 Architectural level optimization
 Gate-level optimization
 Speed/area trade-off
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EE 5323 - VLSI Design I - © Kia Bazargan
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Outline
• One-bit adder, basic ripple-carry adder
• Carry-Lookahead adders (CLA)
• Brent-Kung adder
Fall 2008
EE 5323 - VLSI Design I - © Kia Bazargan
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Adding Two One-bit Operands
• One-bit Half Adder:
A
Cout
B
Sum = A  B
HA
Cout = A.B
A
0
0
1
1
B Sum Cout
0 0
0
1 1
0
0 1
0
1 0
1
Sum
• One-bit Full Adder:
A
Cout
B
FA
Sum
Fall 2008
Sum = A  B  Cin
Cin
Cout = A.B + B.Cin
+ A.Cin
EE 5323 - VLSI Design I - © Kia Bazargan
Cin A
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
B Sum Cout
0 0
0
1 1
0
0 1
0
1 0
1
0 1
0
1 0
1
0 0
1
1 1
1
6
N-Bit Ripple-Carry Adder: Series of FA Cells
• To add two n-bit numbers
An-1 Bn-1
C
FA
A2
...
B2
A1
B1
A0
B0
FA
FA
FA
S2
S1
S0
C0
n
Sn-1
• Note: adder delay = Tc * n
• Tc = (Cin:Cout delay)
A
Cou
B
FA
t
Ci
n
Sum
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EE 5323 - VLSI Design I - © Kia Bazargan
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4-bit Ripple Carry Addition: Example
A=0011
B=0101
C4
0
0
0
1
1
0
1
1
A3
B3
A2
B2
A1
B1
A0
B0
FA
C3
S3
FA
C2
S2
FA
C1
S1
FA
C0
0
S0
T=0
T=1
T=2
0
0
0
0
0
0
0
0
S=0000
0
0
0
1
0
1
1
0
S=0110
0
0
0
1
1
0
1
0
S=0100
T=3
T=4
0
0
1
0
1
0
1
0
S=0000
0
1
1
0
1
0
1
0
S=1000
Fall 2008
EE 5323 - VLSI Design I - © Kia Bazargan
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One-bit Full Adder Implementation
• Direct gate implementation
Sum = A  B  Cin
A
B
Cin
Sum
Cout = A.B + B.Cin + A.Cin
= A.B + Cin. (A+B)
A
B
Cin
A
B
Cout
32 Transistors Used
[WE92] p516
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EE 5323 - VLSI Design I - © Kia Bazargan
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One-Bit Full Adder: Share Logic
• An observation
 Almost always,
sum = NOT carry
includes 111
Sum = A.B.Cin +
(A+B+Cin).Cout
Cin A
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
B Sum Cout
0 0
0
1 1
0
0 1
0
1 0
1
0 1
0
1 0
1
0 0
1
1 1
1
excludes 000
Fall 2008
EE 5323 - VLSI Design I - © Kia Bazargan
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One-Bit Full Adder: Transistor Implementation
Cout = A.B + C.(A+B)
A
B
A
B
C
Fall 2008
B
A
A
B
–
–
–
–
28 Transistors
C
Cout
C
A
Sum = A.B.C + (A+B+C).Cout
B
A
B
C
A
B
C Sum
C
B
A
[WE92] p517
Use inverters to get Cout and Sum
[Rab96] p390
C transistors close to output
Cout delay: 2 inverting stages (1-stage possible?)
Sum delay: 3 inverting stages (not an issue, though)
EE 5323 - VLSI Design I - © Kia Bazargan
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Outline
• One-bit adder, basic ripple-carry adder
• Carry-Lookahead adders (CLA)
• Brent-Kung adder
Fall 2008
EE 5323 - VLSI Design I - © Kia Bazargan
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Carry-Lookahead Adder: Idea
• New look: carry propagation
• Idea:
 Try to “predict” Ck earlier than Tc*k
 Instead of passing through k stages, compute
Ck separately using 1-stage CMOS logic
• Carry propagation: an example
Bit position
7
6
5
4
3
2
1
Carry
1
0
0
1
1
1
1
0
0
1
1
0
0
0
0
1
0
1
1
0
1
Sum
1
0
0
1
0
1
0
A
B
Fall 2008
EE 5323 - VLSI Design I - © Kia Bazargan
0
1
1
+
0
13
Carry-Lookahead Adder (CLA): One Bit
• What happens to the
propagating carry in
bit position k?
0-propagate
A
B
A B Cin Cout
0
0
1
1
kill
A
0
1
0
1
C
C
-
0 (kill)
C (propagate)
C (propagate)
1 (generate)
B
Cout
C
A
B
1-propagate
Fall 2008
B
A
p = A+B (or A  B)
g = A.B
generate
EE 5323 - VLSI Design I - © Kia Bazargan
[Rab96] p391
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CLA: Propagation Equations
• If C4=1, then either:





g3
g2.p3
g1.p2.p3
g0.p1.p2.p3
Cin.p0.p1.p2.p3
generated at bit pos 3
generated at bit pos 2, propagated 3
generated at bit pos 1, propagated 2,3
generated at bit pos 0, propagated 1,2,3
input carry, propagated 0,1,2,3
• C4 = g3+ g2.p3 + g1.p2.p3 + g0.p1.p2.p3 +
Cin.p0.p1.p2.p3
Implement C4 as a one-stage CMOS logic
 large delay
Fall 2008
EE 5323 - VLSI Design I - © Kia Bazargan
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CLA: 12-Bit Example
A=
B=
A11
1101
0111
A10
A9
A8
B11 B10
B9
B8
p,g
p,g
p,g
A7
p,g
1001
0110
B7
p,g
A6
B6
p,g
A5
B5
A4
p,g
B4
p,g
A3
1010
1101
B3
p,g
A2
B2
p,g
A1
B1
p,g
A0
B0
p,g
0
C0
Carry Generator
Carry Generator
C12
Carry Generator
C8
S11
S10
S9
S8
C4
S7
S6
S5
S4
S3
S2
S1
T=0
0
0000
0
0000
0
0000
T=2
T=3
T=4
1
0100
0
1111
1
0111
1
0100
1
0000
1
0111
1
0101
1
0000
1
0111
Fall 2008
EE 5323 - VLSI Design I - © Kia Bazargan
S0
16
Summary: Carry Lookahead Adder
• CLA compared to ripple-carry adder:
 Faster (“4 times”?),
but delay still linear (w.r.t. # of bits)
 Larger area
o P, G signal generation
o Carry generation circuits
o Carry generation ckt for each bit position (no re-use)
• Limitation: cannot go beyond 4 bits of look-ahead
 Large p,g fan-out slows down carry generation
Fall 2008
EE 5323 - VLSI Design I - © Kia Bazargan
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Outline
• One-bit adder, basic ripple-carry adder
• Carry-Lookahead adders (CLA)
• Brent-Kung adder
Fall 2008
EE 5323 - VLSI Design I - © Kia Bazargan
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Binary Carry-Lookahead or Brent-Kung Adder
• Idea: use binary tree for carry propagation
 logarithmic delay
F
A0
A1
A2
A3
A0
A1
A2
A3
A4
A5
A6
A7
Fall 2008
A4
A5
A6
A7
tp ~ N
F
tp ~ log2(N)
[© Prentice Hall]
EE 5323 - VLSI Design I - © Kia Bazargan
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Brent-Kung Adder
• Basic component
MSB
LSB
(gleft, pleft)
gleft pleft
gright
(gright pright)
pright
(g, p)
g
p
Concatenation
g = gleft + pleft • gright
p = pleft • pright
[©Hauck]
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EE 5323 - VLSI Design I - © Kia Bazargan
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Brent-Kung Adder: Structure
• Define (Gi, Pi)
 generate and propagate for least significant i bits
(G0,P0) = (g0,p0)
gi = Ai.Bi
pi = AiBi
• (Gi-1, Pi-1)
= (gi, pi) • (gi-1, pi-1) • . . . . • (g1, p1)
for i>0: (Gi, Pi) = (gi, pi)
• Key to Brent-Kung adder – use tree structure to
perform concatenations
7 6 5 4 3 2 1
C5 ?
No! Doesn’t know about
C0-3 yet!
Fall 2008
7-6
5-4
3-2
1-0
3-0
7-4
EE 5323 - VLSI Design I - © Kia Bazargan
0
7-0
[©Hauck]
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Brent-Kung: the Complete Tree
(g 0 ,p0 )
(g 1 ,p1 )
(g 2 ,p2 )
C0
C1
C2
C4
C3
C5
(g 3 ,p3 )
(g 4 ,p4 )
(g 5 ,p5 )
C6
(g 6 ,p6 )
C7
(g 7 ,p7 )
tadd ~ log2 (N)
Fall 2008
EE 5323 - VLSI Design I - © Kia Bazargan
[© Prentice Hall]
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Brent-Kung: Timing
x15 x14x13 x12 x
x x
11 10 9
x8 x x x x x x x x
7 6 5
4 3 2 1
0
Level
1
2
3
4
5
6
s15 s14 s13 s12 s s s s s s s s s s s s
11 10 9
8 7 6 5
4 3 2 1
0
Fall 2008
EE 5323 - VLSI Design I - © Kia Bazargan
[Par00] p.102
[©Oxford U Press]
23
Brent-Kung Adder: Summary
• Area
 On average, twice as large as ripple adder
 Layout of the cells is very compact
• Delay
 Logarithmic time
 Once carry signals are ready,
sum bits derived in const time
 Good for wide adders
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EE 5323 - VLSI Design I - © Kia Bazargan
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