Sequential Logic
Building Blocks –
Flip-flops
(Week 9 – Lecture 1 of 1)
1
NAND Gate Latch
The two NAND gates are crosscoupled so that the output of
NAND-1 is connected to one of the
input of NAND-2, and vice versa.
The gate output, labeled Q and Q’,
respectively, are latch out-put.
Under normal conditions, these
output will always be the inverse of
each other.
There are two latch inputs:
a) the SET input is the input that sets Q to the 1 state.
b) The CLEAR input is the input that resets Q to the 0 state.
2
NAND Gate Latch
1
The SET and CLEAR inputs are
both normally resting in the HIGH
state. And One of them will be
pulsed LOW whenever we want to
change the latch outputs.
1
3
NAND Gate Latch ( condition SET =1, RESET = 1)
1
1
0
1
a) When we have Q = 0 and Q’ = 1.
With Q = 0, the inputs to NAND-2 are 0 and 1, which
produce Q’ =1.
The 1 from Q’ causes NAND-1 to have a 1 at both inputs to
produce a 0 output at Q.
In effect, resultant a LOW at the output NAND-1 and HIGH
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at the output NAND-2
NAND Gate Latch ( condition SET =1, CLEAR = 1)
1
1
1
0
b) When we have Q = 1 and Q’ = 0.
With Q = 1, the inputs to NAND-2 are 1 and 1, which produce Q’ =0.
The 0 from Q’ causes NAND-1 to have a input 1 and 0 to produce a 1
output at Q.
In effect, resultant a HIGH at the output NAND-1 and LOW at the
output NAND-2
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NAND Gate Latch ( condition SET =1, CLEAR= 1)
Summary of condition SET = 1 and CLEAR =1.
Thus, there are two possible output states when SET and
CLEAR = 1, which are either Q =0 and Q’ = 1 or Q =1 and Q’
= 0.
The outputs are remain unchanged comparing with previous
state even there is new clock pulse or new input S =1 and R
=1
6
NAND Gate Latch ( setting latch, SET = 0, Clear = 1)
t0 t1
t0 t1
1
t0 t1
a) If Q = 0 and Q’ = 1 at
prior to the occurrence
of the pulse ( the
previous state)
As SET is pulse LOW at time
t0, Q will go High ( Q =
1) . And this cause Q’ to
go LOW ( Q’ = 0).
So that , NAND-1 has two
LOW inputs.
Thus,, when SET returns to the 1 state at t1, the NAND-1 output
remains HIGH, which in turn, keeps the NAND-2 output LOW
7
NAND Gate Latch ( setting latch, SET = 0, Clear = 1)
t0 t1
t0 t1
1
t0 t1
b) If Q = 1 and Q’ = 0 at prior to the occurrence of the pulse ( the
previous state)
As Q’ = 0 is keeping the NAND-1 output remain HIGH, the LOW pulse
will not effect the output of NAND-1.
Thus , when SET returns HIGH at t1, the latch outputs are still in the
Q= 1 and Q’ =0 ( no change state)
8
NAND Gate Latch ( setting latch, SET = 0, Clear = 1)
Summary of condition SET = 0 and CLEAR =1.
Thus, A LOW pulse on the SET input will always cause the latch to
end up in the Q = 1 state and Q’ =0.
This operation is called setting the latch or FF
9
NAND Gate Latch ( resetting latch, SET = 1, Clear = 0)
1
t0 t1
t0 t1
t0 t1
a) If Q = 0 and Q’ = 1 at prior to the occurrence of the pulse ( the
previous state)
As CLEAR is pulse LOW and SET is pulse 1 at time t0, Q’ = 1
Since, Q = 0 is keeping the NAND-2 output HIGH, the LOW pulse at
CLEAR will not have any effect to the output.
When, CLEAR returns HIGH at t1, the latch output are remain Q = 0 10
and
Q’ = 1
NAND Gate Latch ( resetting latch, SET = 1, Clear = 0)
1
t0 t1
b)
t0 t1
t0 t1
If Q = 1 and Q’ = 0 at prior to the occurrence of the pulse ( the
previous state)
As CLEAR is pulse LOW at time t0, Q’ = 1
Since, Q’ = 1 , it will forces Q to go LOW , Q = 0. and now NAND-2 has
two inputs.
Thus, when, CLEAR returns HIGH at t1, the latch output NAND-2 HIGH
and NAND-1 keep LOW
11
NAND Gate Latch ( resetting latch, SET = 1, Clear = 0)
Summary of condition SET = 1 and CLEAR =0.
Thus, A LOW pulse on the CLEAR input will always cause the latch to
end up in the Q = 0 state and Q’ =1.
This operation is called clearing or resetting the latch
12
NAND Gate Latch ( resetting latch, SET = 0, Clear = 0)
0
0


When SET and CLEAR inputs are simultaneously pulsed
LOW, this will produce HIGH levels at both NAND output, Q
= 1 and Q’ = 1.
This is am undesired condition because the two outputs are
supposed to be inverses of each other.
13
NAND Gate Latch ( overall)
1. SET = 1, CLEAR = 1
Resting State (no change)
2. SET = 0, CLEAR = 1
Setting the latch
3. SET = 1, CLEAR = 0
Clearing / Resetting the latch
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4. SET = 0, CLEAR = 0
Invalid state(unpredictable result)
NAND Gate Latch
Example:
Assume that Q = 0 initially, and determine the Q waveform for the NAND
latch input of figure below.
15
NOR Gate Latch
Two cross-coupled NOR gates can be used as a NOR gate latch.
The arrangement is similar to the NAND latch except the Q and
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Q’ output have reversed position.
NOR Gate Latch
1. SET = 0, CLEAR = 0
Resting State (no change)
2. SET = 1, CLEAR = 0
Setting the latch ( Q = 1 )
3. SET = 0, CLEAR = 1
Clearing / Resetting the latch ( Q = 0 )
4. SET = 1, CLEAR = 1
Invalid state(unpredictable result)
17
NOR Gate Latch
Example:
Assume that Q = 0 initially, and determine the Q waveform for the NOR latch
input of figure below.
18
Clock Signals
•Digital system operate either asynchronously or synchronously.
•Asynchronous systems - outputs of logic circuit can change state any time
one or more of the inputs change.
•Synchronous systems - the exact time any output can change states are
determined by the clock signal.
•Clock signal is a rectangular pulse train or square wave.
19
Clock Signals
•Positive-going transition (PGT) - clock change from 0 to 1
•Negative-going transition (NGT) - clock change from 1 to 0
20
Clock Signals
•Clocked Flip Flops have a clock input (CLK) that is active on
either the PGT or the NGT.
•The control inputs determine the effect of the active clock
transition.
21
Clocked S-C Flip-Flop
Clocked S-C flip-flop with positive-going edge trigger.
22
Clocked S-C Flip-Flop
Clocked S-C flip-flop with negative-going edge trigger.
23
Logic Diagram of Clocked S-C / S-R Flip-Flop
24
Clocked S-C Flip-Flop
Waveform of the
Clocked S-C flipflop with positivegoing edge trigger.
25
Clocked J-K Flip-Flop
Clocked J-K flip-flop with positive-going edge trigger.
26
Clocked J-K Flip-Flop
Clocked J-K flip-flop with negative-going edge trigger.
27
Logic Diagram for a Clocked J-K Flip-flop
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Clocked J-K Flip-Flop
Waveform of the Clocked J-K flip-flop with positive-going edge trigger.
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Clocked D Flip-Flop
Implementation of the D Flip-Flop.
An edge-triggered D flip-flop is easily implemented by adding a single
INVERTER to the edge-triggered J-K flip-flop.
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Clocked D Flip-Flop
D Latch (Transparent Latch).
•Q output will follow D as long as EN is
HIGH.
•If EN goes LOW, Q output will become
latched to the value that D.
31
Clocked D Flip-Flop (Example):
Assume that Q = 0 initially. Determine the Q waveform for a D latch with the
EN and D inputs of figure below.
32
Clocked T Flip-Flop
Implementation of the T Flip-Flop.
An edge-triggered T flip-flop is easily implemented by connecting J and K
inputs together in an edge-triggered J-K flip-flop.
T
CLK
J
CP
K
Q
_
Q
R
33
Asynchronous Inputs
•Most clocked FFs also have one or more asynchronous inputs which operate
independently of the synchronous inputs and clock input.
•Asynchronous inputs can be used to override all the other inputs in order to
place the FF in one state or the other at any time.
34
Asynchronous Inputs
•Example showing how a clocked flip-flop responds to asynchronous inputs.
35
Master-Slave J-K Flip-Flop
A master-slave flip-flop contains two flip-flops/latches:
1. Master S-C latch (S-C Flip-Flop) - receives data while the input trigger clock
is HIGH.
2. Slave S-C latch (S-C Flip-Flop) - receives data from the master and output it
when the clock goes LOW.
36
Master-Slave J-K Flip-Flop – Operation of the Circuit

Two RS flip-flops are combined together using an inverter to
construct a master-slave JK flip-flop.

When the clock input Cp is 0, the output of the inverter is 1. The
slave latch is then enabled, and its output Q is equal to the master
latch output. The master latch is disabled, because Cp is 0.

When a logic-1 clock pulse is applied, the values on S and R control
the value stored in the master latch. The slave is disabled as long as
the pulse remains at the 1 level, because its Cp input is equal to 0.
Any changes in the external S and R inputs change the master
output, but cannot affect the slave output.

When the pulse returns to 0, the master is disabled and is isolated
from the S and R inputs. At the same time, the slave is enabled, and
the current value of master output is transferred to the output of the
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flip-flop (slave output).
Master-Slave J-K Flip-Flop - Truth Table
INPUTS
OUTPUT
J
K
CLK
Q
Q’
STATE
0
0
PULSE
Q0
Q’0
NO
CHANGE
0
1
PULSE
0
1
RESET
1
0
PULSE
1
0
SET
1
1
PULSE
Q’0
Q0
TOGGLE
38
Master-Slave J-K Flip-Flop – Timing Diagram
39
Note: Here NC means no change.
Master-Slave J-K Flip-Flop
Master-slave flip-flops are called pulse-triggered or level triggered devices
because input data are read during the entire time that the clock pulse is at
a HIGH level.
The master-slave flip-flops has become obsolete (examples: TTL 7473, 7476
and 74107.)
The newer IC in this series have been manufactured as edge-triggered flipflops (example: 74LS76 and 74LS107)
40
Flip-Flop Application
Edge-triggered (clocked) flip-flops can be used in a wide variety of
applications, such as data storage, transferring data from one location to
another, counting, etc.
The most common use of flip-flops is for the storage of data or information by
using groups of flip-flops called registers.
To transfer data from one location to another, we need groups of flip-flops
called shift register arranged in such a way so that the data in binary
numbers form can be stored and shifted from one flip-flop to the next for
every clock pulse.
The application of flip-flops in counting is referred to as frequency division.
By using appropriate number of flip-flops, the circuit could divide a frequency
by any power of 2.
41
Flip-Flop Synchronization
Most digital systems are synchronous in their operation.
However there will be an external signal that is not synchronized
to the clock.
Asynchronous signals often occur as a result of a human
operator’s actuating an input at random time relative to the clock
signal.
The asynchronous signals can produce unpredictable and
undesirable results.
Flip-Flop can be used to synchronize the effect of an asynchronous
input.
42
Flip-Flop Synchronization
The problem with the circuit below is that A is asynchronous; it can change
states at any time.
43
Flip-Flop Synchronization
This can produce partial clock pulses at output X, as shown in the wave forms
below.
44
Flip-Flop Synchronization
To overcome this problem, the A signal is connected to the D input of a
flip-flop, which is clocked by the NGT of the clock signal.
45
Flip-Flop Synchronization
Thus, when A goes HIGH, Q will not go HIGH until the next NGT of the
clock at time T1. This HIGH at Q will enable the AND gate to pass
subsequent complete clock pulses to X.
When A goes LOW, Q will not go LOW until the next NGT of the clock at T2.
Thus the AND gate will not inhibit clock pulses until the clock pulse that ends
at T2 has been passed through to X.
46
Astable/Monostable Multivibrators
A multivibrator is an electronic circuit used to implement a variety of
simple two-state systems such as oscillators, timers and flip-flops. It is
characterized by two amplifying devices (transistors, electron tubes or
other devices) cross-coupled by resistors and capacitors.
There are three types of multivibrator circuit:
astable, in which the circuit is not stable in either state—it continuously
oscillates from one state to the other. Due to this, it does not require a
input (Clock pulse or other).
monostable, in which one of the states is stable, but the other is not—
the circuit will flip into the unstable state for a determined period, but
will eventually return to the stable state. Such a circuit is useful for
creating a timing period of fixed duration in response to some external
event. This circuit is also known as a one shot. A common application is
in eliminating switch bounce.
bistable, in which the circuit will remain in either state indefinitely. The
circuit can be flipped from one state to the other by an external event or
trigger. Such a circuit is important as the fundamental building block of
47 a
a register or memory device. This circuit is also known as a latch or
flip-flop.
Astable/Monostable Multivibrators
48
Astable Multivibrators
Astable Multivibrator:
•An astable multivibrators is also called a free-running multivibrators.
•The astable multivibrators generates a continuous flow of pulse.
•The versatile 555 Timer IC can be used to implement an astable
multivibrators.
•The output frequency of the multivibrator can be increased by decreasing
the value of the resistors and/or capacitor.
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Astable Multivibrators
50
Monostable Multivibrators
Monostable Multivibrator:
A monostable multivibrator is also called a one-shot multivibrator.
When the one-shot is triggered, the multivibrator generates a single short
pulse.
The input trigger may be an entire pulse, a L-to-H or H-to-L trasition of the
trigger pulse.
The output pulse may be either a positive or a negative pulse.
The time duration of the output pulse can be adjusted by using different
resistor-capacitor combinations.
51
Monostable Multivibrators
555 timer IC wired as a monostable multivibrator
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Monostable Multivibrators
74121 IC wired to generate single clock pulse
53