MOTOROLA
68HC08
INTRODUCTION
AND
SYSTEM
OVERVIEW
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CONTENTS
68HC08 Micro Controller Family
Evolution
CSIC Design Philosophy
CPU08 Overview
68HC708 Architecture Overview
Module Preview
68HC08 Technical Support
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Motorola's 6800 Family Evolution
MPC600
32- &
RISC
Most
Powerful
MPC500
68020
68300
15 Versions
Hardware Compatibility
68000
68HC16
16-Bit
68HC12
12 Versions
Architecture
Software Compatibility
2 versions
68HC11
60 Versions
8-Bit
68HC08
15 Versions
6800
68HC05
180 Versions
Least
Expensive
Time
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Design Goals for 8-bit Microcontrollers
Broad product offering for tiered performance application needs
Higher performance, cost sensitive
Easy migration path for existing 68HC05 users
Ability to meet new customer requirements quickly
Low voltage capable
High quality, cost effective manufacturing capabilities
Documentation and development support
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Motorola's Solution:
The 68HC08 CPU
HC05 object code compatible
Architecturally enhanced 68HC05 CPU
5x average performance increase
CSIC's first unified design rules (UDR) core
New module based CSIC design/test methodology
CPU architecture extensibility
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System Overview MTT48 V2.1 1- 6
68HC08 Modular CSIC Solution
Clock
Generation
M odule
System
Integration
M odule
68HC08
CPU
Timer
M odule
Peripheral
M odule
Internal Bus (IBUS)
RAM
M emory
ROM Type
M emory
Peripheral
M odule
Peripheral
M odule
Modularity Requirements
• Standard internal bus definition
• Standard module heights
• Standard module definition
Reduced Die Size (Cost-effectiveness)
• Individual modules hand packed to take up less silicon
• No excessive glue logic
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Building a CSIC from a Module Library
CSIC LIBRARY
CPU
SIM
DMA ADX
EXT TIM
BUS
CPM
PLL RTC
OSC OSD
MC68HC08
68HC08
CPU
SCI
PWM
LCD
SPI
A/D
PTA PTB
PTC PTD
MEM
GEN
CPM – CUSTOMER PROPRIETARY MODULE
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68HCxx 8-BIT CPU Cores
Major Differences
HC05
HC08
HC11
Single Chip Operation
(except for 68HC05C0)
Single Chip and
Expanded Modes
Single Chip and
Expanded Modes
No Direct Control of the
Stack Pointer
Direct Control of
Stack Pointer via
PUSH/PULL Instructions
Direct Control of
Stack Pointer via
PUSH/PULL Instructions
One 8-Bit Index Register
One 16-Bit Index Register
Two 16-Bit Index Register
One 8-Bit Accumulator
One 8-Bit Accumulator
Two 8-Bit Accumulator or
One 16-Bit Accumulator
8-Bit Math with MUL
Instruction
8-Bit Math with
MUL and DIV Instructions
16-Bit Math with MUL and
DIV instructions
IDR Process
(4Mhz bus)
UDR Process
(8 Mhz bus)
IDR P Process
(4 Mhz bus)
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Let's take a closer look at the CPU
LVI
Module
COP
Module
Clock
Generation
Module
System
Integration
Module
IRQ
Module
RESET
Module
68HC08
CPU
Timer
Module
Peripheral
Module
Internal Bus (IBUS)
DMA
Module
RAM
Memory
ROM Type
Memory
Peripheral
Module
Peripheral
Module
Peripheral
Module
BREAK
Module
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68HC08 CPU Design Accomplishments
Increased Bus Speed of 8Mhz at 5V
Sub-micron UDR process
Improved Instruction Set and Addressing Modes
Opcode Look-Ahead Instruction Prefetch
Optional Modular Extensions
• DMA module reduces interrupt overhead
• Address extension module increases address bus to 24bits for > 64K data/program space
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68HC08 Instruction Preview
Data Movement
• Load, Store, Move, Stack
Arithmetic
• Add, Sub, Mul, Div
Logical
• And, Or, Eor
Data and Bit Manipulation
• Shifts, Rotates, Bit Test
Program Control
• Branch, Subroutine
Binary Coded Decimal
Looping Constructs
Special High Level Language Support
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68HC08 Addressing Preview
Inherent
Immediate
Direct
Extended
Indexed
• 8 and 16 bit offset
• Stack Pointer
• Post Increment
Relative
Memory to Memory
• Direct
• Indexed
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68HC08 Instruction/Addressing
Summary
• Stack Manipulation (48 new instructions)
– Directly push/pull any register & add immediate to stack
– Stack relative addressing mode
– Temporary variables on the stack can be manipulated directly, without loading
them into the accumulator
• Index Extension Register (7 new instructions)
– Allows use of full 16-bit index register (H:X)
• Memory to Memory Move (4 new instructions)
• Looping Constructs (12 new instructions)
– Decrement and Branch
– Compare and Branch
• Arithmetic Enhancements (1 new instruction)
– Faster multiply (5 clks vs 11)
– Divide (16/8)
• BCD Support (2 new instructions)
– Decimal adjust accumulator and nibble swap accumulator
• C Compiler Support (4 new instructions)
– Conditional branch with signed operands
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68HC08 Flagship
MC68HC708XL36
Clock
Generation
Module
System
Integration
Module
LVI
IRQ
COP
BREAK
RESET
68HC08
CPU
Timer
Interface
Module
Direct
Memory
Access
Module
Internal Bus (IBUS)
Serial
Communications
Interface
Serial
Peripheral
Interface
Random
Access
Memory
Electronically
Programmable
ROM
Monitor
ROM
Architecturally Enhanced 8-bit CPU
1Kbyte RAM and 36Kbytes EPROM
240 Bytes Monitor ROM
System Control and Protection Modules (SIM)
Direct Memory Access Module (DMA)
General Purpose Timing Interface Module (TIM)
Serial Communication Modules (SCI and SPI)
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CPU SYSTEM MODULES
³
Low Voltage Inhibit (LVI)
³
Computer Operating Properly (COP)
³
Break Module
³
External Interrupt Module (IRQ)
³
System Integration Module (SIM)
• Manages System Protection
– Reset on illegal address and illegal opcode
– Optional reset on LVI and COP
• Manages Interrupts with up to 128 separate vectors
• Bus Clock Generation for CPU and most Peripherals
CLOCK GENERATION MODULE(CGM)
³
Provides clock inputs into SIM Module and SCI Baud Generator
³
Crystal Oscillator circuit and phase locked loop circuit
• Avoids the cost and noise of high frequency crystals
³
Programmable bus frequency
• Integer multiples (1 to 15) of crystal frequency ÷ 4
TIMING INTERFACE MODULE (TIM)
³
Modular architecture
³
68HC05C4 timer compatible channels
• Input capture, Output Compare, PWM
³
Counter may be free-running or modulo up-counter
•
³
Motorola
Optionally toggle any channel output on overflow
Timer interrupts can select CPU or DMA servicing
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DIRECT MEMORY ACCESS (DMA)
³
DMA can be used to reduce CPU overhead of processing normal data movement
interrupts
³
Using DMA to service peripherals instead of CPU interrupts can dramatically
reduce interrupt overhead
•
A byte transfer takes only two clocks (4 MByte/sec peak)
•
CPU processing continues after the DMA transfer as if nothing happened
³
Allows transfers between any two CPU addressable locations
³
Expandable architecture up to seven channels
³
Block transfer capability of up to 256 bytes
³
Programmable bus bandwidth utilization of 25% to 100%
³
Optional CPU interrupt upon completion data block transfer
³
Optional enable for DMA operation during low power wait
SERIAL PERIPHERAL INTERFACE (SPI)
³
Motorola
Compatible with HC05 SPI but with enhancements:
•
Separate receive and transmit buffers avoid write collisions
•
Programmable wired-or mode
•
DMA can service normal data movement SPI interrupts
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SERIAL COMMUNICATIONS INTERFACE (SCI)
³
Compatible with HC05 SCI but with enhancements:
•
Optional HW parity
•
Two idle line receiver wakeup methods
•
Additional interrupt vectors and interrupt enables
•
Loop mode for diagnostics/test
•
DMA can service normal data movement SCI interrupts
MEMORY MODULES
³
1 KByte fully static 8-bit RAM
³
36 KBytes of 8-bit user-programmable ROM
• Windowed packages available for UV erasure
• One-time programmable non-windowed packages
• EPROM security mode
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New Module Development
Modules currently in design or targeted2, 6, & 8 Channel Programmable
Timers
•
•
•
•
•
•
•
•
•
•
•
•
•
Dedicated 8-bit & 16-bit Pulse Width Modulation
Analog/Digital Converter (8-bit and 10-bit)
External Bus Interface
Address Extension
Comparators
RAM
EPROM
ROM
EEPROM
I2C
LCD
Customer Specific
OSD - On Screen Display
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68HC08 Summary
Architecture is an extension of the world's leading 8-bit microcontroller
family - 68HC05
Offers a high performance, cost-effective migration for existing HC05
applications
Modular design and test methodology gives Motorola ability to meet
customer new product requirements with dramatically lower cycle time
Supported by a portfolio of development tools to program, evaluate and
design applications
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