EE2301: Basic Electronic Circuit
Recap in last lecture
EE2301: Block B Unit 2
1
p-n Junction
The pn junction forms the basis of the semiconductor diode
Within the depletion region, no free carriers exist since the holes and
electrons at the interface between the p-type and n-type recombine.
EE2301: Block C Unit 1
2
Diode Symbol and Operation
Forward-biased
Current (Large)
Reverse-biased
Current (~Zero)
iD
+
-
-
+
Forward Biased:
Reverse Biased:
Diode conducts
Little or no current
EE2301: Block C Unit 1
3
Ideal diode model
Circuit containing
ideal diode
EE2301: Block C Unit 1
Circuit assuming that the
ideal diode conducts
Circuit assuming
that the ideal diode
does not conduct
4
Rectification: from AC to DC
One common application of diodes is rectification. In rectification,
an AC sinusoidal source is converted to a unidirectional output
which is further filtered and regulated to give a steady DC output.
Supply is AC
EE2301: Block C Unit 1
DC required
5
Rectifier with regulator diagram
Rectifier
Bi-directional
input
Unidirectional
Filter
Regulator
Steady DC output
output
We will look at two types of rectifiers and apply the large
signal models in our analysis:
1) Half wave rectifier
2) Full wave rectifier
EE2301: Block C Unit 1
6
EE2301: Basic Electronic Circuit
Starting from this lecture
EE2301: Block B Unit 2
7
The Transistor


A transistor is a 3-terminal semiconductor device (cf
Diode is a 2-terminal device)
Performs 2 main functions fundamental to electronic
circuits:
1) Amplification – magnifying a signal
2) Switching – controlling a large current or voltage across 2
terminals (on/off)

2 major families of transistors:
1) Field Effect Transistors (FETs) – Unit 2
2) Bipolar Junction Transistors (BJTs) – Unit 3
Unit 8
8
Transistors as Switches (1)
Controlling I or V
Controlling I or V
I or V applied at 3rd terminal switches the device on/off
Unit 8
9
Transistors as Amplifiers (1)
Controlling I or V
vin
vout
Gain is determined by I or V applied at 3rd terminal
Unit 8
10
Unit 8
11
Block C - Unit 2 Outline
 MOSFET operation
> Construction of the MOSFET
> Basic working principle of the MOSFET
> Operating modes of the MOSFET
 MOSFET amplifiers (In this course, the focus
will be on their use in amplifier circuits)
> Biasing the MOSFET
> Small signal equivalent circuit
EE2301: Block C Unit 2
12
Transistors as Amplifiers
BJT
Unit 3
Unit 2
FET
Whereas a diode is a 2 terminal device, transistors in contrast have 3 terminals. In a
diode, the current is controlled by the voltage across the diode. For transistors, the
current through the device is controlled by the voltage across the device as well as
the voltage or current applied to a 3rd port.
EE2301: Block C Unit 2
13
Classification of FETs
FET: Field Effect Transistor
MOSFET: Metal Oxide
Semiconductor FET
JFET: Junction FET
EE2301: Block C Unit 2
14
Enhancement mode MOS
For NMOS, the source and drain are n-type, while the bulk substrate is p-type.
Gate
Source
Drain
n+
n+
p
Bulk (substrate)
D
Metal
Oxide
Semiconductor
G
S
The above figure shows an n-channel enhancement mode MOS (also known as
NMOS) with its respective symbol. It contains three terminals: Source (S), Gate
(G) and Drain (D). When in operation, the current flows between the source and
drain. The carriers move in the direction from the source to the drain. This current
is controlled by the voltage applied to the gate. In the symbol, the arrow points
towards the gate for n-channel MOS.
EE2301: Block C Unit 2
15
Enhancement NMOS Operation
G
S
n+
D
p
ID: Channel current
Bulk (substrate)
n+
D
VGD
ID
+
G
+VGS-
S
Amount of current in the channel is controlled by the
voltage applied at the terminals (VGS and VGD)
Device is “switched on” (formation of a conducting
channel) by the voltage on the Gate
EE2301: Block C Unit 2
16
Gate Current
G
S
IG=0
D
D
Gate
Oxide
n+
p
Bulk (substrate)
n+
Substrate
G
IG=0
S
Gate current sees a capacitor formed by the gate, oxide
(which is insulating), and substrate (conducting)
EE2301: Block C Unit 2
17
NMOS is normally off
G
S
Reverse-biased
D
S
n+
p
n+
+
_
VDD
VDD
D
Bulk (substrate)
When VGS = 0V, ID = 0A
When no voltage is applied to the gate, the enhancement mode NMOS
will not conduct between S and D (even for a voltage applied across S
and D). This is because, as we can see from the figure on the right:
 Drain-Bulk n+p junction is strongly reverse-biased
 Source-Bulk n+p junction is also reverse-biased
 No undisrupted conductive path between source and drain: no current
EE2301: Block C Unit 2
18
Conducting channel in NMOS
G
S
n+
p
Bulk (substrate)
D
n+
iD
+
- VGG
D
VDD
+
VDD
-
G
VGG
A key point on MOS devices is that for the device
to conduct (or turn on), there must be a conducting
channel between the source and drain. For NMOS,
this channel must be n-type. For this n-channel to
form, VGS must be larger than VT, which is known
as the threshold voltage. The value of VT depends
on the design and properties of the device.
EE2301: Block C Unit 2
+
_
+
_
S
For conduction to
occur, VGS > VT
19
Formation of channel in NMOS
VGG (+ve)
++++++++++++
______________
p-type substrate
Initially when VGS < VT:
 The majority carriers in p-type silicon are
holes (positively charged)
 Holes are repelled away from the surface at
the silicon-oxide interface
 The interface becomes depleted of majority
carriers
 No conduction occurs between S and D
When VGS > VT:
 The minority carriers in p-type silicon are electrons (negatively charged)
 Electrons are attracted towards the surface at the silicon-oxide interface
 A narrow conducting n-type channel near this surface forms
 Electrons from the source can now flow towards the drain resulting in a a
drain current ID
 Increasing VGS (while keeping VDS fixed) increases the concentration of
carriers, thereby increasing conduction
EE2301: Block C Unit 2
20
p-Channel MOS (PMOS)
p
The PMOS operates on the same principle as the NMOS only that the charge carrier
types are reversed. As a consequence of this swap:
(1) It is p-type conducting channel that is formed in an n-type bulk
(2) It requires a negative threshold voltage in order to form the channel
EE2301: Block C Unit 2
21
Enhancement vs Depletion mode
Enhancement mode
Only when VGS is greater than VT will a conducting channel form at
the surface of the bulk as free charge carriers are created, otherwise
device remains off. As such, we say the device is normally off.
Depletion mode
In contrast, depletion mode MOS devices are designed with a built-in
conducting channel. Hence even with no gate voltage, the MOS will
still conduct between source and drain. The device is turned off by
applying a gate voltage so as to deplete this channel.
In this course we will focus on the enhancement mode MOS, which we shall see has
three regions of operation unlike the diode which has only 2 (either on or off).
EE2301: Block C Unit 2
22
EE2301: Basic Electronic Circuit
Different Operation Regions
of a MOSFET Device
Con’t in next lecture
EE2301: Block B Unit 2
23
Cutoff mode
The first mode we shall consider is when the device is off. This
is known as Cutoff. As previously pointed out, this occurs when
the threshold voltage has not been reached.
Cutoff Region
VGS < VT , VGD < VT
As a result of this,
ID = 0A
D
ID
G
S
Cutoff Region
 VGS and VGD both less than VT
 Channel is off at both source and drain
 No conduction and no current flow between S & D
EE2301: Block C Unit 2
24
Triode mode
As mentioned previously, when the gate voltage exceeds the threshold
the MOS can conduct and therefore turns on. When it turns on, it can
operate in one of two possible regions. One of these 2 modes is known
as the triode or ohmic region.
Triode/Ohmic Region
VGS > VT, VGD > VT
The drain current is given by:
ID = K [2(VGS – VT)VDS – VDS2]
ID
G
W  Cox 


L
2
 

K is known as the conductance parameter, and is defined as: K  
Triode/Ohmic Region
 Both VGS and VGD are greater than VT
 Channel is on at source and also on at drain
 Current is dependent of both VDS and VGS
EE2301: Block C Unit 2
D
S
W: channel width
L: channel length
µ: mobility of carriers
Cox: Oxide capacitance
25
MOS in Triode mode
G
Near both the drain and source:
S
D
VGD > VT
VGS > VT
n+
Voltage difference > VT
p
n+
Conducting channel is formed
on both sides
+
_
VDD
Bulk (substrate)
In fact everywhere under the gate
oxide is larger than VT so there is
a continuous channel between the
drain and source.
Increasing VGS thus increases the number of carriers, resulting in a larger drain
current
Increase VDS increases the voltage drop across the channel, resulting in a larger
drain current
ID is dependent therefore on both VDS and VGS (Refer to equation on previous slide)
EE2301: Block C Unit 2
26
Saturation mode
While the MOS is still on, if we continue to increase VDS without increasing VGS,
there will come a point when the voltage near the drain becomes less than the
threshold (VGD < VT). This is known as the saturation region.
Saturation Region
VGS > VT, VGD < VT
The drain current is given by:
iD = K (VGS – VT)2
-
D
VGD
G
ID
+
Saturation Region
+VGS VGS > VT and VGD < VT
S
 Channel is on at source but off at drain
 Current is nearly independent of VDS, depending only on VGS
 One might expect the MOS to operate like in cutoff under these bias
conditions but it does not.
EE2301: Block C Unit 2
27
NMOS in Saturation
G
S
n+
p
Bulk (substrate)
D
n+
+
- VGG
+
VDD
-
The channel in saturation mode is
typically represented as tapered or
wedged (as shown in the figure).
Large currents still conduct via the
channel due to the large voltage drop
across drain and source, but changes
little with increasing VDS.
Pinch-off (going from triode to saturation)
The channel near the drain begins for fall below the threshold condition when
VGD = VT
In terms of the drain-source voltage, this corresponds to:
VDS(pinch-off) = VGS - VT
EE2301: Block C Unit 2
28
Summary of operating modes
 Cut-Off:
VGS < VT, VGD <VT
 Linear/Triode/Ohmic:
VGS > VT, VGD> VT
 Saturation:
VGS > VT, VGD < VT
For n-channel
enhancement MOS
EE2301: Block C Unit 2
29
Operating Regions
When
VGS - VT = VDS
ID = K VDS2
SATURATION
CUTOFF
EE2301: Block C Unit 2
30
Operating state example
Determine the operating state of the MOSFET shown in the circuit for the given values of
VDD and VGG if the ammeter and voltmeter shown read the following values:
a. VGG = 1V; VDD = 10V; ID = 0mA; RD = 100Ω
b. VGG = 4V; VDD = 10V; ID = 72mA; RD = 100Ω
c. VGG = 6V; VDD = 10V; ID = 270mA; RD = 26Ω
For the MOSFET in the circuit, VT = 2V; K = 18mA/V2
a. Drain current is zero, which implies that the MOS
is in the cutoff state. We should also check that VGS
and VGD are both less than VT.
VGS = 1V
VGD = - 9V
EE2301: Block C Unit 2
31
Operating state example
b. VGS = 4V (hence larger than VT); we now still need to find VGD to decide
whether the MOS is in the triode or saturation region.
VDS = VDD – IDRD = 2.8V
VGD = VGS – VDS = 1.2V (less than VT)
MOS is in saturation
c. VGS = 6V (hence larger than VT); we now still need to find VGD to decide
whether the MOS is in the triode or saturation region.
VDS = VDD – IDRD = 3V
VGD = VGS – VDS = 3V (larger than VT)
MOS is in the ohmic region
EE2301: Block C Unit 2
32
MOSFET Q-point
As mentioned at the start, in this course our focus is on the use of transistors for
amplifiers. A key takeaway to remember is that when building an amplifier, we
use the saturation region. Why this is so will become clear in the next few slides.
For this to be realized, the MOS amplifier circuit has to be designed to ensure
the MOS is working at the operating point (which corresponds to a fixed value
of ID, VGS and VDS). This is called the Q-point. We say that the circuit needs
to be properly biased to give us the desired Q-point.
EE2301: Block C Unit 2
33
Determining Q-point (Graphical)
The I-V characteristic of the MOS describes the full range of values that the MOS can take.
However, the MOS works only at one value of ID, VDS and VGS when put in a circuit. It is
the circuit that imposes this constraint on the MOS. Hence to find the Q-point we also need
to consider the characteristics of the circuit as well: this is defined by the load line.
Given: VGG = 2.4V; VDD = 10V; RD = 100Ω
The Q-point is found at the intersection
of the load line and the I-V curve.
Load line: Apply KVL around the right side mesh,
VDD = VDS + IDRD
Since we want to draw this on the I-V curve, we should express this as ID against VDS:
ID = VDD/RD – VDS/RD
EE2301: Block C Unit 2
34
MOSFET amplifiers
But how do we achieve the function of an amplifier from the concept of the Q-point? We
can see this graphically.
Initially, VGS = 2.4V, while ID = 52mA and VDS = 4.75V
Now if VGS was dropped slightly by 0.2V, then VDS ≈ 6.4V (+1.65V)
Now if VGS was instead increased from 2.4V by 0.2V, VDS 2.8V (-1.95V)
VGG forms the input and VD is the output
We see that for a peak to peak change in the input by 0.4V, we see a peak to peak
change in the output by 3.6V  Output is amplified!
EE2301: Block C Unit 2
35
Find Q-point by calculation
We have seen how to determine the Q-point of the MOS graphically. This example shows
how we can do the same but now using calculation.
Given: VGG = 2.4V; VDD = 10V; RD = 100Ω; VT = 1.4V; K = 52mA/V2
Since the source is connected to ground, it becomes obvious that VGS = 2.4V
Now we still need to find VDS and ID (2 equations). To do so we can apply KVL around
the right-hand mesh. To get another equation, we use the formula to find ID when MOS
is in saturation (this is a lot simpler than that for triode state).
Applying KVL to right-hand mesh:
VDD = VDS + IDRD 10 = VDS + 0.1*ID
Next, we use the drain current formula for saturation mode:
ID = K(VGS – VT)2 ID = 52*(2.4 – 1.4)2 = 52mA
From this, we can then find VDS VDS = 4.8V
Is it saturation? Check: VGD = -2.4V (less than VT) YES!!
EE2301: Block C Unit 2
36
EE2301: Basic Electronic Circuit
Recap in last lecture
EE2301: Block B Unit 2
37
Summary of operating modes
 Cut-Off:
VGS < VT, VGD <VT
 Linear/Triode/Ohmic:
VGS > VT, VGD> VT
 Saturation:
VGS > VT, VGD < VT
For n-channel
enhancement MOS
EE2301: Block C Unit 2
38
Operating Regions
SATURATION
CUTOFF
EE2301: Block C Unit 2
39
Biasing aMOSFET (Q-point)
A change in VGS is AMPLIFIED
by 9 times in VDS!!
VGS=2.2V, VDS=2.8V
VGS=2.4V, VDS=4.75V
Vpp =0.4V
VGS=2.6V, VDS=6.4V
Vpp = 3.6V
EE2301: Block C Unit 2
40
EE2301: Basic Electronic Circuit
Let’s con’t
EE2301: Block B Unit 2
41
Self-biasing MOS amplifier
The previous circuit requires a voltage source to bias the gate. One disadvantage is
this takes up space. The self-biasing MOS amplifier takes care of this problem.
Determine VGS, VDS, and ID for the following MOS amplifier, given that:
R1 = R2 = 1MΩ; RD = 6kΩ; RS = 6kΩ; VDD = 10V; VT = 1V; K = 0.5mA/V2
Begin by first finding the gate voltage:
R2
VG 
VDD  5V
R1  R2
Next we assume the MOS is in saturation and then check to
see if this assumption (VGS>VT and VGD<VT) is correct
(formula for saturation is a lot simpler than for triode state,
thus easier to work with):
ID = K(VGS – VT)2 ; where VGS = VG - IDRS
ID = 0.5(5 – 6ID – 1)2
18ID2 -25ID + 8 = 0  ID = 0.89mA or 0.5mA
EE2301: Block C Unit 2
42
Self-biasing MOS amplifier
Only one of these solutions is valid for our case: thus we need to check each one in turn to
see which of these makes physical sense.
But what do we use ID to check for? A hint is that we still have not found the value of VDS
up till this point. We have assumed that it is a value that corresponds to the saturation
mode. We can substitute ID into the right-hand mesh to find VDS since we can see that:
VDD = VDS + ID(RD + RS)
First we try ID = 0.89mA:
VDS = 10 – 0.89*12 = -0.68V (REJECTED: VDS should be positive)
Now we try ID = 0.5mA:
VDS = 10 – 0.5*12 = 4V (ACCEPTED: this makes sense)
Finally, now that we know VDS, we can then use this information to verify if our starting
assumption (that the MOS is in saturation) was true. To do this, we find VGD:
VGD = VG – (VDS + IDRS) = 5 – (4 + 0.5*6) = -2V <VT ;
VGS = VG-IDRS = 5 – (0.5*6) = 2V > VT
This indicates the MOS is in saturation, thereby confirming our starting assumption.
EE2301: Block C Unit 2
43
Example (Prob 11.9)
The NMOS transistor shown in figure has VT=1.5V and
K=0.4mA/V2. If VG is a pulse with 0 to 5V, find the voltage
levels of the pulse signal at the drain output. Assume the NMOS
is in saturation region when VG=5V
Since VT = 1.5 V, with vG = 0 V, vGS <
VT, the transistor is cut off. Therefore,
vD = 5 V.
When vG = 5 V, and assuming that the
transistor is in the saturation region:
iD = k (vGS - VT)2 = 0.4 (5 - 1.5)2 = 4.9
mA. Therefore, vD = 5 - 4.9´1 = 0.1 V.
EE2301: Block C Unit 2
44
Small signal equivalent circuit
 The MOS is inherently a non-linear device (basic circuit
theory is based on linear problems)
 Within a small range, we see from the I-V characteristic that
we can approximate its behavior as linear
 This allows us to analyze a MOS amplifier using the I-V graph
 We can instead define the linear characteristics of the MOS for
a given Q-point
 We can do so using a small signal equivalent circuit
 Now we can analyze the MOS using the linear circuit theory
we have learnt so far
EE2301: Block C Unit 2
45
Small signal equivalent circuit
 Linearizes the characteristics of a MOSFET (which is otherwise
nonlinear) for a given operating point
 Only valid for a particular operating point
 Only valid for small varying signals
rd
VDS
rd 
I D
VGS
I D
, gm 
VGS
VDS
id = gmvgs + vds/ro
Mathematics will not
covered in this course
EE2301: Block C Unit 2
46
EE2301: Basic Electronic Circuit
End of Block C Unit 2
EE2301: Block B Unit 2
47