Lecture 10: Circuit Families Outline Pseudo-nMOS Logic Dynamic Logic Pass Transistor Logic 10: Circuit Families CMOS VLSI Design 4th Ed. 2 Introduction What makes a circuit fast? – I = C dV/dt -> tpd (C/I) DV – low capacitance – high current 4 B – small swing 4 A Logical effort is proportional to C/I 1 1 pMOS are the enemy! – High capacitance for a given current Can we take the pMOS capacitance off the input? Various circuit families try to do this… 10: Circuit Families CMOS VLSI Design 4th Ed. Y 3 Pseudo-nMOS In the old days, nMOS processes had no pMOS – Instead, use pull-up transistor that is always ON In CMOS, use a pMOS that is always ON – Ratio issue – Make pMOS about ¼ effective strength of pulldown network 1.8 1.5 load P/2 1.2 P = 24 Ids Vout 0.9 Vout 16/2 Vin 0.6 P = 14 0.3 P=4 0 0 0.3 0.6 0.9 1.2 1.5 1.8 Vin 10: Circuit Families CMOS VLSI Design 4th Ed. 4 Pseudo-nMOS Gates Design for unit current on output to compare with unit inverter. pMOS fights nMOS Y inputs f Inverter Y A NAND2 gu gd gavg pu pd pavg = = = = = = 10: Circuit Families A B gu g Y gd avg pu pd pavg NOR2 = = = = = = A CMOS VLSI Design 4th Ed. B gu gd gavg Y pu pd pavg = = = = = = 5 Pseudo-nMOS Gates Design for unit current on output to compare with unit inverter. pMOS fights nMOS Y inputs f Inverter 2/3 Y A 4/3 NAND2 gu gd gavg pu pd pavg = 4/3 = 4/9 = 8/9 = 6/3 = 6/9 = 12/9 10: Circuit Families gu g Y gd avg 8/3 pu pd 8/3 pavg 2/3 A B NOR2 = 8/3 = 8/9 = 16/9 = 10/3 = 10/9 = 20/9 2/3 A CMOS VLSI Design 4th Ed. 4/3 B gu gd gavg Y pu 4/3 pd pavg = 4/3 = 4/9 = 8/9 = 10/3 = 10/9 = 20/9 6 Pseudo-nMOS Design Ex: Design a k-input AND gate using pseudo-nMOS. Estimate the delay driving a fanout of H Pseudo-nMOS G = 1 * 8/9 = 8/9 F = GBH = 8H/9 P = 1 + (4+8k)/9 = (8k+13)/9 N=2 4 2 H 8k 13 1/N D = NF + P = 3 9 10: Circuit Families In1 1 Ink 1 CMOS VLSI Design 4th Ed. Y H 7 Pseudo-nMOS Power Pseudo-nMOS draws power whenever Y = 0 – Called static power P = IDDVDD – A few mA / gate * 1M gates would be a problem – Explains why nMOS went extinct Use pseudo-nMOS sparingly for wide NORs Turn off pMOS when not in use en Y A 10: Circuit Families B C CMOS VLSI Design 4th Ed. 8 Ratio Example The chip contains a 32 word x 48 bit ROM – Uses pseudo-nMOS decoder and bitline pullups – On average, one wordline and 24 bitlines are high Find static power drawn by the ROM – Ion-p = 36 mA, VDD = 1.0 V Solution: Ppull-up VDD I pull-up 36 μW Pstatic (31 24) Ppull-up 1.98 mW 10: Circuit Families CMOS VLSI Design 4th Ed. 9 Dynamic Logic Dynamic gates uses a clocked pMOS pullup Two modes: precharge and evaluate 2 A 2/3 Y 1 Y 1 A Static 4/3 Pseudo-nMOS Precharge Y A 1 Dynamic Evaluate Precharge Y 10: Circuit Families CMOS VLSI Design 4th Ed. 10 The Foot What if pulldown network is ON during precharge? Use series evaluation transistor to prevent fight. precharge transistor Y Y inputs A Y inputs f f foot footed 10: Circuit Families CMOS VLSI Design 4th Ed. unfooted 11 Logical Effort Inverter unfooted NAND2 1 gd pd footed 2 2 10: Circuit Families 2 B 2 gd pd = 2/3 = 3/3 1 1 B Y gd pd = 2/3 = 3/3 A 1 gd pd = 1/3 = 3/3 1 Y 1 Y A A = 1/3 = 2/3 1 Y 1 Y A NOR2 A 3 B 3 3 1 Y gd pd = 3/3 = 4/3 CMOS VLSI Design 4th Ed. A 2 B 2 2 gd pd = 2/3 = 5/3 12 Monotonicity Dynamic gates require monotonically rising inputs during evaluation – 0 -> 0 A – 0 -> 1 – 1 -> 1 violates monotonicity – But not 1 -> 0 during evaluation A Precharge Evaluate Precharge Y Output should rise but does not 10: Circuit Families CMOS VLSI Design 4th Ed. 13 Monotonicity Woes But dynamic gates produce monotonically falling outputs during evaluation Illegal for one dynamic gate to drive another! A=1 A Y Precharge Evaluate Precharge X X X monotonically falls during evaluation Y Y should rise but cannot 10: Circuit Families CMOS VLSI Design 4th Ed. 14 Domino Gates Follow dynamic stage with inverting static gate – Dynamic / static pair is called domino gate – Produces monotonic outputs Precharge Evaluate Precharge domino AND W W X Y Z X A B C Y Z dynamic static NAND inverter A B 10: Circuit Families W X H C CMOS VLSI Design 4th Ed. Y H Z = A B X Z C 15 Domino Optimizations Each domino gate triggers next one, like a string of dominos toppling over Gates evaluate sequentially but precharge in parallel Thus evaluation is more critical than precharge HI-skewed static stages can perform logic S0 S1 S2 S3 D0 D1 D2 D3 H Y 10: Circuit Families S4 S5 S6 S7 D4 D5 D6 D7 CMOS VLSI Design 4th Ed. 16 Dual-Rail Domino Domino only performs noninverting functions: – AND, OR but not NAND, NOR, or XOR Dual-rail domino solves this problem – Takes true and complementary inputs – Produces true and complementary outputs sig_h sig_l Meaning 0 0 Precharged 0 1 ‘0’ 1 0 ‘1’ 1 1 invalid 10: Circuit Families Y_l inputs f Y_h f CMOS VLSI Design 4th Ed. 17 Example: AND/NAND Given A_h, A_l, B_h, B_l Compute Y_h = AB, Y_l = AB Pulldown networks are conduction complements Y_l A_h = A*B A_l B_l Y_h = A*B B_h 10: Circuit Families CMOS VLSI Design 4th Ed. 18 Example: XOR/XNOR Sometimes possible to share transistors Y_l = A xnor B A_h Y_h A_l A_l B_l B_h A_h = A xor B 10: Circuit Families CMOS VLSI Design 4th Ed. 19 Leakage Dynamic node floats high during evaluation – Transistors are leaky (IOFF 0) – Dynamic value will leak away over time – Formerly miliseconds, now nanoseconds Use keeper to hold dynamic node – Must be weak enough not to fight evaluation weak keeper A 1 k X H Y 2 2 10: Circuit Families CMOS VLSI Design 4th Ed. 20 Charge Sharing Dynamic gates suffer from charge sharing A Y CY x A Y B=0 Cx Charge sharing noise x CY Vx VY VDD Cx CY 10: Circuit Families CMOS VLSI Design 4th Ed. 21 Secondary Precharge Solution: add secondary precharge transistors – Typically need to precharge every other node Big load capacitance CY helps as well Y A secondary precharge transistor x B 10: Circuit Families CMOS VLSI Design 4th Ed. 22 Noise Sensitivity Dynamic gates are very sensitive to noise – Inputs: VIH Vtn – Outputs: floating output susceptible noise Noise sources – Capacitive crosstalk – Charge sharing – Power supply noise – Feedthrough noise – And more! 10: Circuit Families CMOS VLSI Design 4th Ed. 23 Power Domino gates have high activity factors – Output evaluates and precharges • If output probability = 0.5, a = 0.5 – Output rises and falls on half the cycles – Clocked transistors have a = 1 Leads to very high power consumption 10: Circuit Families CMOS VLSI Design 4th Ed. 24 Domino Summary Domino logic is attractive for high-speed circuits – 1.3 – 2x faster than static CMOS – But many challenges: • Monotonicity, leakage, charge sharing, noise Widely used in high-performance microprocessors in 1990s when speed was king Largely displaced by static CMOS now that power is the limiter Still used in memories for area efficiency 10: Circuit Families CMOS VLSI Design 4th Ed. 25 Pass Transistor Circuits Use pass transistors like switches to do logic Inputs drive diffusion terminals as well as gates CMOS + Transmission Gates: – 2-input multiplexer – Gates should be restoring S S A A S S Y Y B B S 10: Circuit Families S CMOS VLSI Design 4th Ed. 26 LEAP LEAn integration with Pass transistors Get rid of pMOS transistors – Use weak pMOS feedback to pull fully high – Ratio constraint S A S L Y B 10: Circuit Families CMOS VLSI Design 4th Ed. 27 CPL Complementary Pass-transistor Logic – Dual-rail form of pass transistor logic – Avoids need for ratioed feedback – Optional cross-coupling for rail-to-rail swing S A S L Y L Y B S A S B 10: Circuit Families CMOS VLSI Design 4th Ed. 28 Pass Transistor Summary Researchers investigated pass transistor logic for general purpose applications in the 1990’s – Benefits over static CMOS were small or negative – No longer generally used However, pass transistors still have a niche in special circuits such as memories where they offer small size and the threshold drops can be managed 10: Circuit Families CMOS VLSI Design 4th Ed. 29