Lecture 10:
Circuit
Families
Outline
 Pseudo-nMOS Logic (Ratioed Logic)
 Dynamic Logic
 Pass Transistor Logic
10: Circuit Families
CMOS VLSI Design 4th Ed.
2
Introduction
 What makes a circuit fast?
– I = C dV/dt -> tpd  (C/I) DV
– low capacitance
– high current
4
B
– small swing
4
A
 Logical effort is proportional to C/I
1
1
 pMOS are the enemy!
– High capacitance for a given current
 Can we take the pMOS capacitance off the input?
 Various circuit families try to do this…
10: Circuit Families
CMOS VLSI Design 4th Ed.
Y
3
Ratioed Logic
VDD
Resistive
Load
VDD
Depletion
Load
RL
PDN
VSS
(a) resistive load
PMOS
Load
VSS
VT < 0
F
In1
In2
In3
VDD
F
In1
In2
In3
PDN
VSS
(b) depletion load NMOS
F
In1
In2
In3
PDN
VSS
(c) pseudo-NMOS
Goal: to reduce the number of devices over complementary CMOS
4
CMOS VLSI Design 4th Ed.
Ratioed Logic
VDD
• N transistors + Load
Resistive
Load
• VOH = V DD
RL
• VOL =
RPN + RL
F
In1
In2
In3
• Assymetrical response
PDN
• Static power consumption
VSS
5
RPN
• tpL= 0.69 RLCL
CMOS VLSI Design 4th Ed.
Active Loads
VDD
Depletion
Load
VDD
PMOS
Load
VT < 0
VSS
F
In1
In2
In3
PDN
F
In1
In2
In3
PDN
VSS
depletion load NMOS
6
VSS
pseudo-NMOS
CMOS VLSI Design 4th Ed.
Pseudo-nMOS
 In the old days, nMOS processes had no pMOS
– Instead, use pull-up transistor that is always ON
 In CMOS, use a pMOS that is always ON
– Ratio issue
– Make pMOS about ¼ effective strength of
pulldown network
1.8
1.5
load
P/2
1.2
P = 24
Ids
Vout 0.9
Vout
16/2
Vin
0.6
P = 14
0.3
P=4
0
0
0.3
0.6
0.9
1.2
1.5
1.8
Vin
10: Circuit Families
CMOS VLSI Design 4th Ed.
7
Pseudo-nMOS
10: Circuit Families
CMOS VLSI Design 4th Ed.
8
Pseudo-NMOS VTC
10: Circuit Families
CMOS VLSI Design 4th Ed.
9
Pseudo-nMOS Design
Size of PMOS
VOL
Static Power
Dissipation
tpLH
4
0.693 V
564 mW
14 ps
2
0.273 V
298 mW
56 ps
1
0.133 V
160 mW
123 ps
0.5
0.064 V
80 mW
268 ps
0.25
0.031 V
41 mW
569 ps
10: Circuit Families
CMOS VLSI Design 4th Ed.
10
Pseudo-nMOS Gates
 Design for unit current on output
to compare with unit inverter.
 pMOS fights nMOS
 Iout = 4I/3 – I/3
Inverter
Y
A
Y
inputs
f
NAND2
gu
gd
gavg
pu
pd
pavg
=
=
=
=
=
=
10: Circuit Families
A
B
gu
g
Y gd
avg
pu
pd
pavg
NOR2
=
=
=
=
=
=
A
CMOS VLSI Design 4th Ed.
B
gu
gd
gavg
Y pu
pd
pavg
=
=
=
=
=
=
11
Pseudo-nMOS Gates
 Design for unit current on output
to compare with unit inverter.
 pMOS fights nMOS
Y
inputs
f
Inverter
2/3
Y
A
4/3
NAND2
gu
gd
gavg
pu
pd
pavg
= 4/3
= 4/9
= 8/9
= 6/3
= 6/9
= 12/9
10: Circuit Families
gu
g
Y gd
avg
8/3
pu
pd
8/3
pavg
2/3
A
B
NOR2
= 8/3
= 8/9
= 16/9
= 10/3
= 10/9
= 20/9
2/3
A
CMOS VLSI Design 4th Ed.
4/3 B
gu
gd
gavg
Y pu
4/3 pd
pavg
= 4/3
= 4/9
= 8/9
= 10/3
= 10/9
= 20/9
12
Pseudo-nMOS Design
 Ex: Design a k-input AND gate using pseudo-nMOS.
Estimate the delay driving a fanout of H
Pseudo-nMOS





G = 1 * 8/9 = 8/9
F = GBH = 8H/9
P = 1 + (4+8k)/9 = (8k+13)/9
N=2
4 2 H 8k  13
1/N
D = NF + P = 3  9
10: Circuit Families
In1
1
Ink
1
CMOS VLSI Design 4th Ed.
Y
H
13
Pseudo-nMOS Power
 Pseudo-nMOS draws power whenever Y = 0
– Called static power P = IDDVDD
– A few mA / gate * 1M gates would be a problem
– Explains why nMOS went extinct
 Use pseudo-nMOS sparingly for wide NORs
 Turn off pMOS when not in use
en
Y
A
10: Circuit Families
B
C
CMOS VLSI Design 4th Ed.
14
Ratio Example
 The chip contains a 32 word x 48 bit ROM
– Uses pseudo-nMOS decoder and bitline pullups
– On average, one wordline and 24 bitlines are high
 Find static power drawn by the ROM
– Ion-p = 36 mA, VDD = 1.0 V
 Solution:
Ppull-up  VDD I pull-up  36 μW
Pstatic  (31  24) Ppull-up  1.98 mW
10: Circuit Families
CMOS VLSI Design 4th Ed.
15
Pseudo-NMOS Design
 Pseudo-nMOS gates will not operate correctly if
VOL>VIL of the driven gate.
 This is most likely in the SF corner.
 Conservative design requires extra weak pMOS.
 Another choice is to use replica biasing.
 Idea comes from analog design.
 Replica biasing allows 1/3 the current ratio rather
than the conservative ¼ ratio of earlier.
10: Circuit Families
CMOS VLSI Design 4th Ed.
16
Replica Biasing
10: Circuit Families
CMOS VLSI Design 4th Ed.
17
Ganged CMOS
10: Circuit Families
CMOS VLSI Design 4th Ed.
18
Ganged CMOS
A
B
N1
P1
N2
P2
Y
0
0
OFF
ON
OFF
ON
1
0
1
OFF
ON
ON
OFF
~0
1
0
ON
OFF
OFF
ON
~0
1
1
ON
OFF
ON
OFF
0
10: Circuit Families
CMOS VLSI Design 4th Ed.
19
Improved Loads
VDD
M1
Enable
M2
M1 >> M2
F
A
B
C
D
Adaptive Load
20
CMOS VLSI Design 4th Ed.
CL
Improved Loads
10: Circuit Families
CMOS VLSI Design 4th Ed.
21
Improved Loads (2)
Differential Cascode Voltage Switch Logic (DCVSL)
22
CMOS VLSI Design 4th Ed.
DCVSL Example
Out
Out
B
B
A
B
B
A
XOR-NXOR gate
23
CMOS VLSI Design 4th Ed.
DCVSL Example
24
CMOS VLSI Design 4th Ed.
DCVSL Transient Response
10: Circuit Families
CMOS VLSI Design 4th Ed.
25
Pass-Transistor Logic
Inputs
B
Switch
Out
A
Out
Network
B
B
• N transistors
• No static consumption
26
CMOS VLSI Design 4th Ed.
Example: AND Gate
10: Circuit Families
CMOS VLSI Design 4th Ed.
27
NMOS-Only Logic
10: Circuit Families
CMOS VLSI Design 4th Ed.
28
NMOS-Only Switch
29
CMOS VLSI Design 4th Ed.
NMOS Only Logic:
Level Restoring Transistor
• Advantage: Full Swing
• Restorer adds capacitance, takes away pull down current at X
• Ratio problem
30
CMOS VLSI Design 4th Ed.
Restorer Sizing
10: Circuit Families
CMOS VLSI Design 4th Ed.
31
LEAP
 LEAn integration with Pass transistors
 Get rid of pMOS transistors
– Use weak pMOS feedback to pull fully high
– Ratio constraint
S
A
S
L
Y
B
10: Circuit Families
CMOS VLSI Design 4th Ed.
32
Complementary Pass Transistor
Logic
A
A
B
B
Pass-Transistor
Network
F
(a)
A
A
B
B
B
B
B
A
F
B
B
F=AB
A
B
F=A+B
F=AB
AND/NAND
A
F=AÝ
(b)
A
A
B
B
A
A
B
33
Inverse
Pass-Transistor
Network
F=A+B
B
OR/NOR
A
EXOR/NEXOR
CMOS VLSI Design 4th Ed.
F=AÝ
CPL
 Complementary Pass-transistor Logic
– Dual-rail form of pass transistor logic
– Avoids need for ratioed feedback
– Optional cross-coupling for rail-to-rail swing
S
A
S
L
Y
L
Y
B
S
A
S
B
10: Circuit Families
CMOS VLSI Design 4th Ed.
34
Alternative CPL
10: Circuit Families
CMOS VLSI Design 4th Ed.
35
Transmission Gate
10: Circuit Families
CMOS VLSI Design 4th Ed.
36
Resistance of Transmission Gate
30
2.5 V
Resistance, ohms
Rn
20
2.5 V
Vou t
Rp
10
0
0.0
37
Rp
Rn
0V
Rn || Rp
1.0
Vou t , V
2.0
CMOS VLSI Design 4th Ed.
Pass Transistor Circuits
 Use pass transistors like switches to do logic
 Inputs drive diffusion terminals as well as gates
 CMOS + Transmission Gates:
– 2-input multiplexer
– Gates should be restoring
S
S
A
A
S
S
Y
Y
B
B
S
10: Circuit Families
S
CMOS VLSI Design 4th Ed.
38
Pass-Transistor Based Multiplexer
S
S
VDD
S
A
VDD
M2
F
S
M1
B
S
GND
39
In1 S
S
In2
CMOS VLSI Design 4th Ed.
Transmission Gate XOR
10: Circuit Families
CMOS VLSI Design 4th Ed.
40
Delay in Transmission Gate Networks
10: Circuit Families
CMOS VLSI Design 4th Ed.
41
Delay Optimization
42
CMOS VLSI Design 4th Ed.
Transmission Gate Full Adder
P
VDD
VDD
Ci
A
P
A
A
P
B
VDD
Ci
A
P
Ci
S Sum Generation
Ci
P
B
VDD
A
P
Co Carry Generation
Ci
A
Setup
P
Similar delays for sum and carry
43
CMOS VLSI Design 4th Ed.
Other Pass Transistor Families






DPTL (Differential Pass Transistor Logic)
DPL (Double Pass Transistor Logic)
EEPL (Energy Economized Pass Transistor Logic)
PPL (Push-Pull Pass Transistor Logic)
SRPL (Swing Restored Pass Transistor Logic)
DCVSPG (Differential Cascode Voltage Switch with
Pass Gate Logic)
10: Circuit Families
CMOS VLSI Design 4th Ed.
44
Pass Transistor Summary
 Researchers investigated pass transistor logic for
general purpose applications in the 1990’s
– Benefits over static CMOS were small or negative
– No longer generally used
 However, pass transistors still have a niche in
special circuits such as memories where they offer
small size and the threshold drops can be managed
10: Circuit Families
CMOS VLSI Design 4th Ed.
45
Single Clock 2-Phase System
T/2
10: Circuit Families
T
3T/2
CMOS VLSI Design 4th Ed.
46
Shift Register
VDD
P HIBA R
VDD
P HI
A
P HI
P HIBA R
10: Circuit Families
CMOS VLSI Design 4th Ed.
47
Shift Register
 When f = 1, data move through the first
transmission gate to the inverter.
TG  RTG CL
CL  CTG  Cinv  Cline
When VA  1,
 t  

Vin t   VDD 1  e TG 


When VA  0,
Vin t   VDD e
10: Circuit Families

 t
TG
CMOS VLSI Design 4th Ed.
48
Charge Leakage
P HIBAR
A
CL
P HI
10: Circuit Families
CMOS VLSI Design 4th Ed.
49
Charge Leakage
IL  ILn  ILp
dVin
C
 IL
dt
dQstore
 ILp  ILn
dt
dQstore
Cstore 
dV

10: Circuit Families
CMOS VLSI Design 4th Ed.
50
Charge Leakage
 Both Q and I are nonlinear
 Assume that I’s are constant.
Qstore  Cstore V
dV
Cstore
 ILp  ILn
dt
ILp  ILn
V t  
t  V 0
Cstore
C DV
t max  store
IL
f min 
1
IL

2t max 2Cstore DV
CMOS VLSI Design 4th Ed.
10: Circuit Families

51
Charge Sharing
P HIBA R
C1
C2
P HI
10: Circuit Families
CMOS VLSI Design 4th Ed.
52
Charge Sharing
 We can write
At t  0,
V1  VDD ,V2  0, QT  C1VDD
At t  t f , QT  C1  C2 V f
C1
Vf 
VDD
C1  C2
 The more general case:
N

QT   CiVi 0,
i1
 N 
QT   Ci V f
i1 
N
 C V 0
i i
Vf 
i1
N
C
i
i1
10: Circuit Families
CMOS VLSI Design 4th Ed.
53
Dynamic CMOS
 In static circuits at every point in time (except
when switching) the output is connected to
either GND or VDD via a low resistance path.
– fan-in of n requires 2n (n N-type + n P-type)
devices
 Dynamic circuits rely on the temporary
storage of signal values on the capacitance
of high impedance nodes.
– requires on n + 2 (n+1 N-type + 1 P-type)
transistors
54
CMOS VLSI Design 4th Ed.
Dynamic Gate
Clk
Clk
Mp
off
Mp on
Out
In1
In2
In3
CL
A
PDN
C
B
Clk
Me
Clk
Two phase operation
Precharge (Clk = 0)
Evaluate (Clk = 1)
56
1
Out
((AB)+C)
CMOS VLSI Design 4th Ed.
off
Me on
Conditions on Output
 Once the output of a dynamic gate is
discharged, it cannot be charged again until
the next precharge operation.
 Inputs to the gate can make at most one
transition during evaluation.
 Output can be in the high impedance state
during and after evaluation (PDN off), state is
stored on CL
57
CMOS VLSI Design 4th Ed.
Properties of Dynamic Gates
 Logic function is implemented by the PDN only
– number of transistors is N + 2 (versus 2N for static complementary
CMOS)
 Full swing outputs (VOL = GND and VOH = VDD)
 Non-ratioed - sizing of the devices does not affect
the logic levels
 Faster switching speeds
– reduced load capacitance due to lower input capacitance (Cin)
– reduced load capacitance due to smaller output loading (Cout)
– no Isc, so all the current provided by PDN goes into discharging CL
58
CMOS VLSI Design 4th Ed.
Properties of Dynamic Gates
 Overall power dissipation usually higher than
static CMOS
– no static current path ever exists between VDD and
GND (including Psc)
– no glitching
– higher transition probabilities
– extra load on Clk
 PDN starts to work as soon as the input signals
exceed VTn, so VM, VIH and VIL equal to VTn
– low noise margin (NML)
 Needs a precharge/evaluate clock
59
CMOS VLSI Design 4th Ed.
Dynamic Logic
 Dynamic gates uses a clocked pMOS pullup
 Two modes: precharge and evaluate
2
A
f
2/3
Y
1
Y
1
A
Static
4/3
Pseudo-nMOS
f
Precharge
Y
A
1
Dynamic
Evaluate
Precharge
Y
10: Circuit Families
CMOS VLSI Design 4th Ed.
60
The Foot
 What if pulldown network is ON during precharge?
 Use series evaluation transistor to prevent fight.
precharge transistor
f
Y
f
f
Y
inputs
A
Y
inputs
f
f
foot
footed
10: Circuit Families
CMOS VLSI Design 4th Ed.
unfooted
61
Logical Effort
Inverter
f
unfooted
NAND2
1
gd
pd
footed
2
2
10: Circuit Families
2
B
2
gd
pd
= 2/3
= 3/3
f
1
1
B
Y
gd
pd
= 2/3
= 3/3
A
1
gd
pd
= 1/3
= 3/3
1
Y
1
Y
A
A
= 1/3
= 2/3
f
f
1
Y
1
Y
A
f
NOR2
A
3
B
3
3
f
1
Y
gd
pd
= 3/3
= 4/3
CMOS VLSI Design 4th Ed.
A
2
B
2
2
gd
pd
= 2/3
= 5/3
62
Issues in Dynamic Design 1: Charge Leakage
CLK
Clk
Mp
Out
CL
A
Clk
Me
Evaluate
VOut
Precharge
Leakage sources
Dominant component is subthreshold current
63
CMOS VLSI Design 4th Ed.
Solution to Charge Leakage
Keeper
Clk
Mp
A
Mkp
CL
Out
B
Clk
Me
Same approach as level restorer for pass-transistor logic
64
CMOS VLSI Design 4th Ed.
Issues in Dynamic Design 2: Charge Sharing
Clk
Mp
Out
A
CL
B=0
Clk
65
Charge stored originally on CL
is redistributed (shared) over
CL and CA leading to reduced
robustness
CA
Me
CB
CMOS VLSI Design 4th Ed.
Charge Sharing Example
Clk
A
A
B
B
B
Cc=15fF
C
C
Ca=15fF
Out
CL=50fF
!B
Clk
66
CMOS VLSI Design 4th Ed.
Cb=15fF
Cd=10fF
Charge Sharing
VDD
case 1) if DV out < VTn
VDD
Mp
Clk
f
Mp
Out
Out
CL
CL
Ma
A
A
Ma
=
BB
00
Clk f
67
M
Mb
b
Mee
M
XX
a
CC
a
CC
bb
C L VDD = C L Vout  t  + Ca  VDD – V Tn  V X  
or
Ca
DV out = Vout  t  – V DD = – --------  V DD – V Tn  V X  
CL
case 2) if DV out > VTn
C
 --------------------a -
DVout = –V DD 

C
+
C
 a
L
CMOS VLSI Design 4th Ed.
Solution to Charge Redistribution
Clk
Mp
Mkp
Clk
Out
A
B
Clk
Me
Precharge internal nodes using a clock-driven transistor (at
the cost of increased area and power)
68
CMOS VLSI Design 4th Ed.
Issues in Dynamic Design 3: Backgate Coupling
Clk
Mp
A=0
Out1 =1
Out2 =0
CL1
CL2
B=0
Clk
Me
Dynamic NAND
69
Static NAND
CMOS VLSI Design 4th Ed.
In
Backgate Coupling Effect
3
2
Out1
1
Clk
0
In
Out2
-1
0
2
Time, ns
4
CMOS VLSI Design 4th Ed.
6
70
Issues in Dynamic Design 4: Clock
Feedthrough
Clk
Mp
A
CL
B
Clk
71
Out
Me
Coupling between Out and Clk
input of the precharge device
due to the gate to drain
capacitance. So voltage of Out
can rise above VDD. The fast
rising (and falling edges) of the
clock couple to Out.
CMOS VLSI Design 4th Ed.
Clock Feedthrough
Clock feedthrough
Clk
Out
2.5
In1
In2
1.5
In3
In &
Clk
0.5
In4
Clk
Out
-0.5
0
0.5
Time, ns
1
Clock feedthrough
72
CMOS VLSI Design 4th Ed.
Other Effects




73
Capacitive coupling
Substrate coupling
Minority charge injection
Supply noise (ground bounce)
CMOS VLSI Design 4th Ed.
Cascading Dynamic Gates
V
Clk
Mp
Clk
Mp
Out1
Me
Clk
Out2
In
In
Clk
Clk
Me
Out1
VTn
DV
Out2
t
Only 0  1 transitions allowed at inputs!
74
CMOS VLSI Design 4th Ed.
Monotonicity
 Dynamic gates require monotonically rising inputs
during evaluation
f
– 0 -> 0
A
– 0 -> 1
– 1 -> 1
violates monotonicity
– But not 1 -> 0
during evaluation
A
f
Precharge
Evaluate
Precharge
Y
Output should rise but does not
10: Circuit Families
CMOS VLSI Design 4th Ed.
75
Monotonicity Woes
 But dynamic gates produce
monotonically falling
outputs during evaluation
 Illegal for one dynamic gate
to drive another!
A=1
f
A
Y
f
Precharge
Evaluate
Precharge
X
X
X monotonically falls during evaluation
Y
Y should rise but cannot
10: Circuit Families
CMOS VLSI Design 4th Ed.
76
Domino Logic
Clk
In1
In2
In3
Clk
77
Mp
11
10
PDN
Me
Out1
Clk
Mp Mkp
00
01
In4
In5
Clk
PDN
Me
CMOS VLSI Design 4th Ed.
Out2
Domino Gates
 Follow dynamic stage with inverting static gate
– Dynamic / static pair is called domino gate
– Produces monotonic outputs
f
Precharge
Evaluate
Precharge
domino AND
W
W
X
Y
Z
X
A
B
C
f
Y
Z
dynamic static
NAND inverter
f
A
B
10: Circuit Families
f
f
W
X
H
C
CMOS VLSI Design 4th Ed.
Y
H
Z
=
A
B
f
X
Z
C
78
Domino Optimizations
 Each domino gate triggers next one, like a string of
dominos toppling over
 Gates evaluate sequentially but precharge in parallel
 Thus evaluation is more critical than precharge
 HI-skewed static stages can perform logic
f
S0
S1
S2
S3
D0
D1
D2
D3
H
Y
f
10: Circuit Families
S4
S5
S6
S7
D4
D5
D6
D7
CMOS VLSI Design 4th Ed.
79
Dual-Rail Domino
 Domino only performs noninverting functions:
– AND, OR but not NAND, NOR, or XOR
 Dual-rail domino solves this problem
– Takes true and complementary inputs
– Produces true and complementary outputs
sig_h
sig_l
Meaning
0
0
Precharged
0
1
‘0’
1
0
‘1’
1
1
invalid
10: Circuit Families
f
Y_l
inputs
f
Y_h
f
f
CMOS VLSI Design 4th Ed.
80
Example: AND/NAND
 Given A_h, A_l, B_h, B_l
 Compute Y_h = AB, Y_l = AB
 Pulldown networks are conduction complements
f
Y_l
A_h
= A*B
A_l
B_l
Y_h
= A*B
B_h
f
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Example: XOR/XNOR
 Sometimes possible to share transistors
f
Y_l
= A xnor B
A_h
Y_h
A_l
A_l
B_l
B_h
A_h
= A xor B
f
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np-CMOS
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NORA Logic
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NP Domino
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Zipper CMOS
 The NP-Domino or NORA logic is very susceptible
to noise and leakage.
 Zipper Domino has the same structure, but the
precharge transistors are left slightly ON during
evaluation.
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Leakage
 Dynamic node floats high during evaluation
– Transistors are leaky (IOFF  0)
– Dynamic value will leak away over time
– Formerly miliseconds, now nanoseconds
 Use keeper to hold dynamic node
– Must be weak enough not to fight evaluation
weak keeper
f
A
1 k
X
H
Y
2
2
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Charge Sharing
 Dynamic gates suffer from charge sharing
f
f
A
Y
CY
x
A
Y
B=0
Cx
Charge sharing noise
x
CY
Vx  VY 
VDD
Cx  CY
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Secondary Precharge
 Solution: add secondary precharge transistors
– Typically need to precharge every other node
 Big load capacitance CY helps as well
f
Y
A
secondary
precharge
transistor
x
B
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Noise Sensitivity
 Dynamic gates are very sensitive to noise
– Inputs: VIH  Vtn
– Outputs: floating output susceptible noise
 Noise sources
– Capacitive crosstalk
– Charge sharing
– Power supply noise
– Feedthrough noise
– And more!
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Power
 Domino gates have high activity factors
– Output evaluates and precharges
• If output probability = 0.5, a = 0.5
– Output rises and falls on half the cycles
– Clocked transistors have a = 1
– For a 4 input NAND, aCMOS = 3/16, aDynamic = 1/4
 Leads to very high power consumption
 However, glitching does not occur in dynamic logic.
 The load capacitances are lower.
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Completion Detection
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Keepers
 Keeper design is not trivial.
 Many alternatives have been suggested.
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Conventional Keeper
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Weak Keepers
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Differential Keeper
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Burn-in Conditional Keeper
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Adaptive Keeper
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Leakage Current Replica Keeper
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Footed and Footless Domino
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8-input Domino AND
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8-input Domino AND
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MODL
 It is often necessary to compute multiple functions
where one is a subfunction of the other or shares a
subfunction.
 One very typical example is the carry in addition:
c1  g1  p1c 0
c 2  g2  p2 g1  p1c 0 


c 3  g3  p3 g2  p2 g1  p1c 0 



c 4  g4  p4 g3  p3 g2  p2 g1  p1c 0 
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MODL Carry Chains
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MODL
 Beware of sneak paths.
 Certain inputs must be mutually exclusive.
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Domino Summary
 Domino logic is attractive for high-speed circuits
– 1.3 – 2x faster than static CMOS
– But many challenges:
• Monotonicity, leakage, charge sharing, noise
 Widely used in high-performance microprocessors in
1990s when speed was king
 Largely displaced by static CMOS now that power is
the limiter
 Still used in memories for area efficiency
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2-input MUX
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Which Logic Style?





Ease of design
Robustness
Area
Speed
Power
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Which Logic Style?
Ease of
Design
Robustness
Area
Speed
Power
Static
Very good
Very good
Bad
Bad
Good
PseudonMOS
Average
Average
Good
Good
Very bad
Pass
transistor
Difficult
Average
Good (for
specific
circuits)
Good (for
specific
circuits)
average
Dynamic
logic
Very
difficult
Very bad
Good
Good
average
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Circuit Pitfalls










Threshold drops
Ratio failures
Charge sharing
Power supply noise
Coupling
Minority carrier injection
Back-gate coupling
Diffusion input noise sensitivity
Race conditions
Delay matching
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Circuit Pitfalls




Metastability
Hot spots
Soft errors
Process sensitivity
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Threshold Drops
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Ratio Failures
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Power Supply Noise
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Hot Spots
 Caused by nonuniform power dissipation even when
the overall power consumption is within budget.
 Causes variation in delay between gates.
 Full-chip temperature simulation is required.
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Minority Carrier Injection
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Minority Carrier Injection
 Sometimes, a node voltage can momentarily exceed
power supply voltages.
 Then, the drain-body junction becomes forward
biased.
 Noise tools can identify potential problems.
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Diffusion Input Noise Sensitivity
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Diffusion Input Noise Sensitivity
 Exposed diffusion inputs are particularly sensitive to
noise.
 Standard cell latches should be built with buffered
inputs.
 In data paths, one can still utilize exposed diffusion
inputs since one knows the structure.
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Domino Noise Budgets









Charge leakage
Charge sharing
Capacitive coupling
Back-gate coupling
Minority carrier injection
Power supply noise
Soft errors
Noise feedthrough
Process corner effects
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Domino Noise Budgets
Source
Dynamic Output
Dynamic Input
Charge Sharing
10
n/a
Coupling
17
7
Supply Noise
5
5
Feedthrough Noise
5
7
Total
37%
19%
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Silicon-on-Insulator Circuit Design
 SOI technology has been around for decades as
research.
 It was adopted by IBM for PowerPC in 1998.
 Potential for higher performance and lower power
consumption.
 Higher manufacturing cost and more complicated
circuit design due to unusual transistor behavior.
 There is no bulk, but insulator.
 Body is floating, thus changes in Vt.
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SOI Inverter Cross Section
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SOI Process Electron Micrograph
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SOI Circuit Design
 SOI devices are characterized as
– Partially Depleted (PD)
– Fully Depleted (FD)
 In FD SOI, the body is thinner than the channel
depletion width, so the body charge is fixed. Thus,
the body voltage does not change.
 In PD SOI, the body is thicker and its voltage can
vary depending on how much charge is present.
This varying body voltage changes Vt.
 FD SOI is difficult to manufacture.
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Charge Paths in SOI Body
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Charge Paths
 There are two paths through which charge can build up in the
body:
– Reverse biased drain-to-body (Ddb) and possibly source-tobody (Dsb) junctions.
– High-energy carriers causing impact ionization, creating
electron-hole pairs. Some electrons are injected into the
gate or gate oxide, leaving holes behind.
 The charge can exit the body through two paths:
– As body voltage increases, Dsb becomes slightly forward
biased. Eventually, this cancels the first mechanism above.
– A rising gate or drain voltage capacitively couples the body
voltage upward, too. This strongly forward biases Dsb
junction and charge spills out.
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SOI Advantages
 Lower diffusion capacitance.
– Smaller parasitic delay and lower power
consumption.
 Potential for lower threshold voltages.
– Vt is dependent on channel length for bulk
CMOS. Thus, worst case conditions are selected
in determining Vt. In SOI, variations are smaller,
thus smaller Vt can be chosen.
 Lower n, hence better subthreshold slope.
– n decreases from 1.5 to about 1.2.
 SOI is immune to latchup.
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SOI Disadvantages
 PD SOI suffers from history effect.
– 8% variation in gate delay.
– Can be a problem for sensitive analog circuits.
 Presence of a parasitic bipolar transistor.
– If the source and drain are held high for an
extended period of time while the gate is low, the
base will float high due to leakage.
– If the source is pulled low, the npn turns ON,
creating a pulse of current.
– This is sometimes called pass-gate leakage.
 Self-heating => oxide is an insulator for heat as well.
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Parasitic BJT in SOI
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Implications for Circuit Styles
 SOI is attractive for fast CMOS logic.
– Lower delay, lower power consumption.
 Standard CMOS design suffers slightly from history
effect.
 Dynamic circuits suffer from pass-gate leakage.
Many precautions must be taken.
 Analog circuits suffer from threshold mismatches.
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Subthreshold Circuit Design
 As discussed earlier, the minimum energy point is at
a region where VDD < Vt.
 Typically, around 300 mV.
 Frequency is in the high kHz or low MHz region.
 Vt variations are very important, use large transistors
where possible.
 Use standard CMOS, but avoid complex gates. Not
more complex than NAND3. Due to variations, ON
current in one branch may be smaller than OFF
current in the series stack.
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Pitfalls and Fallacies
 Failing to plan for advances in technology
 Comparing a well-tuned new circuit to a poor
example of engineering practice
 Ignoring driver resistance when characterizing passtransistor circuits.
 Reporting only part of the delay of a circuit
 Making outrageous claims about performance
 Building circuits without adequate verification tools.
 Sizing subthreshold circuits for speed
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Historical Perspective
 Ratioed and dynamic circuits are actually earlier
than CMOS.
 In an NMOS process, PMOS transistors were not
available.
 Dynamic gates were proposed in early 1970’s.
 Even with CMOS, domino gates were still used for
area and power advantages, for example in
BELLMAC-32A from Bell Labs.
– The world’s first 32-bit microprocessor
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Historical Perspective
 By the time of Alpha 21264, leakage had become so
important that keepers had to be used.
– 1996, superscalar, out-of-order execution
 180 nm Pentium 4 used self-resetting domino.
 90 nm Pentium 4 used extraordinarily complex LVS
logic. Custom design of 6.8M transistors.
 Japanese engineers favored pass transistor logic all
through 1990’s.
 IBM has always relied on static CMOS.
 Hundreds of logic families in academic literature, but
very few have found application in industry.
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