Processor Design
Computer Architecture
CS 215
Updated 10/21/14
Registers
 Special purpose registers
 Accumulators (arithmetic registers)
 Status register
Machine Types
 Accumulator machines


Limited number of data accumulators
1-address machines
 Stack machines



No register names
Registers organized as a stack
0-address machine
 General register machines


Most often used today
Registers used for almost any purpose
Instruction Sets
 Each family of CPUs has its own
instruction set
 Instruction codes are mapped to
instructions




Data movement
Arithmetic
Logic
Control
Instructions
 Must contain …




Which operation to perform
Where to find the operand(s), if any
Where to put the result, if any
Where to find the next instruction
Memory Access
 Each register has a unique address
 Two operations


Read
Write
Memory Access: Read
 CPU places an address on the address
bus, and a read request on the control
bus
 Memory unit receives request, decodes
address, and locate data at address
 Memory unit places data on data bus
 Memory unit places a complete
message on control bus
Memory Access: Write
 CPU places an address on the address
bus, value to be written on data bus,
and a write request on the control bus
 Memory unit receives request, decodes
address
 Memory unit stores data at address
 Memory unit places a complete
message on control bus
Addressing Modes
 Immediate

i
 Direct

M[i]
 Indirect

M[M[i]]
 Register direct

R[i]
 Register indirect

M[R[i]]
 Displacement

M[R[i]+c]]
 Relative

M[PC+c]
SRC Instructions
 Load instructions

ld, ldr, la, lar
 Store instructions

st, str
 Arithmetic

add, addi, sub, neg
 Logic


and, andi, or, ori, not
shr, sha, shl, shc
 Branching

br, brl
 Miscellaneous

nop, stop
Instruction Formats
ld, st, la, addi, andi, ori
31
27 26
Op
22 21
ra
17 16
12 11
rb
4
2 0
4
2 0
c2
ldr, str, lar
31
27 26
Op
22 21
ra
17 16
12 11
c1
Instruction Formats
neg, not
31
27 26
Op
22 21
ra
17 16
unused
12 11
rc
4
2 0
4
2 0
unused
br
31
27 26
Op
22 21
unused
17 16
rb
12 11
rc
(c3)
unused
Cond
Instruction Formats
brl
31
27 26
Op
22 21
ra
17 16
rb
12 11
rc
4
(c3)
unused
2 0
Cond
add, sub, and, or
31
27 26
Op
22 21
ra
17 16
rb
12 11
rc
4
unused
2 0
Instruction Formats
shr, shra, shl, shc
31
27 26
Op
31
22 21
ra
27 26
Op
17 16
12 11
rb
22 21
ra
4
(c2)
17 16
rb
unused
12 11
rc
Count
4
(c3)
unused
2 0
2 0
00000
nop, stop
31
27 26
Op
22 21
17 16
12 11
unused
4
2 0
cnt:
Example:
.equ
.org
seq: .dc
next: .dc
ans: .dw
.org
lar
la
la
loop: ld
ld
add
st
addi
addi
brnz
stop
8
0
1
1
cnt
0x1000
r31, loop
r0,
cnt
r1,
seq
r2,
seq(r1)
r3,
next(r1)
r2,
r2,
r3
r2,
ans(r1)
r1,
r1,
4
r0,
r0
-1
r31, r0
Try this!
 Develop instruction formats for a 16-bit
CPU, which has 16, 16-bit general
purpose registers.
CPU Design
 Control Unit

Generates the control
signals in the correct
order to effect the
correct data path
activity
 Data Path


Set of
interconnections and
auxiliary registers
Needed to accomplish
overall changes an
instruction makes
CPU
Control Unit
Control signals
out
Data Path
Control unit
inputs
Register Transfer Notation
 Provides a formal means of describing machine




structure and function
Is at the “just right” level for machine
descriptions
Does not replace hardware description
languages.
Can be used to describe what a machine does
(an Abstract RTN) without describing how the
machine does it.
Can also be used to describe a particular
hardware implementation (A Concrete RTN)
RTN (Cont’d.)
 At first you may find this “meta description”
confusing, because it is a language that is used to
describe a language.
 You will find that developing a familiarity with RTN
will aid greatly in your understanding of new machine
design concepts.
 We will describe RTN by using it to describe SRC.
Static Properties
 Specifying registers

IR31..0 specifies a register named “IR” having 32
bits numbered 31 to 0
 “Naming” using the := naming operator:


op4..0 := IR31..27 specifies that the 5 msbs of IR
be called op, with bits 4..0.
Notice that this does not create a new register, it
just generates another name, or “alias” for an
already existing register or part of a register.
Dynamic Properties
• Conditional expressions:
(op=12)  R[ra]  R[rb] + R[rc]:
“if” condition “then”
; defines the add instruction
RTN Assignment Operator
This fragment of RTN describes the SRC add instruction. It says,
“when the op field of IR = 12, then store in the register specified
by the ra field, the result of adding the register specified by the
rb field to the register specified by the rc field.”
Register Declarations
 General register specifications shows some features
of the notation
 Describes a set of 32 32-bit registers with names
R[0] to R[31]
R[0..31]31..0:
Name of
registers
Register #
in square
brackets
msb #
.. specifies
a range of
indices
lsb#
Bit # in
angle
brackets
Colon separates
statements with
no ordering
Naming Operator
 Defining names with formal parameters is a
powerful formatting tool
 Used here to define word memory (big endian)
M[x]31..0 := Mem[x]#Mem[x+1]#Mem[x+2]#Mem[x+3]:
Dummy
parameter
Naming
operator
Concatenation
operator
All bits in
register if no
bit index given
Memory
 Processor State
PC<31..0>:
 32-bit register Program Counter
IR<31..0>:
 32-bit register Instruction Register
Run:
 1-bit run/halt indicator
Strt:
 Start signal
R[0..31]<31..0>:
 32, 32-bit general purpose registers
Main Memory
Mem[0..232-1]<7..0>:

232 addressable bytes of memory
M[x]<31..0>:

= Mem[x]#Mem[x+1]#Mem[x+2]#Mem[x+3]:
Instruction Formats
op<4..0>: = IR<31..27>

Operation code field
ra<4..0>: = IR<26..22>

Target register field
rb<4..0>: = IR<21..17>

Operand, address index, or branch target register
rc<4..0>: = IR<16..12>

Second operand, conditional test, or shift count
register
Instruction Formats
c1<21..0>: = IR<21..0>

Long displacement field
c2<16..0>: = IR<16..0>

Short displacement or immediate field
c3<11..0>: = IR<11..0>

Count or modifier field
Effective Address Calculations
 Displacement
disp<31..0>:=((rb=0)c2<16..0>
{sign extend}:
(rb0)R[rb]+c2<16..0>
{sign extend, 2’s compliment}):
 Relative
rel<31..0>:=PC<31..0>+c1<21..0>
{sign extend, 2’s comp}:
Instruction Interpretation &
Execution
instruction_interpretation:=(
RunStrt(Run1: instruction_intepretation):
Run(IRM[PC]:PCPC+4: instruction_execution):
):
Load & Store Instructions
instruction_execution:=(
ld(:=op=1)R[ra]M[disp]:
ldr(:=op=2)R[ra]M[rel]:
st(:=op=3)M[disp]R[ra]:
str(:=op=4)M[rel]R[ra]:
la(:=op=5)R[ra]disp:
lar(:=op=6)R[ra]rel:
load register
load register relative
store register
store register relative
load displacement address
load relative address
Branch Instruction
Never
Always
Register=0
c3<2..0>=3 R[rc]0 :
Register0
c3<2..0>=4R[rc]<31>=0: >= 0
c3<2..0>=5R[rc]<31>=1): < 0
br(:=op=8)(condPC  R[rb]):
Cond branch
brl(:=op=9)(R[ra]PC:
Branch & link
cond:=( c3<2..0>=00:
c3<2..0>=11:
c3<2..0>=2R[rc]=0:
cond(PCR[rb])):
ALU Instructions
 Arithmetic Instructions
add(:=op=12)R[ra]R[rb]+R[rc]:
addi(:=op=13)R[ra]R[rb]+c2<16..0>:
sub(:=op=14)R[ra]R[rb]-R[rc]:
neg(:=op=15)R[ra]-R[rc]:
ALU Instructions
 Logical Operations
and(:=op=20)R[ra]R[rb]R[rc]:
andi(:=op=21)R[ra]R[rb]c2<16..0>:
or(:=op=22)R[ra]R[rb]R[rc]:
ori(:=op=23)R[ra]R[rb]c2<16..0>:
not(:=op=24)R[ra]R[rc]:
ALU Instructions
 Shift Operations
n:= ((c3<4..0>=0)R[rc]<4..0>:
(c3<4..0>0)c3<4..0>):
shr(:=op=26)R[ra]<31..0>(n@0)#R[rb]<31..n>:
shra(:=op=27)R[ra]<31..0>(n@R[rb]<31>)#R[rb]<31..n>:
shl(:=op=28)R[ra] <31..0>R[rb]<31-n..0>#(n@0):
shc(:=op=29)R[ra] <31..0>R[rb]<31-n..0>#R[rb]<31..32-n>
Miscellaneous Instructions
nop(:=op=0):
stop(:=op=31)run0):
instruction_interpretation:
No operation
Stop instruction
End of
instr_execution;
invoke
instr_interpretation
Abstract vs. Concrete RTN
 Abstract: What occurs

R[3]  R[1] + R[2];
 Concrete: How it occurs

Y  R[2]; Z  R[1] + Y; R[3]  Z;
 Control Sequence

R[2]out, Yin; R[1]out, Zin; Zout, R[3]in;
Bus Transfers
The Rules of Buses
1. Only one item can be on the bus during a
given clock cycle.
2. The contents of the bus disappear at the
end of the clock cycle. No information is
“stored” on the bus from cycle to cycle; any
value to be saved must be stored into a
register at the end of the clock cycle.
Clock Cycle
1-Bus Microarchitecture
31
 Only one value
can be placed
on the bus at
any time
0
 
R0
32 32-bit
General
Purpose Registers
32
31
0
PC
R31
IR
A
A
B
MA
To memory subsystem
ALU
C
C
MD
Abstract Vs. Concrete RTN
31
How would you
accomplish the
following
instruction using
this architecture?
add(:=op=12)
R[ra]R[rb]+R[rc]:
0
 
R0
32 32-bit
General
Purpose Registers
32
31
0
PC
R31
IR
A
A
B
MA
To memory subsystem
ALU
C
C
MD
Abstract Vs. Concrete RTN
31
add(:=op=12)
R[ra]R[rb]+
R[rc]:
0
 
R0
32 32-bit
General
Purpose Registers
32
31
0
PC
R31
IR
Step RTN
A
A
B
MA
To memory subsystem
ALU
C
C
MD
Abstract Vs. Concrete RTN:
addi
Step RTN
T0. MA  PC: C  PC + 4;
T1. MD  M[MA]; PC  C;
T2. IR  MD;
T3. A  R[rb];
T4. C  A + c2<16..0> {sign ext.};
T5. R[ra]  C;
Abstract Vs. Concrete RTN:
ld
Step RTN
T0-T2 Instruction fetch
T3. A  (rb=0  0: rb0  R[rb]);
T4. C  A + (16@IR<16>#IR<15..0>);
T5. MA  C;
T6. MD  M[MA];
T7. R[ra]  MD;
Abstract Vs. Concrete RTN:
st
Step RTN
T0-T2 Instruction fetch
T3. A  (rb=0  0: rb0  R[rb]);
T4. C  A + (16@IR<16>#IR<15..0>);
T5. MA  C;
T6. MD  R[ra];
T7. M[MA]  MD;
Abstract Vs. Concrete RTN:
br
Step RTN
T0-T2 Instruction fetch
T3. CON  cond(R[rc]);
T4. CON  PC  R[rb];
Abstract Vs. Concrete RTN:
shr
Step Concrete RTN
T0-T2 Instruction fetch
T3. n  IR<4..0>;
T4. (n=0)  (n  R[rc]<4..0> ;
T5. C  R[rb];
T6. Shr (:= (n≠0)(C<31..0>0#C<31..1>:
n  n-1; Shr) );
T7. R[ra]  C;
More Detail …
More Detail …
ra, rb, rc fields
Control
signals
5x32
decoder
General
purpose
registers
Try this!
 Problem

Extend the SRC instruction set by adding
the XOR command (op=19), similar to the
AND command
Note: The ALU cannot be altered by adding
XOR

Develop both an abstract and concrete
RTN for the instruction
Try this!
Instruction Register
Sign
extension
Memory Interface
From bus
From memory
To memory
To bus
ALU
ALU
Control sequences:
Instruction Fetch
Step
T0.
T1.
T2.
T3.
Concrete RTN
MA  PC: C  PC+4;
MD  M[MA]: PC  C;
IR  MD;
Instruction_execution
Control Sequence
PCout, MAin, Inc4, Cin
Read, Cout, PCin, Wait
MDout, IRin
Control sequences:
add
Step
T0.
T1.
T2.
T3.
T4.
T5.
Concrete RTN
MA  PC: C  PC+4;
MD  M[MA]: PC  C;
IR  MD;
A  R[rb];
C  A + R[rc];
R[ra]  C;
Control Sequence
PCout, MAin, Inc4, Cin, Read
Cout, PCin, Wait
MDout, IRin
Grb, Rout, Ain
Grc, Rout, ADD, Cin
Cout, Gra, Rin, End
Control sequences:
addi
Step
T0.
T1.
T2.
T3.
T4.
T5.
Concrete RTN
MA  PC: C  PC + 4;
MD  M[MA]; PC  C;
IR  MD;
A  R[rb];
C  A + c216..0 {sign ext.};
R[ra]  C;
Control Sequence
PCout, MAin, Inc4, Cin
Cout, PCin, Wait, Read
MDout, IRin
Grb, Rout, Ain
c2out, ADD, Cin
Cout, Gra, Rin, End
Control sequences:
st
Step
T0-T2
T3.
T4.
T5.
T6.
T7.
Concrete RTN
Control Sequence
Instruction fetch
Instruction fetch
A  (rb=0)  0: rb0  R[rb];
Grb, BAout, Ain
address arithmetic
C  A + c216..0 {sign ext.};
c2out, ADD, Cin
MA  C;
Cout, MAin
MD  R[ra];
Gra, Rout, MDin, Write
M[MA]  MD;
Wait, End
}
Control sequences:
shr
Step
T0-T2
T3.
T4.
T5.
T6.
T7.
Concrete RTN
Instruction fetch
n  IR4..0;
(n=0)  (n  R[rc]4..0);
C  R[rb];
Shr (:=(n≠0)
(C31..0  0#C31..1:
n  n-1; Shr) );
R[ra]  C;
Control Sequence
Instruction fetch
c1out, Ld
n=0  (Grc, Rout, Ld)
Grb, Rout, C=B, Cin
n0  (Cout, SHR, Cin,
Decr, Goto6)
Cout, Gra, Rin, End
Control sequences:
br
Step
T0-T2
T3.
T4.
Concrete RTN
Instruction fetch
CON  cond(R[rc]);
CON  PC  R[rb];
Control Sequence
Instruction fetch
Grc, Rout, CONin
Grb, Rout, CON  PCin, End
Clocking & Timing
Control Unit
2-Bus SRC
3-Bus SRC
Machine Reset
 From a need to initialize processor to a known,
defined state


Control Step Counter  0
PC  Known Value
 RTN



instruction_interpretation := (
RunStrt  (Run  1: PC, R[0..31]  0);
RunRst (IR  M[PC]: PC  PC + 4;
instruction_execution):
RunRst ( Rst  0: PC  0); instruction_interpretation):
Exceptions
 Different from branches and jumps
 Resolved in the writeback stage
Exceptions
 When detected …




Following instructions (earlier in the
pipeline) are marked as invalid
As they flow to the end of the pipe their
results are discarded
Program counter is set to the address of a
special exception handler
Special registers are written with the
exception location and cause
Exceptions
 Types:


System Reset
Machine Check Exceptions
 Memory error checking



Data Access Exceptions
Instruction Access Exceptions
Alignment Exceptions
Program Exceptions
 Illegal instruction
 Unimplemented instruction
 Privileged instruction
 Arithmetic errors (sometimes)
Other Exceptions
 Miscellaneous Hardware Exceptions

Countdown to zero
 Trace & Debugging Exceptions
 Nonmaskable Exceptions

Cannot be ignored

Power outage
 Interrupts (External)
Exception Process
 Interrupt signal asserted
 Determine if interrupt should be
serviced; Finish current instruction, if
possible
Exception Process
instruction_interpretation :=
(RunStrt  Run  1:
Run(ireqIE)  (IR M[PC]:
PC  PC + 4; instruction_execution):
Run(ireqIE)  (IPC  PC31..0:
II15..0 Isrc_info15..0: iack 1:
IE 0: PC  Ivect31..0; iack  0);
instruction_interpretation);