The Physical Structure (NMOS) Gate oxide Al SiO2 SiO2 S n+ Field Oxide Polysilicon Gate D n+ channel Al SiO2 Field Oxide L P Substrate contact Metal (G) (S) n+ L n+ (D) W Poly CONCORDIA VLSI DESIGN LAB 1 Transistor Resistance Two Components: Drain/ Sources Resistance: (G) : (S) n+ RD(S) = Rsh x no. of squares+ contact resistance. L (D) n+ W Channel Resistance: Depends on the region of operation: RCH = -------------------------------1 --------------------------------- ' W K' ----- VGS – VT –V DS L RC H = -------------------------2 --------------------------2 W K' ----- V –V L CONCORDIA VLSI DESIGN LAB GS RS Rch RD Linear Saturation T 2 Transistor Geometry CONCORDIA VLSI DESIGN LAB 3 Transistor Geometry- Detailed CONCORDIA VLSI DESIGN LAB 4 NMOS Operation-Linear 2 1 IDS N = KN VG SN – VTN VD SN – ---VD SN 2 K = C ox Cox ox = ------t ox KN=K’. W/L Process Transconductance uA/V2 for 0.35u, K’ (Kp)=196uA/ V2 Gate oxide capacitance per unit area ox = 3.9 x o = 3.45 x 10-11 F/m tox Oxide thickness for 0.35 , tox=100Ao IDS VGS Quick calculation of Cox: Cox= 0.345/tox (Ao) pf/um2 = mobility of electrons 550 cm2/V-sec for 0.35 process CONCORDIA VLSI DESIGN LAB VDS 5 NMOS Operation-Linear Effect of W/L W/L W Rds W Effect of temperature temp CONCORDIA VLSI DESIGN LAB Rds 6 Variations in Width and Length 1. Width Oxide encroachment Weff= Wdrawn-2WD polysilicon Weff Wdrawn WD WD polysilicon 2. Length Lateral diffusion LD = 0.7Xj Leff= Ldrawn-2LD CONCORDIA VLSI DESIGN LAB Ldrawn LD Leff LD 7 Large Transistors Rchannel decrease with increase of W/L of the transistor CONCORDIA VLSI DESIGN LAB 8 Semiconductor Resistors R= p(l /A) = (p/t). (l /w) = Rsh. (l /w) For 0.5u process: N+ diffusion : 70 / □ P+ diffusion : 140 /□ Polysilicon : 12 /□ Polycide:2-3 /□ 1 = ---------------------------------------------- n q + p qn p current M1: 0.06 M2: 0.06 M3: 0.03 P-well: 2.5K (A)w N-well: 1K l t Rsh values for 0.35u CMOS Process: Polysilicon 10 /□ Contact resistance: PolyI to MetalI 50 Polycide 2 /□ Via resistance: Metal I to Metal II 1.5 Metal1 0.07 /□ Via resistance: Metal II to metal III 1. Metal II 0.07 /□ Metal III 0.05 /□ CONCORDIA VLSI DESIGN LAB 9 Modelling: Resistance 1. Resistance: Rint= Rsh [l/w] Rsh values for 0.35u CMOS Process: Polysilicon 10 / Polycide 2 / Metal1 0.07 / Metal II 0.07 / Metal III 0.05 / Contact resistance: PolyI to MetalI 50 Via resistance: Metal I to Metal II 1.5 Via resistance: Metal II to metal III 1. CONCORDIA VLSI DESIGN LAB 10 Semiconductor Resistors Diffusion n+ polysilicon Al Field oxide Polysilicon Resistor CONCORDIA VLSI DESIGN LAB Al SiO2 n+ Diffusion Resistor 11 Delay Definitions Vin 50% t Vout t pHL t pLH 90% 50% 10% tf CONCORDIA VLSI DESIGN LAB t tr 12 Semiconductor Capacitors 1. Poly Capacitor: a. Poly to substrate b. Poly1 to Poly2 2. Diffusion Capacitor sidewall capacitances depletion region n+ (ND) substrate (NA) CONCORDIA VLSI DESIGN LAB bottomwall capacitance 13 Dynamic Behavior of MOS Transistor G CGS CGD D S CGB CSB CDB B CONCORDIA VLSI DESIGN LAB 14 Prentice Hall/Rabaey SPICE Parameters for Parasitics CONCORDIA VLSI DESIGN LAB 15 Prentice Hall/Rabaey SPICE Transistors Parameters CONCORDIA VLSI DESIGN LAB 16 Prentice Hall/Rabaey Computing the Capacitances VDD VDD M2 Vin Cg4 Cdb2 Cgd12 M4 Vout Cdb1 Cw M1 Vout2 Cg3 M3 Interconnect Fanout Simplified Model CONCORDIA VLSI DESIGN LAB Vin Vout CL 17 Computing the Capacitances CONCORDIA VLSI DESIGN LAB 18 CMOS Inverter: Steady State Response VDD VDD Ron VOH = VDD Vout Vout VOL = 0 Ron Vin = V DD CONCORDIA VLSI DESIGN LAB Vin = 0 19 Switching Characteristics of Inverters Transient Response VDD tpHL = f(R on.CL) = 0.69 RonCL Vout ln(0.5) Vout CL Ron 1 VDD 0.5 0.36 Vin = V DD CONCORDIA VLSI DESIGN LAB RonCL t 20 Step Response Fall Delay Time: TPHL MN OFF VDD=5V Saturation S Linear G VDD IDN MP D Vin Vin = 5 Vo D Vin G Vin= 4 CL MN S Vin= 3 GND VDD-VT VDD Vo (VDSAT) CONCORDIA VLSI DESIGN LAB 21 Step Response- Fall time, tf CL 2 (n – 0.1 ) t f = --------------------------------------- ------------------------ + ln (19 – 20n ) KN VDD (1 – n ) ( 1 – n ) vo 1 0.9 tf=~ k .CL n.VDD k is a constant vin CL ( – 2) (0.1 1 + p) tr = -------------------------------------- ---------------------------- + ln (19 + 20p ) K PVDD ( 1 + p ) (1 + p ) k .CL tr=~ p.VDD CONCORDIA VLSI DESIGN LAB 1-n 0.1 td1 td2 k is a constant 22 Step Response-tPHL Assume normalized voltages vin= Vin/ VDD vo= Vo/ VDD n = VTN/ VDD p = VTP/ VDD Vo Vx VDD-VTN VDD/ 2 Vin td1 tPHL=td1+td2 CL 2n t PHL = --------------------------------------- ---------------- + ln (3 – 4n ) K NVDD (1 – n ) ( 1 – n ) C L A' N tP HL = --------------------KN VDD CONCORDIA VLSI DESIGN LAB VDD vo td2 1 1-n 0.5 vin td1 td2 23 Step Response Rise Delay tPLH and Rise Time tr VDD CL –2p tPLH = --------------------------------------- ----------------- + ln ( 3 + 4p ) KP VDD (1 + p ) (1 + p ) MP D Vin CL ( – 2)0.1 (1 + p) tr = --------------------------------------- ---------------------------- + ln (19 + 20p ) K PVDD ( 1 + p ) (1 + p ) Vo D G CL MN S CONCORDIA VLSI DESIGN LAB G VDD C L A' P tP LH = --------------------KP VDD 4C L A'P tr = --------------------KP VDD S (P= - 0.2) GND 24 Factors Influence Delay Inverter Delay,td = (tPHL+tPLH)/2 The following factors influence the delay of the inverter: • • • • • Load Capacitance Supply Voltage Transistor Sizes Junction Temperature Input Transition Time CONCORDIA VLSI DESIGN LAB 25 Delay as a function of VDD 28 Normalized Delay 24 20 16 12 8 4 0 1.00 2.00 3.00 4.00 5.00 VDD (V) CONCORDIA VLSI DESIGN LAB 26 Delay as a function of Transistor Size tPHL and tf decrease with the increase of W/L of the NMOS tPLH and tr decrease with the increase of W/L of the PMOS CONCORDIA VLSI DESIGN LAB 27 Temperature Effect Temperature ranges: commercial : 0 to700C industrial: -40 to 850C military: -55 to 1250C Calculation of the junction temperature tj= ta + ja X Pd Effect of temperature on mobility Delay and speed implications CONCORDIA VLSI DESIGN LAB 28 Effect of Input Transition Times The delay of the inverter increases with the increase of the input r Vin transition times r and f Vo tPHL = (tPHL) step + (r /6).(1-2p) tPLH = (tPLH) step + (f/6).(1+2n) CONCORDIA VLSI DESIGN LAB 29 Transistor Sizing Define = (W/L)p/(W/L)n CONCORDIA VLSI DESIGN LAB For Equal Fall and Rise Delay KN=KP = n/ p For Minimum Delay dtD/d = 0 opt = Sqrt (n/ p) 30 Power Dissipation in CMOS Two Components contribute to the power dissipation: » Static Power Dissipation – Leakage current – Sub-threshold current » Dynamic Power Dissipation – Short circuit power dissipation – Charging and discharging power dissipation CONCORDIA VLSI DESIGN LAB 31 Static Power Dissipation Leakage Current: • P-N junction reverse biased current: io= is(eqV/kT-1) • Typical value 0.1nA to 0.5nA @room temp. Vin • Total Power dissipation: Psl= i0.VDD VDD S G MP B D Vo D G B MN Sub-threshold Current • Relatively high in low threshold devices CONCORDIA VLSI DESIGN LAB S GND 32 Analysis of CMOS circuit power dissipation The power dissipation in a CMOS logic gate can be expressed as P = Pstatic + Pdynamic = (VDD · Ileakage) + (p · f · Edynamic) Where p is the switching probability or activity factor at the output node (i.e. the average number of output switching events per clock cycle). The dynamic energy consumed per output switching event is defined as Edynamic = i VDDdt DD 1 _ switching_ event CONCORDIA VLSI DESIGN LAB 33 Analysis of CMOS circuit power dissipation 2 2 Edynamic CLVDD 2CMVDD ESC 2 2 CloadVDD [Cdbp Cdbn 2(Cgdn Cgdp )]VDD ESC The first term —— the energy dissipation due to the Charging/discharging of the effective load capacitance CL. The second term —— the energy dissipation due to the input-tooutput coupling capacitance. A rising input results in a VDDVDD transition of the voltage across CM and so doubles the charge of CM. CL = Cload + Cdbp +Cdbn CM = Cgdn + Cgdp CONCORDIA VLSI DESIGN LAB 34 The MOSFET parasitic capacitances • distributed, • voltage-dependent, and • nonlinear. So their exact modeling is quite complex. Even ESC can be modeled, it is also difficult to calculate the Edynamic. On the other hand, if the short-circuit current iSC can be Modeled, the power-supply current iDD may be modeled with the same method. So there is a possibility to directly model iDD instead of iSC. CONCORDIA VLSI DESIGN LAB 35 Schematic of the Inverter CONCORDIA VLSI DESIGN LAB 36 CONCORDIA VLSI DESIGN LAB 37 Analysis of short-circuit current The short-circuit energy dissipation ESC is due to the railto-rail current when both the PMOS and NMOS devices are simultaneously on. ESC = ESC_C + ESC_n Where and CONCORDIA VLSI DESIGN LAB ESC _ c VDD ESC _ d VDD i dt i dt n v0 0 VDD p v0 VDD 0 38 Charging and discharging currents Discharging Inverter CONCORDIA VLSI DESIGN LAB Charging Inverter 39 Factors that affect the short-circuit current For a long-channel device, assuming that the inverter is symmetrical (n = p = and VTn = -VTp = VT) and with zero load capacitance, and input signal has equal rise and fall times (r = f = ), the average short-circuit current [Veendrick, 1994] is I mean 1 3 (VDD 2VT ) 12 VDD T From the above equation, some fundamental factors that affect short-circuit current are: W ( ) t L , VDD, VT, and T. ox CONCORDIA VLSI DESIGN LAB 40 Parameters affecting short cct current For a short-channel device, and VT are no longer constants, but affected by a large number of parameters (i.e. circuit conditions, hspice parameters and process parameters). CL also affects short-circuit current. Imean is a function of the following parameters (tox is processdependent): CL, , T (or /T), VDD, Wn,p, Ln,p (or Wn,p/ Ln,p ), tox, … The above argument is validated by the means of simulation in the case of discharging inverter, CONCORDIA VLSI DESIGN LAB 41 The effect of CL on Short CCt Current CONCORDIA VLSI DESIGN LAB 42 Effect of tr on short cct Current CONCORDIA VLSI DESIGN LAB 43 Effect of Wp on Short cct Current CONCORDIA VLSI DESIGN LAB 44 Effect of timestep setting on simulation results Tr (ps) 0 100 200 CONCORDIA VLSI DESIGN LAB Timestep (ps) 2 4 5 6 8 10 2 4 5 6 8 10 2 5 5 8 8 10 MaxStep (ps) 10 10 10 10 10 20 10 10 10 10 10 20 10 10 20 10 20 20 iMax (uA) 802.6 413.8 336.4 284.9 221 183 73.09 64.4 58.69 65.64 76.13 63.1 50.96 49.78 50.46 50.72 52.08 51.25 iaverage_inT/2 (uA) 1.258 1.264 1.24 1.234 1.245 1.231 1.202 1.213 1.21 1.208 1.207 1.217 1.311 1.295 1.313 1.311 1.311 1.311 45 Thank you ! CONCORDIA VLSI DESIGN LAB 46