VLSI Design
DC & Transient Response
EE 447 VLSI Design
4: DC and Transient Response
1
Outline
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DC Response
Logic Levels and Noise Margins
Transient Response
Delay Estimation
EE 447 VLSI Design
4: DC and Transient Response
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DC Response
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DC Response: Vout vs. Vin for a gate
Ex: Inverter
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When Vin = 0
->
Vout = VDD
When Vin = VDD ->
Vout = 0
In between, Vout depends on
Vin
transistor size and current
By KCL, must settle such that
Idsn = |Idsp|
We could solve equations
But graphical solution gives more insight
EE 447 VLSI Design
4: DC and Transient Response
VDD
Idsp
Vout
Idsn
3
Transistor Operation
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Current depends on region of transistor
behavior
For what Vin and Vout are nMOS and pMOS in
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Cutoff?
Linear?
Saturation?
EE 447 VLSI Design
4: DC and Transient Response
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I-V Characteristics

Make pMOS is wider than nMOS such that bn = bp
Vgsn5
Vgsn4
Idsn
Vgsn3
-Vdsp
Vgsp1
Vgsp2
-VDD
0
VDD
Vdsn
Vgsp3
Vgsp4
Vgsn2
Vgsn1
-Idsp
Vgsp5
EE 447 VLSI Design
4: DC and Transient Response
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Current vs. Vout, Vin
Idsn, |Idsp|
Vin0
Vin5
Vin1
Vin4
Vin2
Vin3
Vin3
Vin4
Vin2
Vin1
Vout
EE 447 VLSI Design
4: DC and Transient Response
VDD
6
Load Line Analysis

For a given Vin:
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Idsn, |Idsp|
Plot Idsn, Idsp vs. Vout
Vout must be where |currents| are equal in
Vin0
Vin5
Vin1
Vin4
VDD
Vin2
Vin3
Idsp
Vin3
Vin4
Vin2
Vin1
Idsn
Vin
Vout
Vout
VDD
EE 447 VLSI Design
4: DC and Transient Response
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Load Line Analysis
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Vin = 0
Vin0
Idsn, |Idsp|
Vin0
Vout
EE 447 VLSI Design
4: DC and Transient Response
VDD
8
Load Line Analysis
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Vin = 0.2VDD
Idsn, |Idsp|
Vin1
Vin1
Vout
EE 447 VLSI Design
4: DC and Transient Response
VDD
9
Load Line Analysis

Vin = 0.4VDD
Idsn, |Idsp|
Vin2
Vin2
Vout
EE 447 VLSI Design
4: DC and Transient Response
VDD
10
Load Line Analysis
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Vin = 0.6VDD
Idsn, |Idsp|
Vin3
Vin3
Vout
EE 447 VLSI Design
4: DC and Transient Response
VDD
11
Load Line Analysis

Vin = 0.8VDD
Vin4
Idsn, |Idsp|
Vin4
Vout
EE 447 VLSI Design
4: DC and Transient Response
VDD
12
Load Line Analysis

Vin = VDD
Vin0
Idsn, |Idsp|
Vin5
Vin1
Vin2
Vin3
Vin4
Vout
EE 447 VLSI Design
4: DC and Transient Response
VDD
13
Load Line Summary
Idsn, |Idsp|
Vin0
Vin5
Vin1
Vin4
Vin2
Vin3
Vin3
Vin4
Vin2
Vin1
Vout
EE 447 VLSI Design
4: DC and Transient Response
VDD
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DC Transfer Curve

Transcribe points onto Vin vs. Vout plot
Vin0
Vin5
Vin1
Vin4
Vin2
Vin3
Vin3
Vin4
Vin2
Vin1
Vout
VDD
VDD
A
B
Vout
C
D
0
Vtn
VDD/2
E
VDD+Vtp
VDD
Vin
EE 447 VLSI Design
4: DC and Transient Response
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Operating Regions

Revisit transistor operating regions
Region
nMOS
pMOS
A
Cutoff
Linear
B
Saturation
Linear
C
Saturation
Saturation
D
Linear
Saturation
E
Linear
Cutoff
VDD
A
B
Vout
C
D
0
Vtn
EE 447 VLSI Design
4: DC and Transient Response
VDD/2
E
VDD+Vtp
VDD
Vin
16
Beta Ratio
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If bp / bn  1, switching point will move from VDD/2
Called skewed gate
Other gates: collapse into equivalent inverter
VDD
bp
 10
bn
Vout
bp
 0.1
bn
2
1
0.5
0
VinDesign
EE 447 VLSI
VDD
4: DC and Transient Response
17
Noise Margins

How much noise can a gate input see before it does
not recognize the input?
Output Characteristics
Logical High
Output Range
VDD
Input Characteristics
Logical High
Input Range
VOH
NMH
VIH
VIL
Indeterminate
Region
NML
Logical Low
Output Range
VOL
Logical Low
Input Range
GND
EE 447 VLSI Design
4: DC and Transient Response
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Logic Levels
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To maximize noise margins, select logic levels at

unity gain point of DC transfer characteristic
Vout
Unity Gain Points
Slope = -1
VDD
VOH
b p/b n > 1
Vin
VOL
Vout
Vin
0
Vtn
VIL VIH VDD- VDD
|Vtp|
EE 447 VLSI Design
4: DC and Transient Response
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Transient Response
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DC analysis tells us Vout if Vin is constant
Transient analysis tells us Vout(t) if Vin(t) changes
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Requires solving differential equations
Input is usually considered to be a step or ramp
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From 0 to VDD or vice versa
EE 447 VLSI Design
4: DC and Transient Response
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Inverter Step Response
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Ex: find step response of inverter driving load cap
Vin (t ) 
Vout (t  t0 ) 
dVout (t )

dt
Vin(t)
Vout(t)
Cload
Idsn(t)
EE 447 VLSI Design
4: DC and Transient Response
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Inverter Step Response

Ex: find step response of inverter driving load cap
Vin (t )  u(t  t0 )VDD
Vout (t  t0 ) 
dVout (t )

dt
Vin(t)
Vout(t)
Cload
Idsn(t)
EE 447 VLSI Design
4: DC and Transient Response
22
Inverter Step Response

Ex: find step response of inverter driving load cap
Vin (t )  u(t  t0 )VDD
Vout (t  t0 )  VDD
Vin(t)
dVout (t )

dt
Vout(t)
Cload
Idsn(t)
EE 447 VLSI Design
4: DC and Transient Response
23
Inverter Step Response

Ex: find step response of inverter driving load cap
Vin (t )  u (t  t0 )VDD
Vout (t  t0 )  VDD
Vin(t)
dVout (t )
I dsn (t )

dt
Cload


I dsn (t )  


Vout
Vout
Vout(t)
Cload
Idsn(t)
t  t0
 VDD  Vt
 VDD  Vt
EE 447 VLSI Design
4: DC and Transient Response
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Inverter Step Response

Ex: find step response of inverter driving load cap
Vin (t )  u (t  t0 )VDD
Vout (t  t0 )  VDD
Vin(t)
dVout (t )
I dsn (t )

dt
Cload

Vout(t)
Cload
Idsn(t)
0
t  t0


2
b
I dsn (t )  
V

V
Vout  VDD  Vt


DD
2

V (t )
 b VDD  Vt  out 2 Vout (t ) Vout  VDD  Vt

 
EE 447 VLSI Design
4: DC and Transient Response
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Inverter Step Response

Ex: find step response of inverter driving load cap
Vin (t )  u (t  t0 )VDD
Vin(t)
Vout (t  t0 )  VDD
dVout (t )
I dsn (t )

dt
Cload

0


2
b
I dsn (t )  
V

V


DD
2

V (t )
 b VDD  Vt  out 2
 
Vout(t)
Cload
Idsn(t)
Vin(t)
t  t0
Vout  VDD  Vt
 V (t ) V  V  V
 out
out
DD
t

EE 447 VLSI Design
4: DC and Transient Response
Vout(t)
t0
t
26
Delay Definitions
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tpdr:
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tpdf:
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tpd:
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tr:
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tf: fall time
EE 447 VLSI Design
4: DC and Transient Response
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Delay Definitions
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tpdr: rising propagation delay
 From input to rising output crossing VDD/2
tpdf: falling propagation delay
 From input to falling output crossing VDD/2
tpd: average propagation delay
 tpd = (tpdr + tpdf )/2
tr: rise time
 From output crossing 0.2 VDD to 0.8 VDD
tf: fall time
 From output crossing 0.8 VDD to 0.2 VDD
EE 447 VLSI Design
4: DC and Transient Response
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Delay Definitions
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tcdr: rising contamination delay
 From input to rising output crossing VDD/2
tcdf: falling contamination delay
 From input to falling output crossing VDD/2
tcd: average contamination delay
 tpd = (tcdr + tcdf )/2
EE 447 VLSI Design
4: DC and Transient Response
29
Simulated Inverter Delay
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Solving differential equations by hand is too hard
SPICE simulator solves the equations numerically
 Uses more accurate I-V models too!
But simulations take time to write
2.0
1.5
1.0
(V)
Vin
tpdf = 66ps
tpdr = 83ps
Vout
0.5
0.0
0.0
200p
400p
600p
800p
1n
t(s)
EE 447 VLSI Design
4: DC and Transient Response
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Delay Estimation
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We would like to be able to easily estimate delay
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The step response usually looks like a 1st order RC
response with a decaying exponential.
Use RC delay models to estimate delay
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Not as accurate as simulation
C = total capacitance on output node
Use effective resistance R
So that tpd = RC
Characterize transistors by finding their effective R
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Depends on average current as gate switches
EE 447 VLSI Design
4: DC and Transient Response
31
RC Delay Models
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Use equivalent circuits for MOS transistors
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Ideal switch + capacitance and ON resistance
Unit nMOS has resistance R, capacitance C
Unit pMOS has resistance 2R, capacitance C
Capacitance proportional to width
Resistance inversely proportional to width
d
g
d
k
s
s
kC
R/k
kC
2R/k
g
g
kC
kC
d
k
s
s
kC
g
kC
d
EE 447 VLSI Design
4: DC and Transient Response
32
Example: 3-input NAND

A 3-input NAND with transistor widths chosen to
achieve effective rise and fall resistances equal to a
unit inverter (R).
2
2
2
3
3
3
EE 447 VLSI Design
4: DC and Transient Response
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3-input NAND Caps

Annotate the 3-input NAND gate with gate and
diffusion capacitance.
2C
2
2C
2C
2C
2
2C
2C
2
2C
3C
3C
3C
2C
2C
3
3
3
3C
3C
3C
3C
EE 447 VLSI Design
4: DC and Transient Response
34
3-input NAND Caps

Annotate the 3-input NAND gate with gate and
diffusion capacitance.
2
2
2
3
5C
5C
5C
3
3
EE 447 VLSI Design
4: DC and Transient Response
9C
3C
3C
35
Elmore Delay
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ON transistors look like resistors
Pullup or pulldown network modeled as RC ladder
Elmore delay of RC ladder
t pd 

Ri to  sourceCi
nodes i
 R1C1   R1  R2  C2  ...   R1  R2  ...  RN  C N
R1
R2
R3
C1
C2
RN
C3
EE 447 VLSI Design
4: DC and Transient Response
CN
36
Example: 2-input NAND

Estimate worst-case rising and falling delay of 2-input
NAND driving h identical gates.
2
2
A
2
B
2x
Y
h copies
EE 447 VLSI Design
4: DC and Transient Response
37
Example: 2-input NAND

Estimate rising and falling propagation delays of a 2input NAND driving h identical gates.
2
2
A
2
B
2x
Y
4hC
6C
2C
EE 447 VLSI Design
4: DC and Transient Response
h copies
38
Example: 2-input NAND

Estimate rising and falling propagation delays of a 2input NAND driving h identical gates.
2
2
A
2
B
2x
R
Y
(6+4h)C
Y
4hC
6C
2C
h copies
t pdr 
EE 447 VLSI Design
4: DC and Transient Response
39
Example: 2-input NAND

Estimate rising and falling propagation delays of a 2input NAND driving h identical gates.
2
2
A
2
B
2x
R
Y
(6+4h)C
Y
4hC
6C
2C
h copies
t pdr   6  4h  RC
EE 447 VLSI Design
4: DC and Transient Response
40
Example: 2-input NAND

Estimate rising and falling propagation delays of a 2input NAND driving h identical gates.
2
2
A
2
B
2x
Y
4hC
6C
h copies
2C
EE 447 VLSI Design
4: DC and Transient Response
41
Example: 2-input NAND
Estimate rising and falling propagation delays of a 2input NAND driving h identical gates.

2
2
A
2
B
2x
x
R/2
R/2
2C
Y
(6+4h)C
Y
4hC
6C
h copies
2C
t pdf 
EE 447 VLSI Design
4: DC and Transient Response
42
Example: 2-input NAND
Estimate rising and falling propagation delays of a 2input NAND driving h identical gates.

2
2
A
2
B
2x
x
R/2
R/2
2C
Y
(6+4h)C
Y
4hC
6C
h copies
2C
t pdf   2C   R2    6  4h  C   R2  R2 
  7  4h  RC
EE 447 VLSI Design
4: DC and Transient Response
43
Delay Components

Delay has two parts

Parasitic delay



6 or 7 RC
Independent of load
Effort delay


4h RC
Proportional to load capacitance
EE 447 VLSI Design
4: DC and Transient Response
44
Contamination Delay


Best-case (contamination) delay can be substantially
less than propagation delay.
Ex: If both inputs fall simultaneously
2
2
A
2
B
2x
Y
4hC
6C
2C
tcdr   3  2h  RC
R R
Y
(6+4h)C
EE 447 VLSI Design
4: DC and Transient Response
45
Diffusion Capacitance



we assumed contacted diffusion on every s / d.
Good layout minimizes diffusion area
Ex: NAND3 layout shares one diffusion contact


Reduces output capacitance by 2C
Merged uncontacted diffusion might help too
2C
2C
Shared
Contacted
Diffusion
Isolated
Contacted
Diffusion
Merged
Uncontacted
Diffusion
2
2
2
3
3
3C 3C 3C
EE 447 VLSI Design
4: DC and Transient Response
3
7C
3C
3C
46
Layout Comparison

Which layout is better?
VDD
A
VDD
B
Y
GND
A
B
Y
GND
EE 447 VLSI Design
4: DC and Transient Response
47