CS1104: Computer Organisation
http://www.comp.nus.edu.sg/~cs1104
School of Computing
National University of Singapore
PII Lecture 5: Basic MIPS
Assembly Language
 Basic MIPS R2000 ISA
 MIPS Assembly Language





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Arithmetic operations
Load/store instructions for memory data
Control flow
Constant handling
Branch addressing
Basic MIPS Assembly Language
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PII Lecture 5: Basic MIPS
Assembly Language
 Reading: Chapter 3 of Patterson’s book:
 3.1 – 3.5, 3.8, 3.11, 3.13, 3.14.
 Optional reading: 3:10, 3.12.
 PCSpim (MIPS R2000 simulator)
 ftp://ftp.cs.wisc.edu/pub/spim/pcspim.exe or
 http://www.cs.wisc.edu/~larus/spim.html
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MIPS R2000 ISA
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MIPS R2000 ISA
 The MIPS instruction set is typical of RISC


(Reduced Instruction Set Computers)
architectures (MIPS, PowerPC, SPACRC,
ARM, etc.)
MIPS R2000 is a load-store register
architecture.
MIPS R2000 Assembly Language:
 32 registers, each 32-bit (4-byte) long.
 Each word contains 32 bits (4 bytes).
 Memory addresses are 32-bit long.
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MIPS Operands: Registers and Memory
MIPS operands
Name
Examples
Comments
32 registers $s0-$s7, $t0-$t9, $zero, $a0- Fast locations for data. In MIPS,
230 memory
words
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$a3, $v0-$v1, $gp, $fp, $sp,
$ra, $at
data must be in registers to perform
arithmetic.
Mem[0], Mem[4], …,
Mem[4294967292].
Accessed only by data transfer
instructions. MIPS uses byte
addresses, so sequential words
differ by 4. Memory holds data
structures, such as arrays, and
spilled registers, such as those
saved on procedure calls.
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MIPS Operands: Registers and Memory
(2)
Name
Register
number
Usage
Name
Register
number
Usage
$zero
0
Constant value 0
$t8-$t9
24-25
$v0-$v1
2-3
Values for results
and expression
evaluation
More
temporaries
$gp
28
Global pointer
$sp
29
Stack pointer
$a0-$a3
4-7
Arguments
$fp
30
Frame pointer
$t0-$t7
8-15
Temporaries
$ra
31
Return address
$s0-$s7
16-23
Saved
$at (register 1) is reserved for the assembler.
$k0-$k1 (registers 26-27) are reserved for the operation system.
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MIPS: Addressing Modes
 Mainly 5 types of addressing modes:





Register
Immediate
Displacement (with a base register and a constant)
PC-relative
Pseudo-direct (with 26 bits concatenated with PC upper bits
for jump address)
 Computation instructions operate only on values in

registers or immediate values embedded in the
instructions.
Data in memory can be accessed through one
memory addressing mode, C(Rx), where C is an
immediate constant and Rx is a register.
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MIPS: Addressing Modes (2)
Register (direct)
op
rs
rt
rd
register
Immediate
op
rs
rt
immed
Displacement
op
rs
rt
immed
register
PC-relative
op
rs
rt
PC
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Memory
+
immed
Memory
+
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MIPS: Instruction Format




Fixed-length instruction format.
All instructions are 32-bit long.
Very structured.
Only three instruction formats: R, I, J.
R-format
6 bits
op
5 bits
rs
5 bits
rt
I-format
op
rs
rt
J-format
op
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5 bits
rd
5 bits
shamt
6 bits
funct
16-bit immed/address
26-bit address
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MIPS: Instruction Format (2)
 R-format: Used for instructions with 3 register

operands.
Arithmetic instructions:
add $t0, $s1, $s2 # $t0  $s1 + $s2
Recall that $t0 is register 8, $s1 is register 17 and $s2 is register 18.
000000
10001
10010
01000
00000
100000
5 bits
rs
5 bits
rt
5 bits
rd
5 bits
shamt
6 bits
funct
R-format
6 bits
op
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MIPS: Instruction Format (3)
 I-format: For data transfer instructions.
 Examples: load word (lw) and store word (sw).
 One register operand and one memory address operand
(specified by a constant and a register)
lw $t0, 40($s2)
# load Mem[$s2+40] to $t0
Recall that $t0 is register 8 and $s2 is register 18.
100011
10010
01000
0000000000101000
5 bits
rs
5 bits
rt
16 bits
16-bit immed/address
I-format
6 bits
op
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MIPS: Opcodes
 Learn by examples.
 Focus mainly on those simple ones, such as:
load
store
add
subtract
move register-register
and
shift
compare equal, compare not equal
branch
jump
call
return
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Basic MIPS Assembly Language
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Assembly vs. Machine Language
 Assembly provides convenient symbolic
representation.
 Much easier than writing down binary numbers (“add”
instead of 000000).
 Destination first.
 Example: Add A, B, C # A  B + C
 Machine language is the underlying reality


 Destination needs not be specified first.
 Example: op rs rt rd
Assembly can provide pseudo-instructions
 Example: “move $t0, $t1” exists only in assembly,
implemented using “add $t0, $t1, $zero”.
When considering performance, count real
instructions.
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Arithmetic Instructions
 All instructions have 3 operands.
 Operand order is fixed.
 Example:
 C code: A = B + C;
 MIPS code: add $s0, $s1, $s2
 Compiler associates registers with variables in
program.
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Arithmetic Instructions (2)
 Design principle: simplicity favours regularity.
 This complicates some things…
 C code: Variable number of operands
A = B + C + D;
E = F – A;
 MIPS code:
add $t0, $s1, $s2
add $s0, $t0, $s3
sub $s4, $s5, $s0
 MIPS operands must be registers.
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Load/Store Instructions
 Only load and store instructions can access memory

data.
Example: Each array element occupies a word.
 C code:
A[7] = h + A[10];
 MIPS code:
lw $t0, 40($s3)
add $t0, $s2, $t0
sw $t0, 28($s3)
 Each array element occupies a word (4 bytes).
 $s3 contains the base address (address of first element) of
array A.
 Remember arithmetic operands (for add) are
registers, not memory!
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Load/Store Instructions (2)
 Besides the load word (lw) and store word (sw)
instructions, there are also the load byte (lb) and
store byte (sb) instructions.
 Similar in format:
lb
sb
$t1, 12($s3)
$t2, 13($s3)
 Similar in working except that one byte, instead of
one word, is loaded or stored.
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Load/Store Instructions (3)
 MIPS disallows loading/storing a word that crosses
the word boundary. Use the unaligned load word
(ulw) and unaligned store word (usw) instructions
instead. These are pseudo-instructions.
 There are other instructions such as
 lh and sh: load halfword and store halfword
 lwl, lwr, swl, swr: load word left, load word right, store word
left, store word right.
 And others.
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First Example
 Figure out the code.
swap(int v[], int k)
{ int temp;
temp = v[k]
v[k] = v[k+1];
v[k+1] = temp;
}
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$5 contains k.
Base address
of array v in $4
$2 contains 4*k
(because each word
contains 4 bytes)
swap:
muli $2, $5, 4
add $2, $4, $2
lw $15, 0($2)
lw $16, 4($2)
sw $16, 0($2)
sw $15, 4($2)
jr $31
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Conditional Control
 Decision making instructions
 Alter the control flow.
 Changing the next instruction to be executed.
 MIPS conditional branch instructions:
bne $t0, $t1, Label
beq $t0, $t1, Label
 Example: if (i == j) h = i + j;
bne $s0, $s1, Label
add $s3, $s0, $s1
Label: …
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Unconditional Control
 MIPS unconditional branch instruction: j (jump)
j Label
 Example:
if (i != j)
h = i + j;
else
h = i – j;
L1:
L2:
beq $s4, $s5, L1
add $s3, $s4, $s5
j
L2
sub $s3, $s4, $s5
…
 Can you write the MIPS code for a simple for loop?
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So far we’ve learned:
 Arithmetic on registers only
 Loading/storing words but addressing bytes.
Instruction
add $s1, $s2, $s3
sub $s1, $s2, $s3
lw $s1, 100($s2)
sw $s1, 100($s2)
bne $s1, $s2, L
beq $s1, $s2, L
j
L
Meaning
$s1 = $s2 + $s3
$s1 = $s2 – $s3
$s1 = Mem[$s2+100]
Mem[$s2+100] = $s1
next instr. at L if $s1 ≠ $s2
next instr. at L if $s1 = $s2
next instr. at L
R-format
6 bits
op
5 bits
rs
5 bits
rt
I-format
op
rs
rt
J-format
op
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5 bits
rd
5 bits
shamt
6 bits
funct
16-bit immed/address
26-bit address
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More About Control Flow
 We have beq and bne, what about branch-if-less
than? We do not have a blt instruction.
Use slt (set on less than).
slt $t0, $s1, $s2
=
if $s1 < $s2 then
$t0 = 1
else
$t0 = 0
 To build a “blt $s1, $s2, Label” instruction:
slt $t0, $s1, $s2
bne $zero, $t0, Label
 We can now build general control structures.
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Constants
 Small constants are used quite frequently (50% of
operands).
A = A + 5;
B = B + 1;
C = C – 18;
 Solution:
 Put ‘typical constants’ in memory and load them.
 Create hard-wired registers (like $zero) for constants like
one.
 Embed them into the instruction code.
 For MIPS instructions, we use the ‘immediate operand’
version:
addi $29, $29, 4
slti $8, $18, 10
andi $29, $29, 6
ori
$29, $29, 4
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Larger Constants
 Bit-wise operations: or, ori, and, andi.
 Examples:
1010 or 1001  1011
1010 and 1001  1000
1010
or
1001
1010
and
1011
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1001
1000
27
Larger Constants (2)
 How to load a 32-bit constant into a register.

 Example: 1010101010101010 1111000011110000?
Need to use two instructions: “load upper immediate”
(lui) and “or immediate” (ori):
lui
$t0, 1010101010101010
1010101010101010
0000000000000000
Lower-order bits
filled with zeros.
 Then to get the lower-order bits correct:
ori $t0, $t0, 1111000011110000
ori
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1010101010101010
0000000000000000
0000000000000000
1111000011110000
1010101010101010
1111000011110000
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Larger Constants (3)
 The above are just illustration of the concept. In the
actual instruction, the value is entered as a decimal
value or an hexadecimal value (prefixed by 0x).
 For example
lui $t0, 43690
# 4369010 = 10101010101010102
lui $t0, 0xAAAA
# AAAA16 = 10101010101010102
or
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Addresses in Branches and Jumps
 Instructions:
bne $t1, $t2, Label
beq $t1, $t2, Label
j
Label
# next instr. at Label if $t1 ≠ $t2
# next instr. at Label if $t1 = $t2
# next instr. at Label
 Formats:
I-format
op
J-format
op
rs
rt
16-bit immed/address
26-bit address
 How is the branch address formed?
 How does this differ from the address calculation in
Load/Store instructions?
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Addresses in Conditional Branches
 Examples:
bne $t1, $t2, Label
beq $t1, $t2, Label
# next instr. at Label if $t1 ≠ $t2
# next instr. at Label if $t1 = $t2
 Formats:
I-format
op
rs
rt
16-bit immed/address
 Specify a register (like lw and sw) and add it to the
specified address
 Use Instruction Address Register, or PC (program counter)
 Most branches are local (principle of locality)
 Address = PC + shift_left_2_bits(16-bit address)
 Why do we shift the specified 16-bit address by 2 bits to the
left?
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Addresses in Unconditional Jumps
 Example:
j
Label
# next instr. at Label
 Formats:
J-format
op
26-bit address
 Jump instructions just use high-order bits of PC
 Address = bits 31-28 of PC + shift_left_2_bits(26-bit address)
 Address boundaries of 256 MB.
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MIPS Instructions: Summary
add
MIPS assembly language
Example
Meaning
add $s1, $s2, $s3
$s1 = $s2 + $s3
Three operands; data in registers
subtract
sub $s1, $s2, $s3
$s1 = $s2 - $s3
Three operands; data in registers
addi $s1, $s2, 100
lw $s1, 100($s2)
sw $s1, 100($s2)
lb $s1, 100($s2)
sb $s1, 100($s2)
lui $s1, 100
$s1 = $s2 + 100
Used to add constants
$s1 = Memory[$s2 + 100]Word from memory to register
Memory[$s2 + 100] = $s1 Word from register to memory
$s1 = Memory[$s2 + 100]Byte from memory to register
Memory[$s2 + 100] = $s1 Byte from register to memory
16
Loads constant in upper 16 bits
$s1 = 100 * 2
beq
$s1, $s2, 25
if ($s1 == $s2) go to
PC + 4 + 100
Equal test; PC-relative branch
branch on not equal bne
$s1, $s2, 25
if ($s1 != $s2) go to
PC + 4 + 100
Not equal test; PC-relative
$s1, $s2, $s3
if ($s2 < $s3) $s1 = 1;
else $s1 = 0
Compare less than; for beq, bne
Category
Arithmetic
Instruction
add immediate
load w ord
store w ord
Data transfer load byte
store byte
load upper
immediate
branch on equal
Conditional
branch
Unconditional jump
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set on less than
slt
set less than
immediate
slti
jump
jump register
jump and link
j
jr
jal
$s1, $s2, 100 if ($s2 < 100) $s1 = 1;
Comments
Compare less than constant
else $s1 = 0
2500
$ra
2500
go to 10000
Jump to target address
go to $ra
For sw itch, procedure return
$ra = PC + 4; go to 10000 For procedure call
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Array and Loop
 Typical example of accessing array elements in a
loop:
Label:
Initialization for result
variables, loop counter, and
array pointers.
Work by:
1. Calculating address
2. Load data
3. Perform task
Update loop counter and
array pointers.
Compare and branch.
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Array and Loop: Example
 Given a word array A with 40 elements A[0], A[1], …,
A[39], with the starting array address stored in $t0.
Count the number of array elements with value zero,
and store the result in $t8.
Answer 1:
addi $t8, $zero, 0
/* initialize counter to zero
addi $t1, $zero, 0
/* $t1 as index ptr, init. to pt. 1st element
L1: add $t2, $t0, $t1
/* address of current element
lw
$t3, 0($t2)
/* load current element from memory
bne $zero, $t3, L2 /* check if data is zero, if not, skip update
addi $t8, $t8, 1
/* increment counter
L2: addi $t1, $t1, 4
/* point to next element
(How to compare and loop back?)
bne $t1, 160, L1 ??? No immediate compare operand!
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Array and Loop: Example (cont’d)
Answer 2:
addi
addi
L1: add
lw
bne
addi
L2: addi
bne
$t8, $zero, 0
$t1, $zero, 156
$t2, $t0, $t1
$t3, 0($t2)
$zero, $t3, L2
$t8, $t8, 1
$t1, $t1, –4
$t1, $zero, L1
/* initialize counter to zero
/* $t1 as index ptr, init. to pt. last element
/* address of current element
/* load current element from memory
/* check if data is zero, if not, skip update
/* increment counter
/* point to previous element
(How about the iteration for the first element?)
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Array and Loop: Example (cont’d)
Answer 3:
addi $t8, $zero, 0
/* initialize counter to zero
addi $t1, $zero, 160 /* $t1 as index ptr, init. to pt. pass
/* last element
L1: add $t2, $t0, $t1
/* address of current element
lw
$t3, –4($t2)
/* load preceding element from memory
bne $zero, $t3, L2 /* check if data is zero, if not, skip update
addi $t8, $t8, 1
/* increment counter
L2: addi $t1, $t1, –4
/* point to previous element
bne $t1, $zero, L1
(Is this correct now?)
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Other Issues
 Things we are not going to cover:






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Support for procedures
Linkers, loaders, memory layout
Stacks, frames, recursion
Manipulating strings and pointers
Interrupts and exceptions
System calls and conventions
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Concepts of Focus
 Basic MIPS ISA
 Basic assembly language programming
 Arithmetic: among registers only
 Memory accesses: load/store only
 Control flow: for loop, if-then-else.
 Handling of constants and branch address data.
 Practice is the key to master the techniques
 Memorization will not help you!
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MIPS R2000 Simulator
 Try out PCSpim (MIPS R2000 simulator)
 ftp://ftp.cs.wisc.edu/pub/spim/pcspim.exe or
 http://www.cs.wisc.edu/~larus/spim.html
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Sample Question (1)
1. Which of the following statements is/are true?
a) In MIPS architecture, the smallest unit of memory to have
an unique memory address is a word.
b) Big and little endians refer to the two dimensions of the
array data stored in memory.
c) Mis-alignment of data along non-word boundary will suffer
performance loss, but not the program accuracy. [Answer]
d) (a) and (c).
e) None of the above.
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Sample Question (2)
2. Which of the following data can be a valid operand
for a MIPS arithmetic instruction? Assume that $t4
is a register in MIPS.
a) 4000000000
b) 64($t4)
c) $t4(0)
d) (b) and (c)
e) None of the above. [Answer]
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Sample Question (3)
3. Which of the following is true for the MIPS
instruction format?
a) Conditional branch instructions can be in J-format.
b) MIPS has variable-length instruction format.
c) All MIPS arithmetic instructions are in R-format only.
d) lw/sw instructions are in I-format only. [Answer]
e) None of the above.
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Sample Question (4)
4.
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Which of the following data can be a valid
destination operand for a MIPS lw instruction?
Assume that $s0 is a register in MIPS.
a)
$s0(32)
b)
100
c)
100000000
d)
32($s0)
e)
None of the above. [Answer]
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Sample Question (5)
5.
In the MIPS architecture, which of the following is
false for the data in memory?
a)
Data in memory can be viewed as a single-dimension
array, with the memory address as an index into the array.
b)
Data in memory is byte-addressing (i.e. each byte has an
unique memory address).
[Answer] c)
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Data in memory is always aligned with the word boundary.
d)
Data in memory can be accessed directly by a subset of
the MIPS instructions only.
e)
None of the above.
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Sample Question (6)
6.
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Under the addressing modes of the MIPS
architecture, which of the following is true?
a)
There is no data memory READ for an operand under the
“immediate” addressing mode. [Answer]
b)
Two instructions are always required to load 32-bit data
from the memory into a register: “lui” to load the upper 16
bits and then “ori” to put the lower 16 bits into the register.
c)
The “register” addressing mode can be used to load a
datum from the memory into a register.
d)
The “displacement” addressing mode can be used to
specify an operand in a MIPS arithmetic instruction.
e)
None of the above.
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Sample Question (7)
7.
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Given a word array of data A[0], A[1], A[2], …, A[10]
in memory, with the starting address stored in
register $t4, element A[6] can be loaded into a
register $t5 using the following instruction:
a)
lw $t5, A[6]
b)
lw $t5, $t4[6]
c)
lw $t5, 6($t4)
d)
lw $t5, $t4[24]
e)
None of the above. [Answer]
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Sample Question (8)
8.
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Which of the following data is/are valid source
operand(s) for the MIPS lw instruction?
a)
100
b)
$s0
c)
32($s2) [Answer]
d)
(a) and (c)
e)
None of the above.
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Sample Question (9)
9.
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Which of the following data is not a valid basic
MIPS instruction?
a)
add $t0, $zero, $zero
b)
addi $t0, $t0, –1
c)
lw $t0, 8096($t1)
d)
beqi $t0, 4, label [Answer]
e)
None of the above.
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Sample Question (10)
10. Given the following MIPS instruction sequence:
addi
add
addi
Loop1: addi
subi
beq
i.
$t1, $zero, 10
$t1, $t1, $t1
$t2, $zero, 10
$t2, $t2, 10
$t1, $t1, 1
$t1, $zero, Loop1
How many instructions are executed?
(a) 6 (b) 30 (c) 33
[Ans]
ii.
(d) 36
(e) None of the above
What is the final value in $t2?
(a) 10 (b) 20 (c) 300 (d) 310 (e) None of the above
[Ans]
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Basic MIPS Assembly Language
50
Sample Question (11)
11. Given the following MIPS instruction sequence:
add $t0, $zero, $zero
add $t1, $t0, $t0
addi $t2, $t1, 4
Loop1: add $t1, $t1, $t0
addi $t0, $t0, 1
bne $t2, $t0, Loop1
Assume that CPIs for add and addi are 1, and bne is 4.
i.
What is the final value in $t1?
(a) 10
ii.
(b) 0
(c) 4
(d) 6
[Ans]
(e) None of the above
What is the overall CPI for the sequence?
(a) 2.5 (b) 1.5 (c) 1.8 (d) 2.0 (e) None of the above
[Ans]
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Basic MIPS Assembly Language
51
Sample Question (12)
12. Given a word array of elements in memory with the
starting address stored in $t1, the following MIPS
instruction sequence is executed:
add
add
addi
Loop1: add
ulw
add
addi
beq
i.
How many instructions are executed?
(a) 5
CS1104-P2-5
$t2, $zero, $zero
$t3, $t2, $t2
$t4, $t3, 10
$t5, $t1, $t2
$t6, 0($t5)
$t3, $t3, $t6
$t2, $t2, 1
$t4, $t2, Loop1
(b) 8 (c) 50
[Ans]
(d) 53 (e) None of the above
Basic MIPS Assembly Language
52
Sample Question (12) (cont’d)
ii.
How many unique bytes of memory (excluding
registers) are read?
(a) 10
(b) 13
(c) 14 (d) 40 (e) None of the above
[Ans]
iii. How many unique bytes of memory (excluding
registers) are modified?
(a) 10
CS1104-P2-5
(b) 13
(c) 14 (d) 40 (e) None of the above
[Ans]
Basic MIPS Assembly Language
53
Sample Question (13)
13. Given a word array of elements in memory with the
starting address stored in $t0, the following MIPS
instruction sequence is executed:
addi
add
Loop1: ulw
add
addi
bne
i.
How many instructions are executed?
(a) 6
CS1104-P2-5
$t1, $t0, 10
$t2, $zero, $zero
$t3, 0($t1)
$t2, $t2, $t3
$t1, $t1, –1
$t1, $t0, Loop1
(b) 8
(c) 41
(d) 42 (e) None of the above
[Ans]
Basic MIPS Assembly Language
54
Sample Question (13) (cont’d)
ii.
How many times is the “bne” instruction
executed?
(a) 1
(b) 8
(c) 9
(d) 10 (e) None of the above
[Ans]
iii. How many times does the “bne” instruction
actually branch to the label Loop1?
(a) 1
(b) 8
(c) 9
[Ans]
(d) 10 (e) None of the above
iv. How many unique bytes of memory (excluding
registers) are read?
(a) 10
CS1104-P2-5
(b) 13 (c) 14 (d) 40 (e) None of the above
[Ans]
Basic MIPS Assembly Language
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Sample Question (14)
14. State whether each of the following statements is
true or false.
[False] a)
When the size (number of bits) of a memory datum is
increased, more address bits are required to access it.
[False] b)
Each register in MIPS has an unique memory address,
which is 32 bits.
[False] c)
It is possible to access a datum in memory through the
“register” addressing mode.
[True] d)
CS1104-P2-5
It is possible to embed a constant operand inside a MIPS
instruction.
Basic MIPS Assembly Language
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Sample Question (15)
15. State whether each of the following statements is
true or false.
[False] a)
[True] b)
[False] c)
CS1104-P2-5
The order of instruction decode process is: Format
identification  Opcode determination  Operand fetch
 Addressing mode determination.
Given the starting address of a word array A to be 256, the
datum A[0] can be loaded into a MIPS register using one
single instruction (without any registers initialized).
The absolute target address of a conditional branch
instruction is encoded in the branch instruction.
Basic MIPS Assembly Language
57
Sample Question (16)
16. State whether each of the following statements is
true or false.
[True] a)
There is no relationship between the size (number of bits)
of a memory datum and the size of its address.
[True] b)
Non-word boundary alignment of data in memory will not
cause program execution errors.
[False] c)
Arithmetic operations in MIPS always have three
operands, each of which can be register, constant, or
memory address.
[False] d)
To increment an array data A[k] by one, the MIPS
instruction is: addi A[k], 1, A[k]
CS1104-P2-5
Basic MIPS Assembly Language
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Sample Question (17)
17. State whether each of the following statements is
true or false.
[False] a)
Before a datum is loaded from memory, its exact address
needs to be stored in a register first.
[False] b)
Decode unit identifies the instruction format (R, I or J) by
finding how many registers are used by an instruction.
[False] c)
Conditional branch and unconditional jump instructions
have the same range of branching distance from the
current PC’s value.
[True] d)
An unconditional jump instruction can be used to loop
back to the beginning of a loop body during loop iterations.
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Basic MIPS Assembly Language
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Sample Question (18)
18. State whether each of the following statements is
true or false.
[False] a)
It is always possible to replace the jump instruction by
conditional branch using: “beq $t1, $t1, Label” for “j Label”
[False] b)
Since MIPS has R, I and J instruction formats, its ISA is
said to have hybrid instruction format.
[False] c)
Given an array element A[k], the starting address of the
array is stored in $t0 and k in $t1. The element can be
loaded into the register $t2 using the instruction “lw $t2,
4$t1($t0)”.
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Basic MIPS Assembly Language
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End of file
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