It’s The Core & Much More ….
Key Success Factors to
32-bit MCU Design
Ying-wai Ho
General Manager, MIPS-Shanghai
MCU Technology and Application Forum
© 2010 MIPS Technologies, Inc. All rights reserved
At the core of the user experience.®
The Heritage of the MIPS Architecture
 Pioneered by Stanford President
John Hennessy in the 1980s
 Pure and elegant RISC architecture


Clean, fast, efficient
Designed for performance
 Now the architecture of choice for
multimedia, home networking & beyond
 Innovation continues by MIPS and
licensees including Altera, Broadcom,
Cavium, ICT, NEC, RMI Corp., Toshiba and
others
Widely used, widely taught architecture with
millions of lines of code written for it
© 2010 MIPS Technologies, Inc. All rights reserved
Photo: In 1984, Stanford computer scientists John Shott, John Hennessy and
James D. Meindl brainstorm about the MIPS project (Photo: Chuck Painter)
2
At the core of the user experience.®
MIPS-Shanghai - China Engineering Center
Dedicated Shanghai-based MIPS design &
engineering center—hardware & software
Only leading processor company
developing cores in China
New M14K and M14Kc soft cores
based on microMIPS ISA
designed and developed entirely in China
Expanding Shanghai engineering team
Leveraging China talent and cost structure
Future plans for expanding operations in China to
take on more engineering projects
© 2010 MIPS Technologies, Inc. All rights reserved
China Engineering Center
3
At the core of the user experience.®
A Systematic Philosophy for Design Success
microMIPS Advanced
Code Compression
2010
2006
2008
Coherent multiprocessing
2007
Superscalar Performance
Multi-threading
2002
2001
DSP Extensions
2005
Microcontroller-specific cores
Highest performance, synthesizable, licensable 32-bit cores
1999
MIPS32 and MIPS64 Architectures
1991
Industry’s First 64-bit microprocessor
Foundation for Success Built on
MIPS’ Legacy of Scalability
© 2010 MIPS Technologies, Inc. All rights reserved
4
At the core of the user experience.®
Industry’s Most
Scalable Processor Architecture
32-bit
Microcontrollers
And everything in between
© 2010 MIPS Technologies, Inc. All rights reserved
64-bit
Networking
5
At the core of the user experience.®
Microcontrollers: Proliferating MIPS Architecture
Performance and power efficiency
leadership
Over 20 MCU Licensees
including:
Microchip—number 1 MCU provider
32-bit PIC32 MCUs based on M4K core
Expanding family of core products M14K,
M14Kc
Addressing MCU design challenges
real time operation, small size, low power
Extending MIPS Architecture
microMIPS ISA code size reduction
Proliferating MIPS architecture to
large community of developers
© 2010 MIPS Technologies, Inc. All rights reserved
6
At the core of the user experience.®
Key Success Factors to 32-bit MCU Design
BEST
ARCHITECTURE
HIGH
PERFORMANCE
MCU
FEATURES
LOW
POWER
COMPLETE
TOOLS
SMALL
SIZE
© 2010 MIPS Technologies, Inc. All rights reserved
LARGE
ECOSYSTEM
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At the core of the user experience.®
MIPS Architecture
© 2010 MIPS Technologies, Inc. All rights reserved
8
At the core of the user experience.®
Wide Range of MIPS 32-Bit
Processor Core Families
1074K
Superscalar; 15-stage pipeline
>1.5GHz prod, >2.4GHz typ (40nm)
>6000 Coremark @ 2.4GHz
Mid-Range 8-stage pipeline
DSP extensions
900MHz prod (65nm)
24KE
74K
1004K
(1-4 cores)
Max ~1.5GHz
prod (40nm)
>12,000 Coremark
10,000 DMIPS
@ 1.25 GHz
Multi-Thread &
Mult-Core
Processing
34K
2010 EEPW - BEST IP award
24K
Smaller & faster
than Cortex M3
4KE
MIPS32 M14K & M14Kc
M14Kc
M4K
4KS
MCU, Embedded
5-stage pipeline
1.5 DMIPS/MHz
Low area & power
microMIPS advanced code compression
& Enhanced MCU Features
M14K
5-stage pipeline
1.48 DMIPS/MHz
300MHz (65nm LP)
2.6 CoreMark/MHz
>30% smaller code
size
Broad range of synthesizable processors
optimized for high performance & low power
© 2010 MIPS Technologies, Inc. All rights reserved
9
At the core of the user experience.®
Architecture for Performance – M4K/M14K
Family
 Classic RISC deep pipeline
 Single cycle throughput
 Single operation instructions
 Simple 32-bit addressing modes and 32-bit data bus
 Less speculative execution
 Efficient branching. No need for branch prediction.
 Compatible with 32- and 64- bit architectures.
 Many architecture extensions : ASE, UDI, COP, SPRam…
1.5 DMIPS/MHz
© 2010 MIPS Technologies, Inc. All rights reserved
10
At the core of the user experience.®
Microchip PIC32 Performance
EEMBC Coremark benchmark scores
MIPS M4K
80MHz, 2 wait state, PIC32 outperforms other MCU
devices operating at 120/100MHz, 0 wait state
© 2010 MIPS Technologies, Inc. All rights reserved
ARM Cortex-M3
ARM Cortex-M0
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At the core of the user experience.®
Architecture for Low Power
 Elegant architecture

Deliver the performance needed with lower frequency and smaller area
 Power reducing instructions


Software controlled power-down via WAIT instructions
Invokes SRAM sleep modes
 High code density Instruction sets, microMIPS & MIPS16e

Reduce system level memory and overall bus traffic
 Registers & handshaking signals for system power control
 Fully static design

Allows on-the-fly changes
 Fine-grain clock gating to reduce dynamic power


Automatically shuts down unused logic
Clock tree at root shuts down, wake up by external event
 Voltage/Frequency scaling support

Compatible with major DVFS IP
 Low power EDA flow support

Reference flow script support for all major EDA vendors physical
design tool chains.
© 2010 MIPS Technologies, Inc. All rights reserved
12
At the core of the user experience.®
Power Consumption – M14K
Power
(mW)
Normal Mode Power
(Dhrystone tight loop)
Speed Optimized
Area Optimized
Speed Optimized
Sleep Mode Power
Area Optimized
180G
130G
38.7
90G
30.7
65G
13.7
8.1
11.3
6.3
1.2
130
0.34
50
0.73
0.19
215
100
0.30
280
2.5
0.08
100
2.75
0.23
310
0.08
150
Target Freq (MHz)
© 2010 MIPS Technologies, Inc. All rights reserved
13
At the core of the user experience.®
Architecture for Minimum Code Size
microMIPS ISA – Maintains MIPS32 assembly code structure
 Complete Standalone ISA (Instruction Set Architecture)




Combines 16- and 32-bit instructions in a single ISA
Recoded MIPS32 & MIPS64 instructions
Includes 15 new 32-bit and 39 new 16-bit instructions
Frequent instructions and macros re-encoded to 16 bits
 High Performance


Code Size : >30% code size reduction;
Functional : MIPS32 level performance; 1.48 DMIPS/MHz, 2.6 CoreMark/MHz
 Compatibility



Supports MIPS32 and MIPS64® architectures
Supports co-existence with legacy MIPS32 decoder
Supports all MIPS ASEs
 Configurability

microMIPS is build time configurable
 Development Support


SW & HW tools – software toolchain, compiler, debug probe
3rd party ecosystem – RTOS, OS, tools
© 2010 MIPS Technologies, Inc. All rights reserved
14
At the core of the user experience.®
microMIPS Code Size Benchmarks
microMIPS code size reduction
100%
100%
90%
80%
70%
60%
50%
40%
30%
20%
10%
0%
73%
65%
73%
70%
MIPS32
microMIPS
MIPS32
CSiBe
Linux Kernel
CoreMark
Dhrystone
EEMBC v1.1
100%
100%
78%
80%
64%
69%
66%
65%
60%
40%
MIPS32
20%
microMIPS
0%
© 2010 MIPS Technologies, Inc. All rights reserved
15
At the core of the user experience.®
MCU Application - Specific optional features
 Reduced Interrupt Latency
IRQn
IRQn+1
Cycles
Prologue
10
ISRn
Chaining
ISRn+1
7
Epilogue
4
21 cycles total
 Enhanced Interrupt Interface

Vectored Interrupt & External Interrupt Controller modes with high number of inputs
 Multiple Shadow Register Sets

Multiple GPR’s for fast Interrupt service & context switching without save & restore
 Atomic Bit Instructions

Bit-set & Bit-clear for Read-Modify-Write semaphore manipulation.
 Flash Access Accelerator

Pre-fetch buffer scheme for slow memory access.
 Parity Support for on-chip memory

Increase system reliability if needed.
 Enhanced Debug Capabilities


Multiple program/data trace & profiling modes
Low overhead, low cost EJTAG
 DFT Coverage

Compliant with ATPG Scan Test and Memory-BIST to achieve high test coverage
© 2010 MIPS Technologies, Inc. All rights reserved
16
At the core of the user experience.®
M14K Core Features
32 GPRs
Shadow Regs
microMIPS & MIPS32
Instruction Decoder
Enhanced iFlowtrace
PC Sampling
Fast Debug Channel
Instruction
Pre-fetch
Multiply Divide
Unit
Reduced latency
Enhanced
Vector/Priority
AHB-Lite
Parity
CorExtend/UDI
Co-Processor
5-stage Pipeline
1.48 DMIPS/MHz
© 2010 MIPS Technologies, Inc. All rights reserved
Low Power
Atomic Bit
Instructions
Retained
Features
New/Enhanced
Features
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At the core of the user experience.®
M14K vs Cortex-M
•High Code Compression
at MIPS32 performance
•Same software platform
•Maintains efficiency
•Best Performance
•Best Real-Time
Performance
•Fastest Interrupt
Response
•Reduced Dev. Time
•Fast Time to
Product
•Fast Code Execution
•Scalable
•Uses std interfaces
•Expandable
•Customizable
FEATURE
Architecture
Pipeline stages
ISA
Legacy 32-bit decoder
Total instructions
DMIPS Performance
CoreMark Performance
GPRs
GPR sets (max)
Interrupt control
Priority levels
Interrupt latency
Tailchaining
Atomic bit instructions
Instruction-only trace
PC sampling
Perfomance counter
Fast Debug Channel
Multiply-Divide unit
Local Code Ram (max)
Local Data Ram (max)
Parity
Fast SRAM interface
Flash memory prefetch
MMU
External interface
Co-Processor interface
Custom Instruction support
© 2010 MIPS Technologies, Inc. All rights reserved
MIPS M14K
Harvard
5
MIPS32
microMIPS
Y - MIPS32
300+
1.48 DMIPS/MHz
2.36
32
16
Y - int & ext
8
10 cycles
Y
Y
Y
Y
Y
Y
Y
4GB
4GB
Optional
Y
Y
Y - FMT
AHB-Lite
Y
Y
ARM Cortex-M3
Harvard
3
Thumb-2
N
155
1.25 DMIPS/MHz
1.76
16
1
Y - int NVIC
4
16 cycles
Y
Y
N
N
N
N
Y
1GB
1GB
N
N
N
Optional
AHB-Lite
N
N
ARM Cortex-M0
Von Neumann
3
Thumb
Thumb-2 (subset)
N
56
0.9 DMIPS/MHz
1.6
13
1
32
4
16 cycles
Y
N
N
N
N
N
Multiply only
None
None
N
N
N
Optional
AHB-Lite
N
N
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At the core of the user experience.®
Cores: MIPS vs. ARM
>
 M14K can be configured to be
equivalent to a Cortex-M3, M1 or M0.
‘3 cores-in-1’
 With more features, more options
 Higher performance, more efficiency
 Lower power, smaller area
 Single development system
 Experience in design
© 2010 MIPS Technologies, Inc. All rights reserved
+
+
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At the core of the user experience.®
Strategic Ecosystem for Success
Complementary IP and Enabling Technologies
Graphics
RTOS/OS
Video
Audio
VoIP
Wireless Stacks
User Interfaces
Networks
Development Tools
Security
SoC IP
EDA/ESL
Foundries
Industry Orgs
Design Services
The right relationships to speed
customers’ SoC development
© 2010 MIPS Technologies, Inc. All rights reserved
21
At the core of the user experience.®
MCU & Embedded Solutions Summary
Ecosystem
Development Support
SG++
SysNav
SEAD-3
Debug / Profiling
EJTAG iFlowtrace Fast Debug Channel
Application-Specific Features
Reduced Latency microMIPS Flash acceleration
AHB-Lite Cache controller TLB MMU Parity
Efficient Base Architecture
High Performance
MIPS32 Release 2
Small Size
32 GPRs
© 2010 MIPS Technologies, Inc. All rights reserved
Low Power SRAM I/F
MDU CorExtend/UDI
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