CLK
CPU Wrapper
RST
Pipelined CPU
Alignment Unit
Controller
I-Cache
memory
Bus
Sharing
logic
Controller
D-Cache
Memory\
WISHBONE SYSTEM BUS
Word Alignment

The next problem we must solve
–
MemAddr_OutReg is word aligned


Address bits 1 and 0 are not used
Must do something about LH and LB which do not address the
low-order portion of the word
Because the processor sign/zero-extends the low-order portion of the word on a
LH, LHU, LB, LBU, we just need to right-shift the contents depending on the
offset!
Note: this has implications for stores!
Word Alignment
Memory [0x00004004] = 0x87654321
Byte 3
8
Byte 2
7
6
“11”
MemoryAddress(1:0)
5
Byte 1
Byte 0
4
2
“10”
“01”
Halfword 1
8
MemoryAddress(1:0)
7
6
“10”
3
1
“00”
Halfword 0
5
4
3
2
“00”
1
Word Alignment
Memory [0x00004004] = 0x87654321
Data in for LBU with MemoryAddress(1:0) = “00”
0
0
0
0
0
0
2
1
Data in for LBU with MemoryAddress(1:0) = “01”
0
0
0
0
0
0
4
3
Data in for LBU with MemoryAddress(1:0) = “10”
0
0
0
0
0
0
6
5
Data in for LBU with MemoryAddress(1:0) = “11”
0
0
0
0
0
0
8
7
Data in for LHU with MemoryAddress(1:0) = “00”
0
0
0
0
4
3
2
1
Data in for LHU with MemoryAddress(1:0) = “10”
0
0
0
0
8
7
6
5
Alignment Unit

Three modes for the alignment unit
 Word mode – pass all data, unshifted
 Halfword mode – shift top two byte lanes to low two byte lane (if
offset = 10)
 Byte mode – shift high byte lanes to low order (dep. on offset)
Address(0)
Address(1)
MSB
32-bit
Word
from memory
32-bit
Word
To CPU
LSB
CPU will
Sign extend if
necessary