Lecture 6
Timers
NCHUEE 720A Lab
Prof. Jichiang Tsai
DMTimer

The timer module contains a free running upward
counter with auto reload capability on overflow

The timer counter can be read and written in real-time


The module includes compare logic to allow an interrupt event


While counting
On a programmable counter matching value
A dedicated output signal can be pulsed or toggled on
overflow and match event.


This output offers a timing stamp trigger signal or PWM (pulse-width
modulation) signal sources
A output signal can be used for general purpose PORGPOCFG

Directly driven by bit 14 of the TCLR register
NCHUEE 720A Lab
Prof. Jichiang Tsai
DMTimer (cont.)

A dedicated input signal is used to trigger automatic timer
counter capture and interrupt event



A programmable clock divider (prescaler) allows reduction of
the timer input clock frequency
All internal timer interrupt sources are merged in one module
interrupt line and one wake-up line


On programmable input signal transition type
Each internal interrupt sources can be independently enabled/disabled
This module is controllable through the OCP peripheral bus

Two clock domains are managed inside this module


Resynchronization is done by special logic between the OCP clock domain
and the Timer clock domain
At reset, synchronization logic allows utilization of all ratios between
the OCP clock and the Timer clock
NCHUEE 720A Lab
Prof. Jichiang Tsai
DMTimer (cont.)


Write-posted mode is used to improve module access latency


By setting the POSTED bit of the System Control Register (TSCR)
OCP write command is granted before write process complete in the
timer clock domain


A drawback of this mode is that full-resynchronization path is used with
access latency performance impact in terms of OCP clock cycles
Observe write process completion (synchronization) at the software level
by reading independent write posted status bits in the Write Posted Status
Register (TWPS)
The timer consists of the following features:



Counter timer with compare and capture modes
Auto-reload mode & Start-stop mode
Programmable divider clock source & 16-32 bit addressing
NCHUEE 720A Lab
Prof. Jichiang Tsai
DMTimer (cont.)







“On the fly” read/write registers
Interrupts generated on overflow, compare and capture
Interrupt enable & Wake-up enable (only for Timer0)
Write posted mode & OCP interface compatible
Dedicated input trigger for capture mode and dedicated
output trigger/PWM signal
Dedicated output signal for general purpose use
PORGPOCFG
The Timer resolution and interrupt period are dependent
on the selected input clock and clock prescale value
NCHUEE 720A Lab
Prof. Jichiang Tsai
Timer Block Diagram
NCHUEE 720A Lab
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Timer Connectivity Attributes
NCHUEE 720A Lab
Prof. Jichiang Tsai
Timer Clock and Reset Management

Each DMTimer[2–7] functional clock is selected

Within the PRCM Using the CLKSEL_TIMERx_CLK register




The 24-MHz (typ) system clock (CLK_M_OSC)
The PER PLL generated 32.768 KHz clock (CLK_32KHZ)
The TCLKIN external timer input clock
The DMTimer 0 functional clock is fixed

Use the internal 32KHz RC Clock (CLK_RC32K)
NCHUEE 720A Lab
Prof. Jichiang Tsai
Timer Pin List

The timer PIEVENTCAPT input and PORTIMERPWM
output signals are muxed onto a single TIMER I/O pad

The pad direction (and hence the pin function) are controlled
from within the DMTimer module

Using the PORGPOCFG signal as an output enable
NCHUEE 720A Lab
Prof. Jichiang Tsai
Functional Modes

The general-purpose timer supports 3 functional modes

Timer mode, Capture mode and Compare mode


By default, after reset, the capture and compare modes are disabled
Timer Mode

The timer can be started and stopped at any time


The Timer Counter Register (TCRR) can be loaded when stopped or
on the fly (while counting)




Through the Timer Control Register (TCLR ST bit)
Loaded directly by a TCRR Write access with the new timer value
TCRR can also be loaded with the value held in the Timer Load Register
TLDR by a trigger register (TTGR) Write access
The TCRR loading is done regardless the TTGR written value.
The TCRR value can be read when stopped or captured on the fly by
a TCRR Read access
NCHUEE 720A Lab
Prof. Jichiang Tsai
Functional Modes (cont.)

When the module’s reset is asserted



When the timer is stopped, TCRR is frozen



The TCRR is reloaded with the Timer Load Register (TLDR) value after a
counting overflow
Not recommended to put the overflow value (FFFF FFFFh) in TLDR


The counter is stopped after counting overflow
Counter value remains at zero
When the auto-reload mode is enabled (TCLR AR bit = 1)


It can be restarted from the frozen value unless reloaded with a new value
In the one shot mode (TCLR AR bit = 0)


The timer is stopped and the counter value is cleared to “0”
The timer is maintained in stop after reset is released.
Because it can lead to undesired results
An interrupt can be issued on overflow if the overflow interrupt
enable bit is set
NCHUEE 720A Lab
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Functional Modes (cont.)


In the timer Interrupt Enable Register (IRQENABLE_SET OVF_IT_FLAG
bit = 1)
A dedicated output pin (PORTIMERPWM) is programmed through
TCLR (TRG and PT bits)

To generate one positive pulse (prescaler duration) or to invert the
current value (toggle mode) when an overflow occurs
NCHUEE 720A Lab
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Functional Modes (cont.)

Capture Mode

The value in TCRR can be captured and saved in TCAR1 or TCAR2
when a transition is detected on the module input pin PIEVENTCAPT


The edge detection circuitry monitors transitions on PIEVENTCAPT


Rising transition, falling transition or both can be selected in TCLR (TCM
bit) to trigger the timer counter capture
The module sets the IRQSTATUS (TCAR_IT_FLAG bit) when an
active transition is detected


Function of the mode is selected in TCLR through the field CAPT_MODE
The counter value TCRR is stored in one of the timer capture registers
If TCLR’s CAPT_MODE field is 0, on the first enabled capture event,
the value of the counter register is saved in TCAR1 register


All the next events are ignored until the detection logic is reset or the
interrupt status register is cleared on TCAR’s position
No update on TCAR1 and no interrupt triggering
NCHUEE 720A Lab
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Functional Modes (cont.)

The TCM value is 01 and CAPT_MODE is 0

Only rising edge of the PIEVENTCAPT will trigger a capture in TCAR
and only TCAR1 will update
NCHUEE 720A Lab
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Functional Modes (cont.)

If TCLR’s CAPT_MODE field is 1, on the first enabled captured event,
the counter value is saved in TCAR1 register





The edge detection logic is reset




On the second enabled capture event, the value of the counter register is
saved in TCAR2 register until the detection logic is reset or the interrupt
status register is cleared on TCAR’s position
All the other events are ignored
No update on TCAR1/2 and no interrupt triggering
This mechanism is useful for period calculation of a clock if that clock is
connected to the PIEVENTCAPT input pin
When the active capture interrupt is served
TCAR_IT_FLAG bit of IRQSTATUS (previously 1) is cleared
A new capture is enabled
The timer functional clock (input to prescaler) is used to sample the
input pin (PIEVENTCAPT)
NCHUEE 720A Lab
Prof. Jichiang Tsai
Functional Modes (cont.)


An interrupt can be issued on transition detection


Input pulse can be detected as pulse time is above functional clock period
If the capture interrupt enable bit is set in the Timer Interrupt Enable
Register IRQENABLE_SET (TCAR_IT_FLAG bit)
Compare Mode

The timer value (TCRR) is permanently compared to the value held in
timer match register (TMAR)



When TCRR and TMAR values match, an interrupt can be issued


When Compare Enable TCLR (CE bit) is set to 1
TMAR value can be loaded at any time (timer counting or stop)
If the IRQENABLE_SET (MAT_EN_FLAG bit) is set
The dedicated output pin (PORTIMERPWM) can be programmed
through TCLR (TRG and PT bits)

To generate one positive pulse (TIMER clock duration) or to invert the
current value (toggle mode) when an overflow and a match occur
NCHUEE 720A Lab
Prof. Jichiang Tsai
Functional Modes (cont.)

The TCM value is 01 and CAPT_MODE is 1


Only rising edge of the PIEVENTCAPT will trigger a capture in
TCAR1 on first enabled event
TCAR2 will update on the second enabled event
NCHUEE 720A Lab
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Prescaler

A prescaler counter can be used to divide the timer
counter input clock frequency



The prescaler is enabled when TCLR bit 5 is set (PRE)
The 2n division ratio value (PTV) can be configured in TCLR
The prescaler counter is reset when the timer counter is
stopped or reloaded on the fly
NCHUEE 720A Lab
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Pulse-Width Modulation

The timer can be configured to provide a programmable
pulse-width modulation (PORTIMERPWM) output

The output pin can be configured to toggle on specified event

TCLR (TRG bits) determines on which register value the pin toggles



Either overflow or match can be used to toggle the PORTIMERPWM pin,
when a compare condition occurs
In case of overflow and match mode, the match event will be ignored from
the moment the mode was setup until the first overflow event occurs
The TCLR (SCPWM bit) can be programmed to set or clear the
PORTIMERPWM output signal




While the counter is stopped or the triggering is off only
Allows fixing a deterministic state of the output as modulation is stopped
0x0 = Clear PORTIMERPWM pin and select positive pulse for pulse mode
0x1 = Set PORTIMERPWM pin and select negative pulse for pulse mode
NCHUEE 720A Lab
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Pulse-Width Modulation (cont.)


The modulation is synchronously stopped when TRG bit is
cleared and overflow occurred
The TLDR and TMAR registers must keep values smaller than
the overflow value (FFFF FFFFh) with at least 2 units



In case the PWM trigger events are both overflow and match, the
difference between the values kept in TMAR register and the value in
TLDR must be at least 2 units
As match event is used, the compare mode TCLR (CE) must be set
The internal overflow pulse is set each time (FFFF FFFFFh –
TLDR + 1) value is reached


Also set when the counter reaches TMAR register value
According to TCLR (TRG and PT bits) programming value, the timer
provides pulse or PWM on the output pin (PORTIMERPWM)

PT: Pulse or toggle mode on PORTIMERPWM output pin
NCHUEE 720A Lab
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Pulse-Width Modulation (cont.)

TCLR (SCPWM bit) is cleared to 0
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Pulse-Width Modulation (cont.)

TCLR (SCPWM bit) is set to 1
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Timer Counting Rate

The timer counter is composed of a prescaler stage and a
timer counter

Prescaler stage is clocked with the timer clock


Acts as a clock divider for the timer counter stage
The ratio can be managed by accessing the ratio definition field of the
control register (PTV and PRE of TCLR)
NCHUEE 720A Lab
Prof. Jichiang Tsai
Timer Counting Rate (cont.)

The timer rate is defined by


The value of the prescaler fields (PRE and PTV of TCLR register)
The value loaded into the Timer Load Register (TLDR)



(FFFF FFFFh – TLDR + 1) × timer Clock period × Clock Divider (PS)
With timer Clock period = 1/ timer Clock frequency and PS = 2(PTV + 1)
If we consider a timer clock input of 32 kHz, with a PRE field equal to
0, the timer output period is:
NCHUEE 720A Lab
Prof. Jichiang Tsai
Accessing Registers

All registers are 32-bit wide

Accessible via OCP interface with 16-bit or 32-bit OCP access


The 32-bit registers write update in 16 bits access must be LSB16 first
and the second write access must be MSB16
The module allows skipping the MSB access if the user does not need
to update the 16 MSB bits of the register


The write operation on any functional register (TCLR, TCRR, TLDR,
TTGR and TMAR) must be complete


Only for registers TIDR, TIOCP_CFG, IRQSTATUS_RAW, IRQSTATUS,
IRQENABLE_SET, IRQENABLE_CLR, IRQWAKEEN and TSICR
The MSB must be written even if the MSB data is not used
The registers write is done synchronously with OCP clock, by the
host, using the OCP bus protocol

TLDR, TCRR, TCLR, TIOCP_CFG, IRQSTATUS, IRQENABLE_SET,
IRQENABLE_CLR, IRQWAKEEN, TTGR, TSICR and TMAR
NCHUEE 720A Lab
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Accessing Registers (cont.)

The counter register (TCRR) is a 32-bit “atomic datum”



16-bit capture is done on the 16-bit LSB first to allow atomic LSB16 +
MSB16 capture
Atomic capture is also performed for the TCAR1 and TCAR2
registers as they may change due to internal processes
A choice between the two synchronization modes

Posted/non-posted



Taking into account the frequency ratio and the stall periods that can
be supported by the system
Without impacting the global performance
The posted mode selection applies only to functional registers
that require synchronization on/from timer clock domain

For write operation the registers affected by this selection are: TCLR,
TLDR, TCRR, TTGR and TMAR
NCHUEE 720A Lab
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Accessing Registers (cont.)


For read operation the register affected by this posted/nonpostedselection are: TCRR, TCAR1 and TCAR2
The OCP clock domain synchronous registers are not affected by the
posted/non-posted mode selection



TIDR, TIOCP_CFG, TISTAT, IRQSTATUS, IRQSTATUS_RAW,
IRQENABLE_SET, IRQENABLE_CLR, IRQWAKEEN, TWPS and TSICR
The write/read operation is effective and acknowledged (command
accepted) after one OCP clock cycle from the command assertion
Posted Mode


Used when freq (timer) < freq (OCP)/4
It uses a posted-write scheme to update any internal register



The write transaction is immediately acknowledged on the OCP interface
The effective write operation will occur later due to a resynchronisation
in the timer clock domain
Not stalling either the interconnect system, or the CPU
NCHUEE 720A Lab
Prof. Jichiang Tsai
Accessing Registers (cont.)

The drawback of this automatic update mechanism is


Assumes a given relationship between the OCP interface frequency and
the timer functional frequency
Non-Posted Mode

Used regardless of the frequency range


Uses a non posted-write scheme to update any internal register





Recommended frequency is: freq (timer) >= freq (OCP)/4
Write transaction will not be acknowledged on the OCP interface, until
the effective write operation occurs, after the resynchronisation
Both the interconnect system and the CPU are stalled during this period
The latency of the interrupt serving is increased
An interconnect logic, including time-out logic to detect erroneous
transactions, can generate an unwanted system abort event
A register read following a write to the same register is always
coherent
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TIMER Registers
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WATCHDOG

The watchdog timer is an upward counter capable of

Generating a pulse on the reset pin and an interrupt to the
device system modules following an overflow condition.

The watchdog timer serves resets to the PRCM module



Also serves watchdog interrupts to the host ARM
The watchdog timer can be accessed, loaded, and cleared by registers



Through the L4 interface
Connects to a single target agent port on the L4 interconnect
It have the 32-kHz clock for their timer clock input


The reset of the PRCM module causes warm reset of the device
The default state of the watchdog timer is enabled and not running
The main features of the watchdog timer controllers are

L4 slave interface support
NCHUEE 720A Lab
Prof. Jichiang Tsai
WATCHDOG (cont.)









32-bit data bus width & 32-/16-bit access supported
11-bit address bus width & Write nonposted transaction mode only
Free-running 32-bit upward counter
Programmable divider clock source (2n where n = 0-7)
On-the-fly read/write register (while counting)
Subset programming model of the GP timer
The watchdog timers are reset either on power-on or after a
warm reset before they start counting
Reset or interrupt actions upon a timer overflow condition
The watchdog timer generates a reset or an interrupt in its
hardware integration
NCHUEE 720A Lab
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Power Management

There are two clock domains in the watchdog timers

Functional clock domain

WDTi_FCLK is a 32 kHz watchdog timer functional clock


Interface clock domain

WDTi_ICLK is a 125 MHz watchdog timer interface clock



Used to clock the watchdog timer internal logic
Used to synchronize the watchdog timer L4 port to the L4 interconnect
All accesses from the interconnect are synchronous to WDTi_ICLK.
The clocks to the watchdog timers are always On

The clocks cannot be turned off, even if the timer is not being used
NCHUEE 720A Lab
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Timer Operation

Based on an upward 32-bit counter with a prescaler

The counter overflow is signaled through two signals



The interrupt generation mechanism is controlled through


By accessing the WDT_WCLR[4:2] PTV bit field and the
WDT_WCLR[5] PRE bit of the control register (WDT_WCLR)
The current timer value can be accessed on-the-fly


WDT_WIRQENSET/WDT_WIRQENCLR and WDT_WIRQSTAT
The prescaler ratio can be set from 1 to 128


A simple reset signal and an interrupt signal
Both active low
By reading the watchdog timer counter register (WDT_WCRR)
Modified by accessing the watchdog timer load register
WDT_WLDR (no on-the-fly update)
NCHUEE 720A Lab
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Timer Operation (cont.)


Or reloaded by following a specific reload sequence on the watchdog
timer trigger register (WDT_WTGR)
A start/stop sequence to the timer start/stop register
(WDT_WSPR) can start and stop the watchdog timers
NCHUEE 720A Lab
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Overflow/Reset Generation

The watchdog timers are enabled after reset


To get the default reset values, software must read the
corresponding WDT_WCLR[4:2] PTV bit field and the 32-bit
register to retrieve the static configuration of the module
When the counter register (WDT_WCRR) overflows, an
active-low reset pulse is generated to the PRCM module

This RESET pulse causes the PRCM module to generate global
WARM reset of the device


Also driven out of the device through the WD_OUT pin
This pulse is one prescaled timer clock cycle wide

Occurs at the same time as the timer counter overflow
NCHUEE 720A Lab
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Overflow/Reset Generation (cont.)

After reset generation, the counter is automatically reloaded
with the value stored in the load register (WDT_WLDR)


The prescaler is reset (the prescaler ratio remains unchanged)
When the reset pulse output is generated, the timer counter
begins incrementing again
NCHUEE 720A Lab
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Start/Stop Sequence

Through the start/stop register (WDT_WSPR)

To disable the timer

Write XXXX AAAAh in WDT_WSPR


Write XXXX 5555h in WDT_WSPR


Poll for posted write to complete using WDT_WWPS.W_PEND_WSPR
To enable the timer


Write XXXX BBBBh in WDT_WSPR
Write XXXX 4444h in WDT_WSPR


Poll for posted write to complete using WDT_WWPS.W_PEND_WSPR
Poll for posted write to complete using WDT_WWPS.W_PEND_WSPR
To modify the timer counter value, prescaler ratio, delay
configuration value, or the load value

The watchdog timer must be disabled by the start/stop sequence
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Interrupt Generation

When an interrupt source occurs

The interrupt status bit (the WDT_WIRQSTAT[0]
EVENT_OVF or WDT_WIRQSTAT[1] EVENT_DLY bit) is set

The output interrupt line (WDTi_IRQ) is asserted (active low)



Writing 1 to the enable bit (the status is already set at 1) also triggers
the interrupt in the normal order (enable first, status next)
The pending interrupt event is cleared when the set status bit
is overwritten by a value of 1

By a write command in the WDT_WIRQSTAT register


When status (the EVENT_xxx bit) and enable (the xx_IT_ENA bit) flags
are set to 1
Reading the WDT_WIRQSTAT register and writing the value back allows
a fast interrupt acknowledge process
The watchdog timer issues an overflow interrupt
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Interrupt Generation (cont.)

If this interrupt is enabled in the watchdog interrupt enable
register (WDT_WIRQENSET[0] OVF_IT_ENA = 1)


When the overflow occurs, the interrupt status bit (the
WDT_WIRQSTAT[0] EVENT_OVF bit) is set to 1
The output interrupt line (WDT_IRQ) is asserted (active low)


This interrupt can be disabled


When status (EVENT_OVF) and enable (OVF_IT_ENA) flags are set to 1
By setting the WDT_WIRQENCLR[0] OVF_IT_ENA bit to 1
The watchdog can issue the delay interrupt

If this interrupt is enabled in the interrupt enable register
(WDT_WIRQENSET[1] DLY_IT_ENA = 1)

When the counter is running and the counter value matches the value
stored in the delay configuration register WDT_WDLY
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Interrupt Generation (cont.)


The corresponding interrupt status bit is set in WDT_WIRQSTAT
the output interrupt line is asserted (active low)


This interrupt can be disabled


When the flag (EVENT_DLY) and enable (DLY_IT_ENA) bits are 1 in the
WDT_WIRQSTAT and WDT_WIRQENSET registers, respectively
By setting the WDT_WIRQENCLR[1] DLY_IT_ENA bit to 1
The WDT_WDLY register is used to specify the value of the
delay configuration register.

The delay time to interrupt is the difference between the reload value
stored in the counter load register (WDT_WLDR) and the
programmed value in this register (WDT_WDLY)


Delay time period = (WDT_WDLY – WDT_WLDR + 1) × Timer clock
period × Clock divider
If the counter value (WDT_WCRR) reaches the programmed value
(WDT_WDLY), an interrupt occurs
NCHUEE 720A Lab
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