Interrupts, Timer, and Interrupt Controller
Prof. Taeweon Suh
Computer Science Education
Korea University
Interrupt
• Interrupt is an asynchronous signal from hardware indicating the
need for attention or a synchronous event in software indicating the
need for a change in execution.
 Hardware interrupt causes the processor (CPU) to save its state of
execution via a context switch, and begin execution of an interrupt handler.
 Software interrupt is usually implemented as an instruction in the instruction
set, which cause a context switch to an interrupt handler similar to a
hardware interrupt.
• Interrupt is a commonly used technique in computer system for
communication between CPU and peripheral devices
• Operating systems also extensively use interrupt (timer interrupt)
for task (process, thread) scheduling
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Software Interrupt in ARM
•
There is an software interrupt instruction in ARM

•
SWI instruction
Software interrupt is commonly used by OS for system calls

Example: open(), close().. etc
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Hardware Interrupt in ARM
• IRQ (Normal interrupt request)
 Informed to CPU by asserting IRQ pin
 Program jumps to 0x0000_0018
• FIQ (Fast interrupt request)
 Informed to CPU by asserting FIQ pin
 Has a higher priority than IRQ
 Program jumps to 0x0000_001C
IRQ
FIQ
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Exception Vectors in ARM
RAZ: Read As Zero
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Exception Priority in ARM
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S3C2440A Block Diagram
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Simplified Hardware System
Interrupt
Controller
Interrupt
ARM920T
Address Bus
R15
….
EAX
R1
(PWM)
Timer
ALU
R0
32-bit
32-bit
0x00000FFF
4KB SRAM
(Steppingstone)
0x00000000
UART
GPIO
32MB SDRAM
Memory
Controller
Data Bus
0x30000000
AMBA
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INTC in S3C2440A
INTMOD (0x4A00_0004)
(Interrupt Mode Register)
SRCPND (0X4A00_0000)
(Source Pending Register)
32-bit
UART_IRQ
TIMER_IRQ
Bit14
Interrupt Controller
…
Only 1-bit with the
highest priority is set
…
nIRQ
0
1
nFIQ
…
Bit14
32-bit
…
INTMSK (0x4A00_0008)
(Interrupt Mask Register)
INTPND (0x4A00_0010)
(Interrupt Pending Register)
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INTMOD (0x4A00_0004)
(Interrupt Mode Register)
Example
0
SRCPND (0X4A00_0000)
(Source Pending Register)
UART_IRQ
TIMER_IRQ
0
32-bit
0
Interrupt Controller
0
0 Bit14
1
0
…
0
0
…
Only 1-bit with the
highest priority is set
0
0
0
0
0
0
0
1
0
0
0
0
1
nIRQ
nFIQ
…
0
0
0
0
0 Bit14
32-bit
0
…
0
0
0
INTMSK (0x4A00_0008)
(Interrupt Mask Register)
0
INTPND (0x4A00_0010)
(Interrupt Pending Register)
Note that the corresponding bit in both SRCPND and
INTPND should be cleared via SW after servicing an
interrupt.
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Timers
http://a-towntales.blogspot.kr/2011/09/dreaded-alarm-clock.html
http://www.ikea.com/us/en/catalog/products/50187566/
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Timer in S3C2440A
• 5 Timers
 Timer 0, 1, 2, 3 have
PWM (Pulse Width
Modulation) function
 Timer 4 has no output
 16-bit counters
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Timer 4 in S3C2440A
• Timer 4 has no output
Interrupt generated
Read TCNTO4 to get the current counter value
TCNT4
TCNTB4
xx
5
5
4
3
2
TCNTB4 write to “5”
5
4
3
2
1
0
5
Manual_update=1
Start=1
0
1
Auto_reload=1
Manual_update=0
Program this register
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Timer 4 Registers
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Timer 4 Registers
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UART
• Universal Asynchronous Receiver
and Transmitter
 Used for serial communication
 Simply called serial port (or RS-232)
 Has a long history (~1970)
 Still widely used in embedded systems
design for debugging purpose
 Detected as a COM port in Windows
• Its original shaped port has almost been
disappeared in computers. Instead, the
serial-to-USB is used whenever necessary
http://sd.hancock.k12.mo.us/files/2010/11/Computer-Back-marked-in-red.jpg
http://linuxologist.com/01general/back-to-basics-identify-your-computer-ports/
http://www.passmark.com/products/loopback.htm
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UART
http://pcsbyjohn.wordpress.com/
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http://tutorial.cytron.com.my/2012/02/16/uart-universal-asynchronous-receiver-and-transmitter/
Korea Univ
UART in S3C2440A
•
3 Channels (UART0, UART1,
and UART3)
•
We use UART0 for debugging



Transmission only to PC
Non-FIFO mode
No interrupt
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UART Registers
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UART Registers (Cont.)
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UART Registers (Cont.)
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Memory Map of Our System
0xFFFF_FFFF
Memory Space
Address Bus
ARM CPU
0x5600_0000
R15
….
EAX
R1
R0
ALU
GPIO
0x5100_0000
Timer
0x5000_0000
UART
0x4A00_1000
INTC
32-bit
32-bit
SDRAM
0x3000_0000
Data Bus
0x0000_0FFF
0x0
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SRAM
4KB
Korea Univ
Linker Script
• Check out the linker script in Makefile
 Figure out what the linker script says where the code and data in the
program should be located in memory
test.lds
test.s
MEMORY
{
RAM (rwx) : ORIGIN = 0x0, LENGTH = 4K
}
.text
b
b
b
b
b
b
b
b
REGION_ALIAS("REGION_TEXT", RAM);
REGION_ALIAS("REGION_RODATA", RAM);
REGION_ALIAS("REGION_DATA", RAM);
REGION_ALIAS("REGION_BSS", RAM);
ResetHandler
.
.
.
.
.
.
.
SECTIONS
{
.text :
{
*(.text)
. = ALIGN(4);
} > REGION_TEXT
.rodata :
{
__RO_BASE__ = .;
*(.rodata)
*(.rodata.*)
ResetHandler:
mov r0, #16
ldr r2, =LED_BASE
. = ALIGN(4);
__RO_LIMIT__ = .;
} > REGION_RODATA
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Backup Slides
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AMBA
• Advanced Microcontroller Bus Architecture
 On-chip bus protocol from ARM
• On-chip interconnect specification for the connection and
management of functional blocks including processor and
peripheral devices
 Introduced in 1996
 AMBA is a registered trademark of ARM Limited.
 AMBA is an open standard
Wikipedia
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AMBA History
• AMBA
• AMBA 3 (2003)
 AXI3 (or AXI v1.0)
 ASB
 APB
• widely used on ARM Cortex-A
processors including Cortex-A9
 AHB-Lite v1.0
 APB3 v1.0
 ATB v1.0
• AMBA 2 (1999)
 AHB
• widely used on ARM7, ARM9 and
ARM Cortex-M based designs
 ASB
 APB2 (or APB)
• AMBA 4 (2010)
 ACE
• widely used on the latest ARM CortexA processors including Cortex-A7 and
Cortex-A15
 ACE: AXI Coherency Extensions
 AXI: Advanced eXtensible Interface
 AHB: Advanced High-performance Bus
 ASB: Advanced System Bus
 APB: Advanced Peripheral Bus
 ATB: Advanced Trace Bus
Wikipedia






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ACE-Lite
AXI4
AXI4-Lite
AXI-Stream v1.0
ATB v1.1
APB4 v2.0
Korea Univ
ASB
AMBA Specification V2.0
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ASB
Hardware
Device 0
Hardware
Device 1
Hardware
Device 2
Hardware
Device 4
Hardware
Device 5
ASB
Hardware
Device 3
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AHB
AMBA Specification V2.0
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AHB with 3 Masters and 4 Slaves
 “H” indicates AHB signals
AMBA Specification V2.0
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AHB Basic Transfer Example with Wait
Write data
Read data
HREADY Source: Slave
AMBA Specification V2.0
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AHB Burst Transfer Example
HREADY Source: Slave
AMBA Specification V2.0
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AHB Split Transaction
• If slave decides that it
may take a number of
cycles to obtain and
provide data, it gives a
SPLIT transfer response
• Arbiter grants use of the
bus to other masters
HRESP: Transfer response fro slave (OKAY, ERROR, RETRY, and SPLIT)
AMBA Specification V2.0
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APB Write/Read
AMBA Specification V2.0
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AXI v1.0
• AMBA AXI protocol is targeted at high-performance,
high-frequency system designs
• AXI key features
 Separate address/control and data phases
 Support for unaligned data transfers using byte strobes
 Separate read and write data channels to enable low-cost
Direct Memory Access (DMA)
 Ability to issue multiple outstanding addresses
 Out-of-order transaction completion
 Easy addition of register stages to provide timing closure
AMBA AXI Specification V1.0
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5 Independent Channels
• Read address channel and Write address channel
 Variable length burst: 1 ~ 16 data transfers
 Burst with a transfer size of 8 ~ 1024 bits (1B ~ 256B)
• Read data channel
 Convey data and any read response info.
 Data bus can be 8, 16, 32, 64, 128, 256, 512, or 1024 bits
• Write data channel
 Data bus can be 8, 16, 32, 64, 128, 256, 512, or 1024 bits
• Write response channel
 Write response info.
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AXI Read Operation
Read
Address
Channel
Read
Response
Channel
RREADY: From master, indicate that master can accept the read data and response info.
AMBA AXI Specification V1.0
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AXI Write Operation
Write
Address
Channel
Write
Data
Channel
Write
Response
Channel
 WVALID Source: Master
 WREADY Source: Slave
AMBA AXI Specification V1.0
 BVALID Source: Slave
 BREADY Source: Master
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Out-of-order Completion
• AXI gives an ID tag to every transaction
 Transactions with the same ID are completed in order
 Transactions with different IDs can be completed out of order
AMBA AXI Specification V1.0
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ID Signals
Write
Data
Channel
Write
Address
Channel
Write
Response
Channel
Read
Address
Channel
Read
Response
Channel
AMBA AXI Specification V1.0
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Out-of-order Completion
• Out-of-order transactions can improve system performance in
2 ways
 Fast-responding slaves respond in advance of earlier transactions
with slower slaves
 Complex slaves can return data out of order
• A data item for a later access might be available before the data for an
earlier access is available
• If a master requires that transactions are completed in the
same order that they are issued, they must all have the same
ID tag
• It is not a required feature
 Simple masters and slaves can process one transaction at a time in
the order they are issued
AMBA AXI Specification V1.0
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Addition of Register Slices
• AXI enables the insertion of a register slice in any
channel at the cost of an additional cycle latency
 Trade-off between latency and maximum frequency
• It can be advantageous to use
 Direct and fast connection between a processor and highperformance memory
 Simple register slices to isolate a longer path to less
performance-critical peripherals
AMBA AXI Specification V1.0
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