# SoRaX - Electrical and Computer Engineering Department

```Software-defined Radio using Xilinx
Anton S. Rodriguez, Michael C. Mensinger, Jr.
Dr. In Soo Ahn and Dr. Yufeng Lu
Department of Electrical and Computer Engineering
Outline
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Motivation
Project Goals
Equipment
QPSK Theory
Background
System Block Diagram
Requirements
Results
Conclusions
References
Motivation
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(SDR) provides a versatile
wireless communication
solution for a wide range of
applications.
Applications:
• Cell phones
• GPS
• Wi-Fi
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The SDR can be easily
modified to the operating
needs of individual
applications.
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Lower costs
• No expensive equipment
• No need to replace
hardware
Project Overview
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The objective of this project is
to design a communication
board.
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QPSK modulation scheme is
used.
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The main focus is on the
carrier synchronization and
phase ambiguity correction
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A Simulink model of the entire
system is designed and then
implemented on the
SignalWave Virtex-II FPGA
board .
Project Goals
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Gain an in-depth
FPGA implementation of
carrier synchronization.
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Achieve fast acquisition of
carrier synchronization.
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model.
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model on an FPGA board.
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Correct the phase ambiguity
present in the recovered data.
Equipment
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Virtex 4 FPGA
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Xilinx - ISE 9.2 Compiler
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SignalWave Virtex-II
FPGA
QPSK Signal Representation
2 bits
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s(t) = I(t)*cos(2πfot) – Q(t)*sin(2 πfot)
= A*cos(2πfot + θ(t))
θ(t)
I(t)
Q(t)
π/4
1
1
3π/4
-1
1
5π/4
-1
-1
7π/4
1
-1
Q
I
Background
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Previous QPSK Project
Digital Data
(Transmitter)
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Wired
Channel
Digital Data
Objectives:
• Make this system wireless
• Overcome the following communication problems:
 Multi-path effect
 Carrier synchronization
 Phase ambiguity
Multi-path Effect
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Random process.
α1*x(t-τ1)
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A number of different paths
may be traveled.
A
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Constructive/destructive
interference.
α2*x(t-τ2)
α3*x(t-τ3)
B
Carrier Synchronization
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Wireless communication introduces distortion due to channel
imperfections.
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The carrier signals must be synchronized to decode data correctly
for both I &amp; Q channels.
Phase Ambiguity
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Typical problem in QPSK
systems.
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Due to the nature of phaselocking characteristics, a static
phase error is introduced.
Q
Q
I
I
Transmitted and decoded in-phase data
Outline
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Motivation
Project Goals
Equipment
QPSK Theory
Background
System Block Diagram
Requirements
Results
Conclusions
References
System Block Diagram
Channel
Baseband Signal Shaping
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Raised-cosine filtering
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Reduces inter-symbol interference (ISI)
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Interpolator/Decimator
Interpolator
Decimator
System Block Diagram
Channel
Phase-Locked Loop
(Carrier Recovery)
Corrected Signal
X(n)
I(n)
FIR
LPF
r(n)
cos(Өon+Ф)
+
-
FIR
LPF
Y(n)
-sin(Өon+Ф)
Q(n)
DDS
Loop Filter
Y(n)*I(n) - X(n)*Q(n)
Functional Requirements
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System clock = 50 MHz
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Carrier signal frequency = 12.5 MHz
• Data rate = 12.5 Mbps
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The frequency offset tolerance is 1 kHz.
Results
(Carrier Synchronization)
QPSK signal
I &amp; Q waveforms
Results
(Phase Ambiguity)
Transmitted Image
Results
(Phase Ambiguity Correction)
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Differential coding
Channel
Results
(No Phase Ambiguity / Color)
Transmitted Image
Results
(Preserved data / Color)
Conclusions
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QPSK wireless communication system is designed
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Carrier synchronization is achieved using digital PLL
Phase ambiguity is resolved using differential coding
Tested whole system with real data
Hardware implementation
Demonstrated the configurability of a software-defined radio
• Expandable to MPSK, MQAM and other modulation schemes
Future Work
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Symbol timing
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Error correcting capabilities
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Implement other modulation schemes
• 8PSK
• 16PSK
• and so on…
Acknowledgements
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Dr. Yufeng Lu
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Dr. In Soo Ahn
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Senior Project Support from
• Department of Electrical and Computer Engineering
Questions?
References
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Chris Dick, Fred Harris, and Michael Rice, FPGA Implementation of Carrier
Synchronization for QAM Receivers, Journal of VLSI Signal