COM509 Computer Systems
Lecture 2. Chipset and PCIe
Prof. Taeweon Suh
Computer Science Education
Korea University
x86-based Computer System
CPU
Main
Memory
(DDR2)
FSB
(Front-Side Bus)
Graphics
card
North
Bridge
South
Bridge
Hard disk
USB
BIOS
ROM
PCIe card
2
Korea Univ
Q35 Chipsets System Block Diagram
3
Korea Univ
Chipsets
• Chipsets include MCH and ICH in the x86-based system
 There are PCIe devices inside the MCH and the ICH
 Backbone of MCH and ICH is based on PCI express
• Q35 (North Bridge)
 Device 0 : Function 0
• DRAM Controller Registers
 Device 1 : Function 0
• PCIe Registers associated with x16 root port
 Device 2 : Function 0, 1
• Integrated Graphics Devices Registers
 Device 3 : Function 0, 1, 2, 3
• Intel Management Engine (ME) subsystem registers
4
Korea Univ
Chipsets
• ICH9 (South Bridge)
 D30:F0
• PCI-to-PCI Bridge Register
 D31:F0
• LPC (Low Pin Count) Interface Bridge Registers
 D31:F2
• SATA (Serial ATA) Controller Registers
 D31:F3
• SMBus Controller Registers
 ….
5
Korea Univ
PCI Express
• 3rd generation high-performance I/O bus
 Used to interconnect peripheral devices
 Point-to-point connection as opposed to bus
 PCIe interconnect consists of either a x1, x2, x4, x8, x12, x16 or x32
point-to-point link
• if you have x16 link, there are 64 physical lines (16 * 2 (both directions)
* 2 (differential signaling))
 1st generation
• ISA, EISA, VESA and Micro Channel buses
 2nd generation
• PCI, PCI-X, and AGP
6
Korea Univ
PCI Express
7
Korea Univ
PCI Bus Based Platform
8
Korea Univ
PCIe-based System Topology
• Root Complex
 Denote the root of
I/O hierarchy that
connects the
CPU/memory
subsystem to the
I/O
 May support one
or more PCIe ports
as shown
• Endpoint
 devices other than
root complex and
switches that are
requesters or
completers of PCIe
transactions
Souce: PCIe specification 2.0
9
Korea Univ
PCIe Example Topology
• Switch
 Can be thought of as consisting of 2 or more logical PCI-to-PCI
bridges
 One port of a switch pointing in the direction of the root complex is
an upstream port
 All other ports pointing away from the root complex are downstream
ports
Souce: PCIe specification 2.0 10
Korea Univ
PCIe Topology
11
Korea Univ
PCIe Address Space
• PCIe supports the same address spaces as PCI
 Memory space
 IO space
 Configuration space
• PCIe provides a 4KB space per a function as opposed to
256B in PCI
• PCIe support up to 256 buses, 32 devices, and 8
functions
12
Korea Univ
PCIe Configuration Registers
13
Korea Univ
PCIe Configuration Registers
14
Korea Univ
PCIe Configuration Registers
15
Korea Univ
PCIe Configuration Registers
• Vendor ID
 Identify the manufacturer of the function
 The value is assigned by a central authority (PCI SIG)
that controls issuance of the numbers
• Device ID
 Assigned by the function manufacturer
 Identify the type of the function
16
Korea Univ
PCIe Configuration Registers
• Class code
17
COM906
Korea Univ
How to Access Configuration Registers?
• In x86-based platform, there are 2 ways to access configuration
registers
 I/O transaction with 0xcf8 and 0xcfc
• PCI compatible configuration mechanism
• 0xcf8 and 0xcfc are IO port addresses implemented within root complex
 It means you have to use “in” or “out” instructions in x86
 0xcf8: Configuration address port
 0xcfc: Configuration data port
18
Korea Univ
How to Access Configuration Registers?
 MMIO (Memory-Mapped IO) transaction
• Each function’s 4KB config. space starts at a 4KB-aligned address
with the 256MB memory space set aside as configuration space
• For example, you can use “mov” instruction in x86 to access the
config. space
19
Korea Univ
PCIe Memory Space
20
Korea Univ
PCIe I/O Space
21
Korea Univ
PCIe Transaction Routing
22
Korea Univ
PCIe Transaction Routing
TLP: Transaction Layer Packet
23
Korea Univ
PCIe Transaction Routing
24
Korea Univ
PCIe Transaction Routing
25
Korea Univ
PCIe Transaction Routing
26
Korea Univ
PCIe Transaction Routing
27
Korea Univ
PCIe Transaction Routing
28
Korea Univ
PCIe Transaction Routing
29
Korea Univ
PCIe Transaction Routing
30
Korea Univ
PCIe Enumeration
• At power up time, the configuration software only knows
of the existence of bus 0
 Bus 0 is the bus that resides on the downstream side of the
Host/PCI bridge
 The configuration S/W does not even know what devices reside
on bus 0
• So… how does the system discover the various buses,
devices, and functions on the computer system?
 Answer: Via the enumeration process
• BIOS is doing the enumeration
31
Korea Univ
PCIe Enumeration
32
Korea Univ
PCIe Enumeration
33
Korea Univ
Example: Before PCIe Enumeration
34
Korea Univ
PCIe Enumeration Process
35
Korea Univ
PCIe Enumeration Process
36
Korea Univ
PCIe Enumeration Process
37
Korea Univ
PCIe Enumeration Process
38
Korea Univ
PCIe Enumeration Process
39
Korea Univ
PCIe Enumeration Process
• ………
40
Korea Univ
Example: After PCIe Enumeration
41
Korea Univ