Hosted @
Supported
by SKA
School of Electrical and Electronic
Engineering; Uni. of Johannesburg
A short course on
FPGA & Verilog
presented by
Dr. Simon Winberg
John-Philip Taylor
Software Defined
Radio Research Group
(SDRG), UCT
Pelindaba Laboratory for
Accelerator and Beam-line
Sciences (PLABS) at NECSA
November 2014
Day #5
Today’s lecture: FPGA Development
Approaches & Product Case Studies
Mission Brief
FPGA manufacturers & specialised types
Other approaches to FPGA programming
DPAS – Quality & Confidence of solutions
FPGA Design Case studies
Code cracking
SKA Digital Back End (DBE)
RHINO platforms
NextRAD – Coastal Monitoring Radar Network
FPGA &
Verilog
define
* Developing a terminology guide basedFPGA
on &
Verilog
literature meta analysis
FPGA application vs.
FPGA platform development
• FPGA platform development =
– Developing an infrastructure using FPGA(s)
– E.g., developing an FPGA development board
• FPGA application development =
Focus of this
short course
– Using an existing platform
– Developing custom hardware and software for
deployment on the platform
FPGA &
Verilog
Reconfigurable Computer &
Reconfigurable Computing
• A reconfigurable computer
• FPGA platform development =
– Developing an infrastructure using FPGA(s)
– E.g., developing an FPGA development board
• FPGA application development =
Focus of this
short course
– Using an existing platform
– Developing custom firmware and software for
deployment on the platform
FPGA &
Verilog
FPGA &
Verilog
FPGA Manufacturers
• The ‘Big 2’ (most commonly used)
– Xilinx : Capital $8.52B, 2984 employees
– Altera : Capital $12B, 2555 employees
• The others pretty big ones…
– Microsemi Corp. / Actel :
$2B Capital, 2250 employees
– Lattice Semiconductor Corp :
$700M capitalizations, 708 employees
Caters for
specific
contexts,
more niche
areas
compared
to the Big2
FPGA &
Verilog
Sources: “100 Power Tips for FPGA Designers”
About the FPGA Families
• Xilinx
– Focusing on highest performance and highest
capacity: Vertex family (e.g. Vertex 7)
– Provides lower-cost options with
high capacity (e.g. Spartan family)
– Range of variations, e.g. low power
options, economy (lower capacity) models.
FPGA &
Verilog
About the FPGA Families
• Altera
– Stratix: higher performance and density models
(e.g. Stratix-V)
– Arria: mid-range, lower-power, but also lower
performance and density compared to Stratix.
– Cyclone: lowest cost option, also aimed at low
power, cost sensitive and mobile applications
FPGA &
Verilog
Altera’s ASIC HardCopy fabrication
• Altera’s ASCI HardCopy service
– Converts a design that works on (certain) of their
FPGAs into an ASIC package (a form that cannot be
altered).
– Benefit to the client by reducing design security risks
and lower costs for higher volume production.
– Design engineers can prototype their designs in Stratix
series FPGAs, and then migrate these designs to
HardCopy ASICs when they're ready for volume
production.
– Design engineers can employ a single RTL, set
of intellectual property (IP) cores, and Quartus II
design software for both FPGA and ASIC
implementations.
FPGA &
Verilog
About the FPGA Families
• Microsemi (previously Actel)
– Focuses on providing the lowest
power, and widest range of small packages
– IGLOO : low power, small footprint, SoC
– SmartFuson : Mixed FPGA and ARM
processor
– RTAX/RTSX : radiation tolerant and very
high reliability
FPGA &
Verilog
About the FPGA Families
• Lattice
– Range of options (low power; high
performance; small package)
– Own specialised development tools
– Lattice iCE family, e.g. iCE40:
A more descriptive
illustration would
be:
• High functional density for the thinnest devices; & very small
• Measuring just 1.40 mm X 1.48 mm x 0.45 mm,
can fit in the most space constrained modules.
– (of these four, this one is the only firms not in
California; they are currently in Oregon)
FPGA &
Verilog
About the FPGA Families
• Others
– Achronix :
• Focusing on building the fastest FPGAs (not
necessarily highest capacity)
– Tabula :
• Unique FPGA ‘SpaceTime’ technology
• Focus: highest capacity and memory capabilities
FPGA &
Verilog
Memory jogger…
Q: What is Xilinx’s highest-capacity FPGA family?
A: Vertex (currently Vertex 7)
Q: Which FPGA manufacturer is focusing on
developing the fastest FPGAs?
A: Achronix
Q: Is the Stratix an Altera or Xilinx FPGA?
A: Altera
FPGA &
Verilog
FPGA &
Verilog
Do you have to use
HDL to program
FPGAs?
FPGA &
Verilog
The answer is:
No!
You don’t have to use HDL (from a users
perspective) as the only means to program
FPGAs. There’s lots of other approaches…
FPGA &
Verilog
An obvious alternative is:
Using the block diagram / schematic visual
editor, available in both Quartus II and ISE.
FPGA &
Verilog
There are some limitations that you can
probably think of…
Solutions such as HDL Coder, which integrates
with Mathworks Simulink and Matlab provides
powerful facilities for visual modelling and
simulation of complex FPGA applications…
But it is very costly.
But there are alternatives…
Text-based solutions are commonly used and
effective… lets look at a few open source
options.
FPGA &
Verilog
Program,
Test on H/W
Place & Route
/ Compile
Synthesis
Requirements
Modeling/
Drawings
Testing the
Model
Simulation &
Verification
Design &
HDL Coding
HDL Tool Flow Options:
Software Defined Radio Group’s (SDRG) view on HDL tool flows
FPGA &
Verilog
Many HDLs abound…
•
•
•
•
•
•
•
•
•
•
•
•
•
Verilog
(similar to C)
SystemVerilog
VHDL (similar to ADA)
AHDL (Altera HDL)
ABEL (Advanced Boolean Expression Language)
MyHDL (a Python based HDL)
MiGen (a Python based HDL)
JHDL (Java HDL)
CUPL (Logical Devices ‘universal compiler for programmable logic’)
Hydra
OptiSDR
Handle-C (a C based HDL)
SystemC (a C based HDL)
… various others…
* Ones I’ll show briefly in a moment
FPGA &
Verilog
Synthesis & Simulation
Most of the digital designs built up of some basic elements or
components (e.g. registers, logic gates, counters, adders, RAM, etc.)
Standard cell library is the collection of these building blocks available to run your
design. These are specific to the PLD / FPGA you are using.
The Synthesis tool:
Inputs HDL; outputs gate level mapping
Does take a bit of computation, but fairly quick compared to other steps
A very complex process: seeing how time and space can be rearranged,
trade-offs made, analyse sequential dependence, identify parallelism,
etc.
From this point the implementation becomes platform dependent
FPGA &
Verilog
Synthesis & Simulation
Simulation:
Generally, the more opportunities to test the design
before committing it to hardware, the better.
Simulation can fit into various stages of a tool flow:
Code
Test
Behavioral simulation
Post-synthesis simulation
Functional simulation – verify that synthesized netlist
matches the behavioural model.
Timing simulation / discrete event simulation
Deployment on hardware
In-circuit verification (might hook up to simulation
/ test vectors)
HDL for Simulation
HDL for Synthesis
Simulation test bench
support –collecting test
vectors, sample signals,
stimulae and expected
responses, etc to test the
design.
FPGA &
Verilog
What tools are in place in the various tool flows out there?
…
FPGA &
Verilog
FPGA &
Verilog
MyHDL Code
Python-based
HDL
Your favorite Text
Editor
Signal traces using
e.g. MatPlotLib
MyHDL
Standard
Python
Shell-type
Interpreter
Interface
Quick Access to
Behavioral
Simulation
MyHDL
Library &
Extensions
Verilog
Generation
Verilog Code
EDA Tool
Xilinx Vivado /
Altera QuartusII etc.
FPGA &
Verilog
MiGen Approach
Python-based HDL generator
Can do quite complex designs without knowing (much) HDL
Similarities to sequencing of MyHDL toolflow;
Highly object-oriented
Powerful language and operator extensions,
encapsulation and manipulation of subsystems /
fragments, command-line interactions and inspection
features…
Concept, design & most code implemented by S. Bourdeauducq*
A collaborative project re use of RHINO with MiGen
MiGen developed by Milkymist M-Labs http://m-labs.hk/gateware.html
FPGA &
Verilog
Hydra* & FYNBOS**
Hydra: A computer hardware description language (CHDL) that
helps you to design digital circuits.
Based on the standard functional programming language Haskell, its
simple modular structure supports everything from small low-level
circuits up to complete computer system designs.
A very quick look…
*Hydra. Lead researcher:
John O'Donnell
Computing Science Department
University of Glasgow, Great Britain
**FYNBOS:
Ms. Jane Wyngaard
PhD Student, RRSG Group
University of Cape Town
http://www.dcs.gla.ac.uk/~jtod/Hydra/
FPGA &
Verilog
Hascal Language
FPGA &
Verilog
Fynbos:
Hydra->HDL Generator
The Fynbos project at UCT provides a new type of fine-grain parallel
computer generator. Generates HDL representation that executes on FPGA
platform.
Hascal
Code
Hydra
Fynbos
HDL
Xilinx
ISE
Hydra parallel machine model
This project is carried out in collaboration with Ms. Jane Wyngaard and
Prof. Mike Inggs from UCT, and with Brian Farrimond from SimCon.
FPGA &
Verilog
OptiSDR
Development of a text-based Domain Specific Language (DSL)
for Software Defined Radio (SDR) - Referred to as SDR-DSL
(OptiSDR)
Building on the Delite
framework.
A collaboration with the
Pervasive Parallelism Lab at
Stanford University
Currently doesn’t provide
FPGA support (this feature
is not yet available in
Delite)
http://stanford-ppl.github.io/Delite/
FPGA &
Verilog
Project by: Lerato Mohapi
FPGA &
Verilog
Developing Correct Solutions
• Development of FPGA applications can
take a significant amount of time…
• But you also need to know that after this
effort your solution is correct.
• But you also need to know that after this
effort your solution is correct (at least
according to the specifications).
• But …
FPGA &
Verilog
Building FPGA applications
• A typical large FPGA project has many
unique characteristics, for instance:
– Non standard hardware (PCB)
– Possible custom-designed processing
elements and CPU
– Various adapted processing blocks (e.g.
changing the interface to modules to make
them connect into a larger design)
– Various protocols, maybe some custom, So…
FPGA &
Verilog
Building FPGA applications
• There are many places that bugs and
design errors / misunderstandings can
creep in
• Generally more so than
– Regular PC-based solutions (use well
understood, mature architecture & tools)
– Embedded platforms (use mass produced,
highly and thoroughly tested microcontrollers,
big user communities).
Which brings me to…
FPGA &
Verilog
DPAS
• DPAS =
Dual Processing And Simulation
FPGA &
Verilog
Dual Processing?
A technique to verify operation
Essentially performing the
same operation twice (if not
more times) on different
platforms (e.g. FPGA and PC to
check for consistency in results).
Often uses correlations.
FPGA &
Verilog
Limitation in Dual Processing?
• Lots; for example processing speed, not
working in real-time (having to use prerecorded data), etc. etc.
• But it can save time and cost.
FPGA &
Verilog
Simulation
• Useful as a means to save time
• Provides ways to run a variety of test
vectors though your design, checking trial
inputs correspond to expected outputs.
• Particularly for fictional testing:
– Can be especially quick and time-saving; e.g.
checking in a few seconds that changes
haven’t broken a previously working
implementation
FPGA &
Verilog
On-hardware testing facilities
• Xilinx ChipScope / Altera SignalTap
FPGA &
Verilog
FPGA &
Verilog
Lots of FPGA Applications
•
•
•
•
•
•
•
•
•
ASIC prototyping
Parallel processing
Computer hardware emulation
High speed Switches
Software defined radio
Cryptography
Medical imagining
‘Glue’ logic in PCB designs
Typically ‘vertical applications’
FPGA &
Verilog
COPACOBANA
A Codebreaker for DES and other Ciphers
Expandable design – motherboard that can take multiple ‘blades’
Spartan-3 XC3S1000*
http://www.copacobana.org/
COPACOBANA: the Cost-Optimized
Parallel COde Breaker
• FPGA-based machine
• Optimized for cryptanalytical
algorithms
• Suited for parallel computation
problems with low communication
requirements.
• DES cracking is very parallelizable:
an exhaustive key search of the Data
Encryption Standard (DES) takes no
longer than a week on average.
• Can be used for problems outside
cryptography.
* Revision 12/2006
FPGA &
Verilog
SKA: Brief Overview
3D artists impression of the eventual SKA South Africa site.
FPGA &
Verilog
SKA:
Brief Overview
The SKA SA array will be the world's largest and most sensitive radio telescope:
about 50x more sensitive, up to 10,000x faster (in survey speed) than the best
radio telescopes currently available.
It will sense radio waves from objects billions of light years away.
Scientists expect the SKA will make new discoveries that we can't even imagine at
present. Maybe they will find extra terrestrial life elsewhere else in the Universe!
Why the name? The collecting areas of all the receivers of the SKA adds up to one
square kilometre – that’s why it is called the "Square Kilometre Array".
The SKA is taking shape from the efforts of many different countries working together
- and to pay for - the SKA. At least 13 countries and close to 100 organisations (2013)
are involved and more are in the process of joining the project.
Find out more on the web at: http://www.ska.ac.za/
FPGA &
Verilog
KAT7 – Built
FPGA &
Verilog
MeerKAT*:
Digital Back End (DBE) Overview
* MeerKAT is a SA lead radio astronomy array,
to Become integrated with the larger SKA.
Information prepared by Francois Kapp, Sub-system Manager: DBE, Francois.kapp@ska.ac.za
FPGA &
Verilog
SKA Digital Backend
Computing
ROACH: reconfigurable open architecture computing hardware
SKA Capacity Building Programme: Offers comprehensive bursaries to students in engineering,
mathematics, physics and astronomy at undergraduate and postgraduate level. Bursary holders benefit
from regular workshops and student conferences, where they interact with the world’s leading
astronomers and scientists.
General contact: amashemola@ska.ac.za or contact SKA CBP affiliates in an area you are interested in.
FPGA &
Verilog
The ROACH Board
ROACH: reconfigurable open architecture computing hardware
Can be obtained from Digicom in the US (Roach 2 and later, can do another run of older versions if you
really want it)
Versions and variants can also be obtained via Tellumat (South African company).
ROACH design in collaboration between SKA South Africa and Casper Berkeley
FPGA &
Verilog
Obtaining a ROACH Board
ROACH: reconfigurable open architecture computing hardware
Can be obtained from Digicom in the US (Roach 2)
Versions and variants can also be obtained via Tellumat (South
African company).
ROACH design in collaboration between SKA South Africa and Casper Berkeley
SKA Capacity Building Programme: Offers comprehensive bursaries to students in engineering,
mathematics, physics and astronomy at undergraduate and postgraduate level. Bursary holders benefit
from regular workshops and student conferences, where they interact with the world’s leading
astronomers and scientists.
General contact: amashemola@ska.ac.za or contact SKA CBP affiliates in an area you are interested in.
FPGA &
Verilog
Reconfigurable Hardware Interface for
computiNg and radiO (RHINO) platform
FPGA &
Verilog
RHINO (version 1) Design Overview
2x 256MB DDR3
SDRAM
2x 128MB DDR2
SDRAM
USB, SD Card,
100Mbps
Ethernet, audio
and video
256MB NAND
Flash
2x CX4 (10Gbps
ethernet)
(RHINO 1.x has no ADC/DAC, this provided
by FMC add-on boards)
FPGA &
Verilog
RHINO: The Board
BORPH boot SD card
4DSP FMC
Sampling
Board
FMC
PIO and
interfacing
expansion
Daughterboard
FPGA &
Verilog
White-RHINO
By: Ojonav Hazarika
(Main supervisor: A Mishra)
Much Un-Used spectrum!
Called ‘Whitespaces’ …
e.g. Transition from
Analog to Digital TV freed
many channels, these are
‘TV whitespaces’
In 2008, FCC was first
organization to make
TV Band spectrum
avail to unlicensed users.
Sharing of Spectrum done
by either spectrum sensing
or a database
management system.
AIM: develop a hardware platform which can operate as Whitespace Communication
node with radar detection as its commensal operation.
Applications ideas: communications, ATC, border monitoring, cognitive radio prototyping
FPGA &
Verilog
NextRAD
NextRAD is a multiband multistatic radar system being developed in collaboration
between UCL in the UK and the RRSG group at UCT in South Africa.
The system is under development, and a first version of prototyped radars,
transmitters and receivers have been built and testing completed.
The aim is towards scaling this system up towards larger applications, such as
coastal monitoring and automated detection of poaching activities in protected areas.
FPGA &
Verilog
FPGA &
Verilog
FPGAs & FPGA Developers
Hopefully, with all the effort that is being applied to the
development of FPGA development tools and reusable, and open,
FPGA designs and platforms, we are getting – at least closer – to
a point where…
FPGA &
Verilog
FPGAs & Engineers will:
Coexist happily!
FPGA &
Verilog
FPGA &
Verilog
Over to John-PhiliP:
VGA Graphics on An FPGA
FPGA &
Verilog
Day 5
TutorialS
FPGA &
Verilog