Paul Schumacher & Pradip Jha
Xilinx, Inc.

Outline
 Motivations
 Estimation Details
 Results, Examples, & Demo
 Conclusions & Future Improvements

The Need for More Information
®
Virtex ®-6
FPGA
Logic Utilization:
Number of Slice Flip Flops: 301 out of 12,288 2%
Number of 4 input LUTs: 900 out of 12,288 7%
Logic Distribution:
Number of occupied Slices: 498 out of 6,144 8%
Total Number 4 input LUTs: 920 out of 12,288 7%
Number used as logic: 900
Number used as a route-thru: 20
Number of bonded IOBs: 21 out of 320 6%
Number of BUFG/BUFGCTRLs: 1 out of 32 3%
Number used as BUFGs: 1
Number used as BUFGCTRLs: 0
Total equivalent gate count for design: 8,944
How are these resources being used?!?

Exemplary FPGA Design Flow
HLL Definition
Optimization
RTL Generation
Synthesis & Simulation
N Constraints met?
Y
Place & Route
FPGA Bitstream
 Issue #1: Perspective
– Overlook vast design space from high level
– Your implementation: very low level
– You need to deftly navigate both levels
 Issue #2: Time
– Designing can be very iterative process
– Performing what if scenarios can be costly
– Possible tradeoffs: speed vs. accuracy

Exemplary FPGA Design Flow
HLL Definition
Optimization
RTL Generation
Synthesis & Simulation
N Constraints met?
Y
Place & Route
FPGA Bitstream
High-Level Estimation
 In-depth information
– Supply perspective desired by designers
– Provide context: where, when, why
 Immediate feedback
– Offer quick estimations
– Increasing benefits with multiple runs

What Do We Have?
PlanAhead™  Provides estimated FPGA resources of RTL designs
– Without running synthesis
– All resources reported
– All FPGA families supported
 Benefits
– Fast : 100x faster than synthesis
– Accurate : 15.2% average error
– Transparent : in default RTL flow
– Useful : help user select part, etc.
 Released with ISE
®
11

Resource Estimation Tool Flow
HDL Source Code
HDL Parser/Elaborator
Design Netlist
Macro-Level
Estimations
PlanAhead
Tool
 User-provided input
– RTL source code
– Settings (e.g., FPGA family)
– Tcl script (batch mode)
Library
Characterization
 Obtain netlist from HDL parser/elaborator
 Estimate each macro in netlist
 Refine using synthesis modeling
Refinements
Estimation Database
 Estimation output
– Interactive database (GUI)
– Report files (XML, Excel)

Benchmark Results
FPGA
Resource
Slices
LUTs
Flip-Flops
BlockRAMs
DSP48s
Run-Time**
Post-Map Estimation
Error (Avg.)*
15.2%
15.6%
11.5%
6.4%
2.2%
17.2 sec
* Using suite of 100 customer designs across three FPGA families
** Run-time includes HDL parser/elaborator + estimation

Estimation Run-Time

Demo: MPEG-4 Decoder

PlanAhead Integration
Resources by Function
Resources by Hierarchy

Results: MPEG-4 Decoder
QCIF CIF 4CIF 720p 1080p
FPGA Family Comparison Memory Comparison
Both experiments performed in less than one minute!

Estimation Use Models
 Early in design: immediate feedback
 Later in design : “hot spot” identification
 Design space exploration (DSE)
 Increased abstraction level
 Design benchmarking & comparison

Conclusions
 Resource estimator integrated into PlanAhead
 Provides detailed analysis of design
– Breakdown of resources by functionality & hierarchy
– Statistics on memories and bit widths
 Future releases
– Improved QoR
– Estimation of other requested design budgets
– Integration with other tools
 Contact us with any questions!
– Email: {paul.schumacher, pradip.jha}@xilinx.com