Astrium Use Case
Workshop - November 2011 - Toulouse
Main Objectives
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Improvement of our skills in HW/SW codesign methods/technologies
Explore and identify the optimal architecture for a given algorithm
How to verify real time determinism ?
How to debug a SoC ?
Definition of the different types of models required at each step of
the design flow
 Evaluation of the use of HW models obtained from a HW design
flow, to be used in computer simulators for the integration and
validation of critical embedded SW. (Representativity improvement
and cost reduction)
 Define an tool-aided flow that helps collaboration between different
teams
 Support to requirements traceability
Workshop - November 2011
Functional Architecture
 Image Processing « starrer »
 Moving objects extraction
 Moving objects tracking
 Lossless compression
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Main
sequence
Current image
N
Initialisation
Static detection
Geometric model
N-1
Current Mask
N
Chips specification
MatLab Models
Image 1000x1000 -> 10000x10000
10 Hz
100Mb/s of telemetry allocation
Chips correlation
Reference mask
N-1
Resampling
Mask Resampling
Model fitting
Geometric model
N
Reference image
N -1 Resampled
Adaptive fusion
 Telemetry bandwidth needs reduction
 Guidance/Navigation/Control
Reference image
N-1
Reference mask
N-1 Resampled
Reference image
N
Reference mask
N
Stabilisation
Geometric model
N
Out image
Workshop - November 2011
N
Main Processing Steps
 Image Registration: computation of the
geometrical model of image distortion thanks to
image correlation and re-sampling,
 Image Fusion: data volume reduction by
eliminating inter-images redundancies.
 Stabilization: compensation for pan and tilt of the
sensor by a new image re-sampling
 Basically, serial processing but pipelining solution
are investigated
Workshop - November 2011
Architectures ciblées
AHB decoder/arbiter
µP + custom HW blocks
SDRAM Controler
LEON 3 CPU
HW in charge of a full transformation
(algorithm step)
Pipelining performed between
SW stages and HW stages
AHB/APB Bridge
IRQ
APB Bus
AHB Bus
Processing Accelerator Interface
PA Register I/F
Bus Error
Read Data I/F
Write Data I/F
Debug Link
PA IRQ
irq
Instruction
TCM
µP
Data
TCM
reg_addr reg_wdata
reg_rdata reg_write
berror
rdata
rvalid rlast
read
wdata wready wlast
Processing Accelerator Core
M
read
Local Bus
M
Local Bus
S
S
S
External
Memory
Controller
Smart
DMA Engine
µP + custom HW operators
S
HW
Engine
HW
Engine
S
External Memory
write
S
write
S
accelerate
SW in charge of the full algorithm by
using shared HW operators to
the processing
Local Bus
Workshop - November 2011
write
Evaluation Criteria (1)
 Design Space Exploration with performance profiling
(functional, resource usage, power consumption, ...)
 HW functions fast prototyping thanks to HLS
 Skeleton generation from IP-XACT Description
 HW/SW co-simulation:
 HW/SW interface validation
 Representative virtual platform for SW development, debug
and validation
 Automatic documentation generation from models (HW
and SW)
 Static and dynamic Analysis methods and tools to check
real time constraints conformance
Workshop - November 2011
Evaluation Criteria (2)
Questions to be answered
 What can be verified and validated at each
abstraction level of modelling (and compliant with
ECSS) ?
 What is the position/role of IP-XACT description
(only for assembling or the Central Data Base of all
the design process)
Workshop - November 2011
Use Case Process
 Algorithm Functional Modelling with Matlab
 Algorithmic C Model (today coded by hand)
 C Model update for HLS usage
 HW/SW partitioning
 Parallelism extraction
 In parallel, developing SystemC/TLM Toolbox (ISS, DMA, Memory
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Controllers, Traffic Generator, Fault Injection Engines)
Automatic generation of SC/TLM & OBSW skeletons & documentation
Coding of the behavioural parts
Using assertion-based verification applied on given IPs
Assembling the Virtual Platform
Real Time SW constraint verification with WCET Tools
Implementing requirements traceability through the overall process
Workshop - November 2011
Thank you for your attention
?
Any questions ?
Workshop - November 2011