International Journal of Engineering Trends and Technology (IJETT) – Volume 18 Number1- Dec 2014
High Efficient Carry Select Adder using Zero
Carry Look Ahead Adder
P.Lavanya1
B.Chinna Rao2
T.Vishnu Murty3
PG Student,
Aditya Institute Of Technology
and Management,Tekkali,
Srikakulam ,A.P, india.
Associate Professor ,ECE Dept
Aditya Institute Of Technology
and Management,Tekkali,
Srikakulam ,A.P, india.
Assistant Professor,ECE Dept.,
Pragati Engineering College,
Suram Palem,Kakinada,EG,AP.
I.
ABSTRACT
Adders are used vastly in digital systems; Carry select
adder is a fast adder, which uses multiple narrow
adders and results fast wide adders. Carry select adders
have great scope by reducing area, power consumption
and delay. The simple and efficient gate level
modification helps to reduce the area and power of
CSLA. In this paper the proposed design of 16bit CSLA
Using ZCLA is compared with modified version of
SQRT CSLA. The result shows that CSLA Using ZCLA
is better than the modified SQRT CSLA. This project
was aimed for reduce the delay which performance
optimized high speed carry select adder architecture.
Keywords: Area efficient, Carry Select Adder (CSLA),
Square-root CSLA (SQRTCSLA), Zero Carry Look
Ahead Adder (ZCLA).
II.
INTRODUCTION
DESIGN of high performance digital adder is an important
requirement in advanced digital processors for faster
computation. In digital adder circuits, the speed of addition
is limited by the time required for a carry to propagate
through the adder. Many different approaches had already
been suggested to improve the performance of the adder.
CSLA Using ZCLA is one among them and is used to solve
the problem of carry propagation delay by independently
generating multiple carries and then select a carry to
generate the final sum. In CSLA Using ZCLA, requirement
of producing two adders and final selection multiplexers
make it consuming more area, even though carry
propagation delay is reduced much.
The CSLA is used in many computational systems to
alleviate the problem of carry propagation delay by
independently generating multiple carries and then select a
carry to generate the sum. However, the CSLA is not area
efficient because it uses multiple pairs of Ripple Carry
Adders (RCA) to generate partial sum and carry by
considering carry input Cin=0 and Cin=1, then the final sum
and carry are selected by the multiplexers (mux). Binary to
Excess-1 Converter (BEC) instead of RCA with Cin=1 in
ISSN: 2231-5381
the regular CSLA to achieve lower area and power
consumption
The basic idea of this work is to use Zero Carry look Ahead
adder (ZCLA) instead of RCA with Cin=0 in the modified
CSLA to achieve High speed. The main advantage of this
CSLA Using ZCLA logic comes from the lesser number of
logic gates than the –bit Full Adder (FA) structure. The
details of the ZCSA logic are discussed in Section IV.
This brief is structured as follows. Section III deals with the
delay and area evaluation methodology of the basic adder
blocks and BEC logic. Section IV presents the detailed
structure and the function of the ZCLA. The SQRT CSLA
Using ZCLA has been chosen for comparison with the
proposed design as it has a less delay, and balanced power
and area. The delay and area evaluation methodology of the
modified SQRT CSLA and modified SQRT CSLA Using
ZCLA are presented in Sections V and VI, respectively.
III.
DELAY AND AREA EVALUATION
METHODOLOGY OF THE BASIC
ADDER BLOCKS
Figure 1: Evaluation of delay and Area for XOR
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International Journal of Engineering Trends and Technology (IJETT) – Volume 18 Number1- Dec 2014
Adder Blocks
Delay
Area
XOR
3
5
2:1 MUX
3
4
3-bit BEC
4
12
Table II: Area and Delay count basic blocks in CSLA
As stated above the main idea of this work is to use BEC
instead of the RCA with Cin=1 in order to reduce the area
and power consumption of the regular CSLA. To replace
the n-bit RCA, an n+1-bit BEC is required. A structure and
the function table of a 4-b BEC are shown in Figure 2 and
Table II, respectively. Figure 3 illustrate how the basic
function of the CSLA is obtained by using the 4-bit BEC
together with the mux. One input of the 8:4 mux gets as it
input (B3, B2, B1, and B0) and another input of the mux is
the BEC output. This produces the two possible partial
results in parallel and the mux is used to select either the
BEC output or the direct inputs according to the control
signal Cin. The importance of the BEC logic stems from the
large silicon area reduction when the CSLA with large
number of bits are designed.
Figure 2: 3-bit BEC
IV.
Table I: the Functional table of 3-Bit BEC
The following Boolean equations for 3-bit BEC
The AND, OR, and Inverter (AOI) implementation of an
XOR gate is shown in Figure 1. The gates between the
dotted lines are performing the operations in parallel and
the numeric representation of each gate indicates the delay
contributed by that gate. The delay and area evaluation
methodology considers all gates to be made up of AND,
OR, and Inverter, each having delay equal to 1 unit and
area equal to 1 unit. We then add up the number of gates in
the longest path of a logic block that contributes to the
maximum delay. The area evaluation is done by counting
the total number of AOI gates required for each logic
block. Based on this approach, the CSLA adder blocks of
2:1 mux, Half Adder (HA), and FA are evaluated and listed
in Table II.
ISSN: 2231-5381
ZCLA
The main idea of this work to reduce the gate delay to use
Zero Carry Look Ahead adder(ZCLA) instead of RCA with
carry in=0,in order to reduce the delay and area of modified
Regular CSLA and modified SQRT CSLA, to replace n-bit
RCA with n-bit ZCLA is required. A structure as show in
Figure 4
Figure 3: 2-bit ZCLA
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International Journal of Engineering Trends and Technology (IJETT) – Volume 18 Number1- Dec 2014
V.
DELAY AND AREA EVALUATION
METHODOLOGY OF MODIFIED 16-BSQRT
CSLA
The structure of the proposed 16-b SQRT CSLA using
BEC for RCA with Cin=1 to optimize the area and power is
shown in Figure 5. We again split the structure into five
groups. The delay and area estimation of each group are
shown in Figure 6. The steps leading to the evaluation are
given here.
1) The group2 [see Figure. 4] has one 2-b RCA which has 1
FA and 1 HA for Cin=0. Instead of another 2-b RCA with
Cin=1 a 3-b BEC is used which adds one to the output from
2-b RCA. Based on the consideration of delay values of
Table I, the arrival time of selection input C1(time (t)=7) of
6:3 mux is earlier than the S3[t=9] and C3[T=10] and later
than the S2[T=4]. Thus, the sum3 and final C3 (output
from mux) are depending on S3 and mux and partial C3
(input to mux) and mux, respectively. The sum2 depends
on C1 and mux.
HA=6(1*6)
AND=1
NOT=1
XOR=10(2*5)
MUX=12(3*4)
BEC (5-BIT) = NOT + AND + XOR = 24
Group
Delay
Area
Group2
13
43
Group3
16
61
Group4
19
84
Group5
22
107
Table III: Area and Delay Count of Modified SQRT CSLA
2) For the remaining group’s the arrival time of mux
selection input is always greater than the arrival time of
data inputs from the BEC’s. Thus, the delay of the
remaining groups depends on the arrival time of mux
selection input and the mux delay.
4) Similarly, the estimated maximum delay and area of the
other groups of the modified SQRT CSLA are evaluated
and listed in Table III.
Figure 4: 16 bit Modified SQRT CSLA,The parallel RCA
with Cin=1 is replaced with BEC
3) The area count of group2 is determined as follows:
Gate count =43(FA+HA+Mux+BEC)
FA=13(1*13)
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International Journal of Engineering Trends and Technology (IJETT) – Volume 18 Number1- Dec 2014
VI.
DELAY AND AREA EVALUATION
METHODOLOGY OF MODIFIED 16-B SQRT
CSLA using ZCLA
B[15:11]
A[15:11]
5 BIT ZCLA
A[10:7]
B[10:7]
A[6:4]
4 BIT ZCLA
6bit BEC
5bit BEC
A[3:2]
B[6:4]
3 BIT ZCLA
2 BIT ZCLA
4bit BEC
3:2RCA
B[3:2]
B[1:0]
2
BIT ZCLA
A[1:0]
1
2
2
10
8
2
MUX
12:6
MUX
12:6
2
6
MUX
12:6
MUX
12:6
C7[11]
C11[14]
C2[5]
C4[8]
COUT
SUM[15:11]
[17]
SUM[10:7]
4
SUM[3:2]
SUM[6:4]
SUM[1:0]
Figure 5: Modified 16-b SQRT CSLA. The parallel RCA with Cin=0 is replaced with ZCLA
The structure of 16-b SQRT CSLA is proposed to used
RCA with Cin=0 for replaced with ZCLA. To optimize the
area and delay is shown in above Figure. 6. We again split
the structure into five groups. The delay and area
estimation of each group are shown in Figure 7. The
following steps clearly explained how to calculate delay
and area count.
1)
The Figure 6 shows that Group1 RCA with
Cin=0 is replaced with ZCLA, estimated time
delay C2 [5] and area count is 19. The below
Boolean algebra is going to explain delay and
area calculations.
P0=A0^B0, G0=A0&B0, S0=P0^C0
delay C4[8] this carry depends upon previous
carry C2[5] and mux delay[3].
3)
The Group3 Figureure 7(b), 3-bit ZCLA followed
by 4-bit BEC this carry C6[11] is depends on
previous carry C4[8] and mux delay[3].
4)
The Figureure 7(c), the group4, 4-bit ZCLA
followed by 5-bit BEC then the delay C10[14]
this carry depends upon previous carry C6[11]
and mux delay[3].
5)
Coming to the group5, in fugure 7 (d) shows as
5-bit ZCLA followed by 6-bit BEC this can be
delay C16[14], this carry depends upon previous
carry C6[11] and mux delay[3].
And C1=G0+ (P0&C0), where C0=0 then S0=P0,
C1=G0, S1=P1^G0 and G1+(P1&G0)
2)
The Figure 7(a) shows that Group 2, 2-bit ZCLA
followed by 2-bit RCA with carry Cin=1 then the
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International Journal of Engineering Trends and Technology (IJETT) – Volume 18 Number1- Dec 2014
design show a decrease for 16-, 32-, and 64-b sizes which
indicates the success of the method and not a mere tradeoff
of delay for power and area. The modified CSLA
architecture is therefore, low area, low power, simple and
efficient for VLSI hardware implementation.
References
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8
51
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Figure 6: Delay and area evaluation of modified SQRT
CSLA ZCLA: (a) group2, (b) group3, (c) group4, and (d)
group5.
VII.
CONCLUSION
This paper reveled that delay of ZCLA in each structure of
the level in a simple approach. The proposed reduce the
delay of SQRT CSLA architecture. The reduced number of
gates of this work offers the great advantage in the
reduction of area and also the total power. The compared
results show that the modified SQRT CSLA has a delay
reduces ( 22.76%), but the area of the 16-b modified SQRT
CSLA are slightly increases by 0.2% . The power-delay
product and also the area-delay product of the proposed
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