Power Delivery Network Optimization
for Low Power SoC
Anil Gundurao
Melinda Yang
Eileen You
Harpreet Gill
System LSI SoC Bay Area R&D
Samsung Semiconductor Inc.
SoC Power Integrity Challenges
 28nm SoC flip chip package
 10M+ instances, 500+ macros
 3 operating voltages
 50+ clock domains
Package
Die
VRM
Decap
Decaps
PCB
 Complexity of simulating PDN
 SoC complexity: Size, Modes/corners, voltage domains
 System complexity: Board and Package
 Early analysis and optimizations
 Model, Analyze and Optimize
 System PI analysis
 Add more detailed models in phases
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Pkg Decap
Early System Model
Signoff Model
Board
Lumped RLC
Full Wave
Package
Lumped RLC
Full Wave
Chip
Chip power model
Physical database
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Generating chip model
 Estimate chip impedance
 Intrinsic and Intentional decap
 Estimate Rdie / Cdie at operating frequencies
Cdie Core
Rdie Core
9
Capacitance
8
Cdie Top
Rdie top
7
6
5
4
3
S
e
r
i
e
s
2
1
0.00E+00
1.00E+01
Operating freq
2.00E+01
3.00E+01
4.00E+01
Frequency
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5.00E+01
R
e
s
i
s
t
a
n
c
e
6.00E+01
Z11 Plots Comparison
Lpkg Cdie
Impedance
Board LC
BoardR
Decap Self-resonance
Frequency
Board + Pkg (embedded decap) + Die
Board + Pkg (substrate only) + Die
Die + Pkg (with embedded decap)
Die + Pkg (Substrate only)
Adding board model changes the Z11 plots
 Impact on time-domain noise depends on freq content

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Understanding Current Signature
 Demand current = f (circuit switching activity)
 FFT (current)
Mode 1
Mode 2
FFT up to 500MHz
Energy concentrated at harmonics of 50MHz
Energy concentrated > 500MHz
FFT up to 3GHz
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Optimization: Impact of PDN components
Adding on-chip decaps
Changing Package model
Adding embedded decaps
Updating board Model
Voltage at Pads




-- Board + Pkg (embed decap)
-- Pkg (no decap)
-- Board+ Pkg (no decap)
-- Pkg (embed decap)
Sim Time
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Impact of On-chip Decap on DvD
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On-Chip Decap & Package Core Thickness Impact
Percentage Instances
(%)
20
NoDECAP
1XDECAP
2XDECAP
6XDECAP
15
10
5
5
10
15
20
25
30
35
40
45
50
55
60
65
70
75
80
85
90
95
100
105
110
115
120
125
130
135
140
145
150
155
160
165
170
175
180
185
190
195
200
205
210
215
220
225
230
235
240
0
DvD
Percentage of Instances
(%)
18.0
16.0
14.0
12.0
10.0
8.0
6.0
4.0
2.0
0.0
Thin Package
Thick Package
50
55
60
65
70
75
80
85
90
95 100 105 110 115 120 125 130 135 140 145
Change in DvD due to Package
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Impact of Package and Board impedance
"Pkg only with Decap"
2.5
2
1.5
Instance Count
(1e6)
3
Board and with Decap
Board with no decap
1
0.5
0
1
3
5
7
9
11
13
15
17
DvD Range
19
21
23
25
27
29
31
33
35
1.05
 Including Board
impedance impacts
DvD results
Instance VDD
1
0.95
0.9
0.85
w/o_DECAP
w_DECAP
w/ PCB
Ideal VDD_CPU
 Having Package/ Board
decaps will also impact
DvD
Time
0.8
0
500
1000
1500
2000
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Summary
 For Power Integrity verification:
 Critical to model all components of the system PDN
 Time-domain and Frequency domain analysis
 Model the system early
 Estimated and lumped models to predict the PDN response
 Use the system model to study effects of different PDN
parameters.
Detailed
DVD
Database
Compare
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