Workshop - November 2011 - Toulouse
Plan
 Socket Process & Airbus application
 First Phase :
 Models Development
 Platform Integration (Hw/Sw)
 Second Phase :
 ISS Open Source alternatives
 Conclusion
Workshop - November 2011
2
Plan
 Socket Process & Airbus application
 First Phase :
 Models Development
 Platform Integration (Hw/Sw)
 Second Phase :
 ISS Open Source alternatives
 Conclusion
Workshop - November 2011
3
SoCKET process
Classical process
 Formalism unification
Co-design process
System Specifications
System Specifications
 Remove any semantics holes
Executable Specification
(system level simulation)
HW/SW
Partitioning
Alternate architectures
exploration
into HW/SW interface
SW Design
HW Simulation
SW Simulation
HW Synthesis
(netlist)
SW Compilation
(code binaire)
Unit Tests
Modules Unit Tests
HW Synthesis
(netlist)
SW Compilation
(binary code)
Equipment Tests
SW Validation Tests
Unit Tests
Modules Unit Tests
Equipment Tests
SW Validation Tests
 Models transformation
operators
 Automation
 Traceability
 Overall coherency insurance
HW/SW
Partitioning
HW Design
 Tools interoperability
 Keystone of 2 previous points
HW/SW Integration
Workshop - November 2011
HW Design
SW Design
HW Simulation
SW Simulation
TO
HW/SW
co-simulation
HW/SW Integration
4
Socket Design Flow
System requirements
System
Properties
Global SoC spec.
Platform
assembly
HW
Properties
IP-Xact
SoC
Functionality
Functionality
+
timing
HLS
SoC
Architecture
TLMLT
Metrics
Requirement traceability
Metrics
HLS
Functional validation
Traffic
generators
Header
generation
C/C++/ASM
Software
SW Performance validation
Software
RTL
Co-simulation/Co-emulation
Software
Silicon
Device execution
Software
TLMAT
Workshop - November 2011
SW
Properties
Instruction Set
Simulator
Socket Design Flow
System requirements
System
Properties
Global SoC spec.
Platform
assembly
HW
Properties
IP-Xact
SoC
Functionality
Functionality
+
timing
HLS
SoC
Architecture
TLMLT
Metrics
Requirement traceability
Metrics
HLS
Functional validation
Traffic
generators
Header
generation
C/C++/ASM
Software
SW Performance validation
Software
RTL
Co-simulation/Co-emulation
Software
Silicon
Device execution
Software
TLMAT
Workshop - November 2011
SW
Properties
Instruction Set
Simulator
Main Topics
• Architecture description (Coware, Magillem)
• Components and platform description
• Code generation (makefile, netlist, etc.)
• SystemC/TLM LT virtual platform evaluation
• Hardware requirement validation
• Early software development
1st Phase
2nd Phase
• Functional safety
• assertion based verification (PSL)
• Monitors/checkers generation (ISIS)
• Certification
• Requirement traceability
Workshop - November 2011
7
Plan
 Socket Process & Airbus application
 First Phase :
 Models Development
 Platform Integration (Hw/Sw)
 Second Phase :
 ISS Open Source alternatives
 Conclusion
Workshop - November 2011
8
st
1
Phase
• Study Case specification
• Coware tool experiment
• SystemC TLM-PV models development
• tsip, sgdma, timer, and uart modules
• ARM Coware/Synopsys cpu model
• Models and virtual platform validation with specific software
• Application software development on virtual platform
Workshop - November 2011
9
st
1
Phase
• Plateform assembly with Coware
Workshop - November 2011
10
st
1
Phase
• Simulation and results
Workshop - November 2011
11
st
1
Phase
• Hardware validation team feedback
• Debug hardware behaviour with software tools
•
•
•
Halt and Resume
• Freeze and Restore real time processing
100% Visibility & Control
• State machines
• Variables
• Buses
Tracing and logging
• Golden Reference Platform
•
Consolidate platform evolution
• Early validation of specifications
Workshop - November 2011
12
st
1
Phase
• Application software team feedback
• Develop & Validate low level software sooner
• Debug software with same tools than real platform
•
•
One time tool ramp-up
Debugging real world “utilities” (parsers, compilers, debugger scripts
...)
• Mixed Hardware/Software Breakpoints
•
•
•
SW : instruction / data | HW : event / signal / bus data
Freeze & Restore real time execution
Get visibility not available on real SoC platform
Workshop - November 2011
13
nd
2
Phase Motivation
 End of Coware tool experiment
 Need to find CPU Model
 Need to find Bus Model
 Need a way to rebuilt the platform
 Need to implement traceability in SystemC models
IP-XACT in the design flow for embedded airborne electronic equipment
development
 Need to add monitors in the platform to increase
safety
ABV in the avionics context: verification of safety requirements
Workshop - November 2011
Plan
 Socket Process & Airbus application
 First Phase :
 Models Development
 Platform Integration (Hw/Sw)
 Second Phase :
 ISS Open Source alternatives
 Conclusion
Workshop - November 2011
15
nd
2
Phase
• Investigation for ARM Coware model replacement
• ISS generator Trap-gen
• TLM2 compatible bus model development
• Magillem tool experiment
• Components IP-XACT description
• Platform Assembly
• Code generation from IP-XACT files
•
•
•
Netlist SystemC
SystemC skeleton compatible with SCML2 Library
Makefile to compile platform
• Traceability
• Safety, SystemC monitors generation with ISIS Tool (TIMA)
Workshop - November 2011
16
nd
2
Phase
SystemCLT Model
SystemC
Skeleton/Makefile
/Netlist
PSL properties
ISIS
Template
JET
Generator
IP-XACT
desc.
Magillem Packager
Monitor/
Generator
IP-XACT desc.
Magillem PLT Assembly
Magillem Generator Studio
Template
JET
Generator
IP-XACT
desc.
SW dev
HAL
debugger
Magillem Register View
Validation
Fonctionnelle
Workshop - November 2011
17
ISS alternative : Investigation
• ISS needs :
• Open source Licence
• Moderate performance
• OSCI TLM2 Sockets
• Low virtual platform integration effort
• Support GDB debugger
• Active devellopement
• Investigations :
• QEMU
• OVP
• ORK1SIM
• TRAP-GEN
Workshop - November 2011
18
ISS alternative : QEMU
 http://wiki.qemu.org/Main_Page
 From ST Webex :
 Major breakthrough with 0.13
 The libqemu.a no longer exists (not built, and API obsolete)
 The License is not clear (GPL/LGPL)
 Memory must be internal to QEMU (performance)
 Wrapping in TLM needs modifications inside QEMU
 Complex TLM platform not easy to connect to QEMU
Workshop - November 2011
19
ISS alternative : OVP
 http://www.ovpworld.org/
 Open Virtual Platform
 A lot of models : ARM, MIPS, PowerPC, SPARK
 Support TLM2 sockets
 Support GDB
 Can boot linux
 Open source models but simulator is only free for non commercial
use.
Workshop - November 2011
20
ISS alternative : Ork1sim
 www.embecosm.com :
 Application note : Building a Loosely Timed SoC Model with OSCI






TLM 2.0: A Case Study Using an Open Source ISS and Linux 2.6
Kernel
Tutorial based on Or1ksim ISS
http://opencores.org/openrisc,or1ksim
Implement TLM2 Sockets
Support GDB remote debugger
Support temporal decoupling
Can boot Linux
Memories inside ISS
Workshop - November 2011
21
ISS alternative : Trapgen
 http://code.google.com/p/trap-gen/
 LGPL open source Licence
 Generate multiple ISS from one architecture specification
Workshop - November 2011
22
ISS alternative : Trapgen
• Generated ISS
• OSCI TLM2 Sockets interface
• Use SystemC scheduler
• OS Emulator (system calls redirection)
• Just in time compilation
• Support interrupt modeling
• Support GDB interface
• Support multiprocessing
• ISS examples : LEON 2/3, ARM 7/9, Microblaze
• Drawbacks :
• No cache or MMU models
• Not a lot of feedback, but active development (LEON3)
Workshop - November 2011
23
ISS alternative : Trapgen
 ARM9TDMI Model Selected
 Source code modification needed
 Interrupts IRQ ,FIQ port activation
 CPU mode changing instruction bug
 Register definition bug
 Generated ISS Interrupt ports uses SystemC/TLM sockets
 Need to modify timer, sgdma irq ports.
 Custom ISS development possible with minimum effort
Workshop - November 2011
24
Plan
 Socket Process & Airbus application
 First Phase :
 Models Development
 Platform Integration (Hw/Sw)
 Second Phase :
 ISS Open Source alternatives
 Conclusion
Workshop - November 2011
25
Global Results
• Productivity gain
• Early hardware architecture validation
• Early software development
• Easy platform duplication and distribution (executable file)
• Complexity management
• Better observability than real platform
• HW/SW CoDebug
• Safety and certification credit improvement (ex : fault injection)
• Virtual Prototyping not Only for SoC technologies BUT also for Embedded
Computer development
• Data perenity
• Use of standard : SystemC/TLM, IP-XACT, PSL
• Potential bridges others languages, as SysML, SystemVerilog
Workshop - November 2011
26
Any Questions ?
Workshop - November 2011
27
SoCKET design flow
System requirements
System
Properties
HLS
HW
Properties
Platform
assembly
Functionality
Functionality
+
timing
HLS
Metrics
TLMLT
TLMAT
RTL
Silicon
SoC
Architecture
IP-Xact
SoC
Requirement traceability
Global SoC spec.
Metrics
Traffic
generators
SW
Properties
Header
generation
Functional validation
SW Performance validation
Co-simulation/Co-emulation
Device execution
Workshop - November 2011
C/C++/ASM
Software
Software
Instruction
Set
Simulator
Software
Software
28
SoCKET design flow
System requirements
System
Properties
HLS
HW
Properties
Platform
assembly
Functionality
Functionality
+
timing
HLS
Metrics
TLMLT
TLMAT
RTL
Silicon
SoC
Architecture
IP-Xact
SoC
Requirement traceability
Global SoC spec.
Metrics
Traffic
generators
SW
Properties
Header
generation
Functional validation
SW Performance validation
Co-simulation/Co-emulation
Device execution
Workshop - November 2011
C/C++/ASM
Software
Software
Instruction
Set
Simulator
Software
Software
29