Lab Report 0
CPE 133 - 15, Fall 2025
Dr. Mona El Helbawy
Arjaneer Samra and Arya Geejo
Block Diagram
Description: This is a 3 single-bit input (A, B, C) circuit that has one single-bit output (Q). The
circuit had been created and verified within Vivado to familiarize with the digital design flows.
The truth table assigns Q as a logic function of A, B, and C. The digital design was synthesized,
simulated, and verified by use of Vivado.
Structural Model
Description: After we've synthesized, the RTL schematic of Vivado verified the circuit structure.
The inputs A, B, and C go into an OR gate and an AND gate, whose outputs go into a final OR
gate that controls Q. This matches the logic we expected from the truth table.
Verification with Simulation
Description: This simulation was carried out for every one of the 8 input combinations of A, B,
and C. The waveform shows the proper output Q transitions for each of the input sets. When
inputs were A=0, B=0, C=1, then output Q = 1, consistent with the truth table. All of the
expected values of Q checked against the truth table agreed correctly.
Source Code
Sim Code