United International University
Department of CSE
Course Code: CSE 1326
Course Name: Digital logic design laboratory
Experiment no. 3
Experiment Name: Implementation of 1 and multi-bit full
Adder
Submitted by:
Name: Jassia Chowdhury Ahona
Student ID: 0112520138
Section: F
Date of Performance: 07-12-25
Date of Submission: 07-12-25
Objective: The goal is to analyze and implement the 1-bit full adder. This
involves determining its truth table and Boolean logic equations, followed by
building the 1-bit circuit using fundamental logic gates (XOR, AND, OR). The
final task is to demonstrate scalability by assembling multi-bit
adders—specifically, a 4-bit adder built from four 1-bit units, two 2-bit units, and
one comprehensive 4-bit unit.
Apparatus/Instruments used in the Lab:
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-​
-​
-​
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Logic gates: AND, XOR, OR
Input pins (A,B, Cin), Output pins (S, Cout)
Wires for Connections
ICs: XOR(7486), AND(7408), OR(7432)
Logism
Theory: 1-bit full adder can add up to 3 binary inputs(A, B and Cin) and it has
two outputs: S , Cout.
Here the Algebraic expression for S and Cout can found by getting the their SOP
from the truth table which are:
Let, A = X, B = Y and Cin = Z
Then,
X
Y
Z
S
Cout
0
0
0
0
0
0
0
1
1
0
0
1
0
1
0
0
1
1
0
1
1
0
0
1
0
1
0
1
0
1
1
1
0
0
1
1
1
1
1
1
S = X'Y'Z + XYZ + X'YZ' + XY'Z'
= X’ (Y’Z + YZ’) + X (Y’Z’ + YZ)
= X’ (Y⊕ Z) + X (Y⊕ Z)’ [(Y ⊕ Z) = A]
= X’A + XA’
=X⊕A
=X⊕Y⊕Z
And;
Cout = X’YZ + XY’Z + XYZ’ + XYZ
= Z (X’Y + XY’) + XY (Z + Z’)
= Z (X ⊕ Y) + XY
By these equation we can see a 1 bit adder needs,​
​
- Two XOR gates
- Two AND gates
- One OR gate
Solution of the mentioned problems:
A(A3, A2, A1, A0) = 10 = 1 0 1 0
B(B3, B2, B1, B0) = 9 = 1 0 0 1
9 + 10 = 19
S(S4, S3, S2, S1, S0) = 19 = 10011
1-bit Full Adder
4 1-bit Full Adders
2 2-bit Full Adders
1 4-bit Full Adder
Discussion:
The simulation confirmed the design, with correct Sum and Carry values observed
for all input combinations, perfectly matching the truth table. Different bit adders
operated properly due to the successful carry-out changes in different stages of the
circuit. Consequently, the experiment provided a deep understanding of binary
addition and the functional logic of full adders in digital circuits.
.