# Document 17809968 ```Design a non-inverting tri-state buffer
out of PMOS and NMOS transistors.
2. Multiple Choice
a. A 6-bit 2’s complement number can represent values
from _________ to _________.
b. ______ is the only negative value that has the same 3-bit
representation as both a signed magnitude and 2’s
complement number.
c.
A 6-input NAND gate has ____________ minterms
d. If F=∑A,B,C,D (0,2,3,4,5) then F has __________ maxterms.
e. DRAM and SRAM both are volatile / are dynamic / store
their data in a capacitor.
2. Multiple Choice
f.
Write 23.36 as a decimal number: _____________.
g.
When comparing a 32-bit ripple-carry adder and a 32-bit
adder to have more / less / exactly the same delay and use
more / fewer / exactly the same number of gates.
h.
Say you want to develop an encoding that allows you to send
2-bit messages (one of {00,01,10,11}) over a wire. Say you
wish to encode that information so that one bit of error can
be detected. How many bits would you need, at a minimum,
to encode each of these messages allowing for one bit of
detection? 3 / 4 / 5 / 6 / 10
i.
If A↑B=C and B↑C=A then ↑ is the Boolean operator OR /
AND / NOR / NAND/ XOR.
A
B
C
D
E
F
A
B
C
D
X=((A*B)+(C*!B))⊕(D*E)
Y=A+B+C
A common task is to count the number of 1s in a string. Let X[6:0] be the input and C[2:0]
be the output. C should be the number of 1s in X. So if X=”1100011” C should be “100” or
4 because there are 4 1s in X.
Design a circuit which computes C given X. You may only use the following components: 1bit full adders, 2-to-4 decoders, 2-to-1 MUXes and 3-input AND gates. To get full credit, you
must use as few devices as possible. Any solution that uses more than 10 devices will get
zero points.
Using a K-map find all the minimal sum-of-rpodcuts of F= Σ(PQRS) (1,2,4,5,6,7,8,9,10,12,13,14).
Place a star (*) next to each distinguished 1 in your K-map.
Using only standard gates (AND, OR, NOT, XOR), D flip-flops and bubbles as well as a single up
counter with a synchronous reset, design a device which generates a clock with 12 times the
period of the input clock and has a duty cycle of 1/3. The output should be glitch free and