EC311: Introduction to Logic Design
Combinational Logic:
Digital Arithmetic
Prof. Tali Moreshet
FIGURE 4.1
Block diagram of combinational circuit
1
Combinational Logic Analysis Procedure
1. Label gate outputs with intermediate node labels
2. Going from inputs to outputs, determine the Boolean
function for each of the nodes
Modified FIGURE 4.2 Logic diagram for analysis example
T4
T5
T6
2
A
B
C
F2
F2’
T1
T2
T3
F1
0
0
0
0
1
0
0
0
0
0
0
1
0
1
1
0
1
1
0
1
0
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
1
0
0
0
1
1
0
1
1
1
0
1
0
1
1
0
1
1
1
1
0
1
0
1
0
0
0
1
1
1
1
0
1
1
0
1
Combinational Logic Design Procedure
1. Determine and label inputs and outputs
2. Obtain truth table for the outputs as a function
of the inputs
3. Derive Boolean logic expression for each output
4. Simplify via Boolean algebra or K-maps
5. Describe the circuit via Logic diagram or Verilog
6. Verify the design manually (by comparison to truth
table) and/or via simulation
3
Adders
• Half Adder (HA) – a combinational circuit that
– Adds two 1-bit inputs
– Outputs 1-bit sum and 1-bit carry-out
(or a 2-bit sum)
• Full Adder (FA) – a combinational circuit that
– Adds two 1-bit inputs and a 1-bit carry-in
– Outputs 1-bit sum and 1-bit carry-out
(or a 2-bit sum)
4
FIGURE 4.5
FIGURE 4.8
Implementation of half adder
Implementation of full adder with two half adders and
an OR gate
5
FIGURE 4.11
Logic diagram of carry lookahead generator
FIGURE 4.12
Four-bit adder with carry lookahead
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FIGURE 4.13
Four-bit adder–subtractor (with overflow detection)
Table 4.5
Derivation of BCD Adder
7
FIGURE 4.14
FIGURE 4.15
Block diagram of a BCD adder
Two-bit by two-bit binary multiplier
8
FIGURE 4.16
Four-bit by three-bit
binary multiplier
Mult 4-bit B by 3-bit A
FIGURE 4.17
Four-bit magnitude comparator
XNOR
9