VLSI DESIGN
Lab Report
Lab 7
Group 1:
Bheesetti Chaitanya
2022H1230195H
Abhishek Shrivastav
2022H1230192H
Aim:
Design and implementation of ripple carry adder (RCA):
1. Implement a full adder using AND, OR and NOT gates only.
2. Add seven 4-bit numbers (X0 to X6) using CSA scheme
Tools Used:
Xilinx Vivado
Observations:
1.) Implement a full adder using AND, OR and NOT gates only.
Code:
Test bench:
Results:
2.) Add seven 4-bit numbers (X0 to X6) using CSA scheme
Code:
TEST BENCH:
SCHEMATIC:
Results: