EE241 - Spring 2013
Advanced Digital Integrated
Circuits
Lecture 6: Delay Models
Announcements
Homework #1 posted
Due February 25
Project teaming by January 20
Title
½ page description
5 references
Project web page – e-mail me the link
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Assigned Reading
K. Bernstein, et al, “High-performance CMOS variability
in the 65-nm regime and beyond” IBM J. on R&D, 2006.
Review SRAM design form EE141
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Outline
Last lecture
Transistor on-currents and leakage
This lecture
Delay modeling
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2
C. Transistor C-V
MOS Transistor as a Switch
Discharging a capacitor
• Can solve:
vGS
+
iDS v
DS
-
iDS iDS v DS
C
iDS C v DS
• Prefer using equivalent resistances
t pHL
• Find tpHL
• Find equivalent C, R
dv DS
dt
C (v
)d v
iDS DSvGS,v DSDS
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3
MOS Capacitances
Gate capacitance
Non-linear channel capacitance
Linear overlap, fringing capacitances
Miller effect on overlap, fringing capacitance
Non-linear drain diffusion capacitance
PN junction
Wiring capacitances
Linear
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Gate and Drain Capacitances
Gate capacitance
Drain capacitance
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4
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Gate Capacitances
Gate capacitance is non-linear
First order approximation with CoxWL (CoxL = 1.5fF/m)
Need to find the actual equivalent capacitance by
simulating it
Since this is a linear approximation of non-linear
function, it is valid only over the certain range
Different capacitances for HL, LH transitions and power
computation
Drain capacitance non-linearity compensates
But this changes with fanout
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5
D. Gate Delays
MOS Transistor as a Switch (EECS141)
Traversed path
C
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MOS Transistor as a Switch (EECS141)
Solving the integral:
with appropriately calculated Idsat
Averaging resistances:
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CMOS Performance
Propagation delay: t pHL ln 2ReqnC L
t pLH ln 2ReqpC L
ln2 = 0.7
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Switching Trajectory
6.0E-04
5.0E-04
4.0E-04
IDS[A] 3.0E-04
2.0E-04
1.0E-04
0.0E+00
0.2
0.4
0.6
0.8
1.0
VDS[V]
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Effective Current
Ion(VDD) is never reached
Define Ieff = (IH + IL)/2
IL = IDS(VGS=VDD/2, VDS=VDD); IH=IDS(VGS=VDD, VDS=VDD/2),
Na, IEDM’2002
Von Arnim, IEDM’2007
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Switching Trajectory - NAND
6.0E-04
5.0E-04
4.0E-04
IDS[A] 3.0E-04
2.0E-04
1.0E-04
0.0E+00
0.2
0.4
0.6
VDS[V]
0.8
1.0
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Effective Current in Stacks
Add linear current, I3
Von Arnim, IEDM’2007
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Calibrating Delays
Accurate delay model needs to incorporate:
Slope effects
Non-linear capacitive loading
Signal arrival times
Wire models
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FO4 Inverter Delay
In
Shapes the
input slope to FO4
tp
FO4 load
Suppresses Miller
kickback
Horowitz, IEEE Micro1/98
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Input Slope Dependence
I out CL
dVout
I NMOS I PMOS
dt
One way to analyze slope effect
Plug non-linear IV into diff. equation and solve…
Simpler, approximate solution:
Use VThZ model
From Elad Alon
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Slope Analysis
For falling edge at output:
For reasonable inputs, can ignore IPMOS
Either Vds is very small, or Vgs is very small
So, output current ramp starts when Vin=VThZ
Could evaluate the integral
Learn more by using an intuitive, graphical approach
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Slope Dependence
Iout ramps linearly for
VThZ<Vin<VDD
Constant once Vin =VDD
CL integrates Iout
VThZ<Vin<VDD: Vout quadratic
Vin = VDD: Vout linear
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Slope Dependence (2)
Consider step input
whose output crosses
VDD/2 at same time
Vout set by charge
removed from CL
Need to make
QR = QS
Step has to shift to when
Iout=IDSAT/2
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Slope Dependence (3)
To find Δtslope:
Find Vin when Iout = IDSAT/2
(Vhalf)
And use input tr
IDSAT α (VDD-VThZ):
Vhalf – VThZ = VDD/2 – VThZ/2
Vhalf = (VDD+VThZ)/2
So Δtslope = (VThZ/2)/kr
kr = VDD/(2*tp,in)
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Result Summary
For reasonable input slopes:
For tp,avg, VThZ is (VThZN + VThZP)/2
VThZ/VDD typically ~1/3-1/2 at nominal supply
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Model vs. Spice Data
For reasonable
input slope
Model matches
Spice very well
Model breaks with
very large tr
Input looks “DC” –
traces out VTC
Have other problems here anyways
Short-circuit current
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E. Standard Cells
Standard Cell Library
Contains for each cell:
Functional information: cell = a *b * c
Timing information: function of
input slew
intrinsic delay
output capacitance
non-linear models used in tabular approach
Physical footprint (area)
Power characteristics
Library
Wire-load models - function of
Block size
Fan-out
K. Keutzer, EE244
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Synopsys Delay Models
Linear (CMOS2) delay model
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Example Cell Timing
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Cell Characterization (Linear Model)
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Synopsys Nonlinear Delay Model
Delay is a function of:
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Synopsys Nonlinear Delay Model
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