EE241 - Spring 2011
Advanced Digital Integrated
Circuits
Lecture 6: Gates and Timing
Outline
Last lecture
Leakage currents
This lecture
Capacitances
Gate delays
Static timing
Reading: Papers from the website
2
1
Transistor C-V
MOS Transistor as a Switch
Discharging a capacitor
• Can solve:
vGS
iDS  iDS  v DS 
+
iDS v
DS
-
C
iDS  C  v DS 
• Prefer using equivalent resistances
t pHL 
• Find tpHL
• Find equivalent C, R
dv DS
dt
C (v
)d v
 iDS DSvGS,v DSDS
4
2
MOS Capacitances
Gate Capacitance
p
Overlap Capacitance
CGSO = CGDO
= CoxxdW
= CoW
(often lump fringe cap
into it)
5
MOS Capacitances
Gate capacitance
Non-linear channel capacitance
Linear overlap, fringing capacitances
Miller effect on overlap, fringing capacitance
Non-linear drain diffusion capacitance
PN junction
g capacitances
p
Wiring
Linear
6
3
Gate-Channel Capacitance
G
G
CGC
CGC
D
S
G
Cut-off
CGC
D
S
Resistive
CGB
D
S
Saturation
CGS
CGD
+ overlap
7
Gate and Drain Capacitances
Gate capacitance
2.0E-15
0.13um Cgs/um vs. Vgs
1.8E-15
1.6E-15
1.4E-15
1 2E 15
1.2E-15
Cgs [F]
1.0E-15
8.0E-16
6.0E-16
NMOS VDS=VDD
PMOS VDS=VDD
4.0E-16
NMOS VDS=0
2.0E-16
Vgs [V]
PMOS VDS=0
0.0E+00
0.0
0.4
0.8
1.2
Drain capacitance
1.8 0E -15
1 6 0E -15
1.6
15
Cd
db (F)
2.0 0E -15
0.13um Cdb/um vs . V ds
N MOS VGS=0
PMOS VGS =0
1.4 0E -15
1.2 0E -15
1.0 0E -15
8.0 0E -16
6.0 0E -16
4.0 0E -16
2.0 0E -16
V d s (V )
0 .0 0E +00
0.0
0.4
0 .8
1.2
8
4
Gate Capacitances
Gate capacitance is non-linear
First order approximation
with CoxWL ((CoxL = 1.5fF/m)
pp
 )
Need to find the actual equivalent capacitance by
simulating it
Since this is a linear approximation of non-linear
function, it is valid only over the certain range
Different capacitances for HL,
HL LH transitions and power
computation
Drain capacitance non-linearity compensates
But this changes with fanout
9
Gate Capacitance vs. VTh, VDD
Nose, Sakurai, ISLPED’00
10
5
Gate Capacitance with Scaling
High-k allows for EOT scaling,
increases Cgate
But some of it is masked by
fringe/overlap caps
Scaling advantage
Transconductance increases
If fringe cap can be controlled, win on
power
11
Gate Delays
6
MOS Transistor as a Switch (EECS141)
Traversed path
C
13
MOS Transistor as a Switch (EECS141)
Solving the integral:
with appropriately calculated Idsat
Averaging resistances:
14
7
CMOS Performance
Propagation delay: t pHL  ln 2ReqnC L
t pLH  ln 2ReqpC L
ln2 = 0.7
15
Inverter Switching
1200
1000
IDS [uA]
800
600
400
200
0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
VDS [V]
16
8
Effective Current
Ion(VDD) is never reached
Define Ieff = (IH + IL)/2
IL = IDS(VGS=VDD/2, VDS=VDD); IH=IDS(VGS=VDD, VDS=VDD/2),
Na, IEDM’2002
Von Arnim, IEDM’2007
17
NAND – Bottom/Top Switching
1200
1000
IDS [uA]
800
600
400
200
0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
VDS [V]
18
9
Transient NAND NMOS Trajectories
Ids
9
o and + are spaced out at the
same time interval 1ps
Rise time from inverter FO4
FO1 at output
x 10 -5
8
7
bottom
0.5
top
0.6
0.7
0.8
6
0.9
5
1
fast
4
1.1
1.2
3
2
1
0
0
0.2
0.4
0.6
0.8
1
1.2
1.4
Vds
19
Calibrating Delays
Accuracy can be improved by including:
Slope effects
Non-linear capacitive loading
Signal arrival times
Wire models
20
10
FO4 Inverter Delay
In
tp
Shapes the
input slope to FO4
FO4 load
Suppresses Miller
kickback
[Harris, Horowitz]
21
Input Slope
Simulated vs. linear model
70
8
4
1
60
Delay [ps]
D
50
Driving gate
fanout
40
30
tp = p + gfi + sfi-1
20
10
0
0
2
4
6
FanOut
8
10
22
11
Input slope
We can model the delay as tp = 0.7*RekvC
When driving with non-step input, the rise/fall time is absorbed
i t Rekv
into
Rekv is different than one extracted straight from I-V
The output delay is linearly dependent on input
rise/fall time tp = 0.7RC + tr/f
 = 0.17 in this example (~1/6)
The model is limited to a range of fanouts
More accurate delay models propagate two
quantities: delay and signal slope
Both can be modeled either as linear or table lookups
23
Standard Cell Library
Contains for each cell:
Functional information: cell = a *b * c
Timing information: function of
input slew
intrinsic delay
output capacitance
non-linear models used in tabular approach
Physical footprint (area)
Power characteristics
Library
Wire-load models - function of
Block size
Fan-out
[from K. Keutzer]
24
12
Synopsys Delay Models
Linear (CMOS2) delay model
25
13