1. For the transistors in this question, assume 𝑉𝐷𝐷 = 1.8V, 𝜇𝑛 𝐶𝑜𝑥 = 100 µA∕𝑉 2 , 𝜇𝑝 𝐶𝑜𝑥 = 50 µA∕𝑉 2 ,
𝑉𝑇𝐻,𝑁 = 0.4 V, 𝑉𝑇𝐻,𝑃 = -0.5 V, 𝜆𝑁 = 𝜆𝑃 = 0.
a. In the inverter of Fig. 1, the output low level must remain below 100 mV. If (𝑊/𝐿)2 = 3∕0.18 µm,
determine the minimum required width of M1 in case 𝐿1 = 180 nm. Find the static power
consumption of the inverter in case where 𝑉𝑂𝐿 = 100 mV.
VDD
M2
Vout
Vin
M1
b. Using the device sizes found in a., find the voltage transfer characteristic of the inverter.
2. A large capacitance 𝐶𝐿 = 3 pF is needed to be driven from a minimum size inverter with an input
capacitance 𝐶𝑖𝑛 = 12 fF and propagation delay of 75 ps. In order to drive the capacitance, a twostaged buffer as shown in Fig. 2 is introduced.
a. Assuming that the input capacitance of an inverter is proportional to its size, determine the sizes of
buffer stages that minimizes the propagation delay.
b. Add any number of stages to achieve minimum delay. How many stages would you insert? What is
the resulting propagation delay?
c. Compare the two methods.
3. Using the device model for 𝑉𝐷𝐷 = 1.8V, 𝜇𝑛 𝐶𝑜𝑥 = 100 µA∕𝑉 2 , 𝜇𝑝 𝐶𝑜𝑥 = 50 µA∕𝑉 2 , 𝑉𝑇𝐻,𝑁 = 0.4 V, 𝑉𝑇𝐻,𝑃 =
-0.5 V, 𝜆𝑁 = 𝜆𝑃 = 0, 𝑉𝐷𝑆𝐴𝑇𝑛 = 0.63 𝑉, 𝑉𝐷𝑆𝐴𝑇𝑝 = −1 𝑉.
Assume 𝐶𝑖𝑛 is not related to size (which is not the case for real devices) and equal to 12 fF for
simplicity.
Design the CMOS inverter that achieves the propagation delay figures in Q.2.