Electric-Electronics Engineering
Department
EEM/EEE 410 (01)
Integrated Circuit Design
By
Assistant Prof. Dr.
Gülşah DEMİRHAN AYDIN
Assignment 1:
Standard Cell Design
Due to be submitted to ÖYS by March 22nd 2024 11:55 pm
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TABLE OF CONTENTS
1. INTRODUCTION
................................................................................................................................................. 3
2. STANDARD CELL DESIGN
................................................................................................................................... 4
2.1. Standard Cell Design Concept
.................................................................................................................. 4
2.2. Standard Cell Layout for an Inverter
........................................................................................................ 4
2.3. 2-Input AND Design Using Standard Cells
................................................................................................ 5
3. DC SWEEP ANALYSIS
......................................................................................................................................... 7
4. TRANSIENT ANALYSIS
......................................................................................................................................10
Back-Annotation of Parasitics
.........................................................................................................................11
5. POWER DISSIPATION ANALYSIS
......................................................................................................................12
6. An Alternative Way for Digital Circuits Simulation
.........................................................................................13
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1. INTRODUCTION
The following aspects of VLSI design will be explored in this exercise, along with the corresponding
capabilities of Electric VLSI Design System CAD tools:
Chapter 2: Standard Cell Design using 2 input AND gate as an example
Chapter 3: Inverter and AND Gate DC Analysis
Chapter 4: AND Gate Transient (AC) Analysis
Chapter 5: AND Gate Power Dissipation Analysis
You will document, and electronically submit a subset of your work. Follow the directions carefully in
order to make sure you are not missing any portion of your submission.
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2. STANDARD CELL DESIGN
2.1. Standard Cell Design Concept
Today’s digital VLSI designs are composed of millions of logic gates, which corresponds to billions of
transistors. Designing such a complex machine on a time schedule requires that design libraries are built
and utilized heavily for digital design so that common gates or blocks can be repeatedly instantiated.
Therefore, all the common cells should be designed in such a way that they can be used in many different
parts of the design. Along with the standard cell library use, there arises the need to fully characterize
the AC and DC characteristics of any given cell, and generate a known specification for the design cell
under well-defined environmental and loading conditions. In this CAD assignment we will provide a
flavor of the standard cell design process by considering a 2-input AND gate as an example. Although
temperature and supply voltage will be fixed in these exercises, keep in mind that in a full
characterization flow, thermal and supply fluctuation events are also included.
The determination of the location of the building blocks in the chip is called "placement".
Interconnecting their I/O and power terminals is called "routing". Both placement and routing are very
important in digital design, and directly impact the area and speed. Therefore, care must be taken in
these design steps. One needs to place and route a number of primary or primitive gates (like inverters,
nand/nor gates) in order to build complex circuits (like counters, ALUs, etc.). It is possible to place
digital gates in a number of ways, but the simplest method involves connecting all the gates in the same
row. In other words, digital gates will be placed next to the others in the same row. A number of
requirements should be satisfied in doing this:
➢ The heights of the cells should be exactly the same. Typically one would build minimum sized
cells for minimum loads. One would then add scaled-up versions of such libraries to larger sizes
for driving large fanout and/or long interconnect, but we will not be concerned about these
alternate cells. The width of the cells in any given library will vary. For simple circuits, width
will be small, and for complex circuits it will be wider.
➢ When we place the circuits next to another, we want their power lines (VDD and GND) to be
continuous. The height of these lines should therefore be same and they should cover all the
width of the cell.
➢ Substrate and nwell contacts are often placed under VDD and GND lines. This method
decreases the minimum width of the cell, and may provide better biasing of the substrate and
the nwell. If we place two cells next to the other, the layout of each should ensure no layout rule
violation occurs.
2.2. Standard Cell Layout for an Inverter
The Cadance tutorial document and the example of a 180 nm standard cell layout is for an inverter, as
depicted in Figure 2-1. The sizes of the transistors are given as followings: for PMOS W= 600 nm and
L=180 nm and for NMOS W=240 nm and L=180 nm (it makes inverter nearly symmetric). The
following are the layout guidelines. Keep in mind there is not a single way to build a standard cell
library, and the guidelines may vary depending on the overall strategy. The most important aspect is to
be consistent from one cell to another.
➢ The height of the cells in the library will be fixed at 7 μm (as measured from the upper edge of
top NWELL to the lower edge of bottom M1 line). This sets the vertical pitch for all standard
library components that will share the same row with this inverter. Although the width of the
inverter shown in the figure is 2 μm (set by the width of the NWELL), it should be noted that
NWELL layer and the PIMP/NIMP layers can run over the edges of the layout when this cell
is instantiated in the final full layout design. When another cell is inserted next to this one, these
layers may be continuous, and possibly overlapping with the same layer in the neighboring cell,
as long as there is no other DRC error.
➢ The substrate and nwell contacts have been placed under VDD and GND lines.
➢ The width of the power lines is non-minimum, at 0.8 μm. Layout with wide power lines is a
common practice in order to minimize resistive (IR) drops and other failures in supply voltage
rails. The power lines extend across the whole width of the layout. By convention, use the upper
power line as VDD and lower one as GND.
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➢ In this example you will find few contacts have been used (as many as layout rules allow)
between subsrate/NWELL and MET1 (Metal 1) in order to decrease the overall contact
resistance. In general as many contacts as possible should be used.
➢ The I/O pins should use MET2 (Metal 2) in order to enable ease of connection to the pins from
outside.
➢ The poly length is minimized in order to reduce the resistance of input routes.
Figure 2-1 Standard inverter cell layout in 180 nm with 7 μm height for a minimum sized cell library.
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2.3. 2-Input AND Design Using Standard Cells
Figure 2-2 depicts the layout of a 2-Input AND gate, which is built by instantiating both in schematic
editor and layout editor two different standard cells, a 2-Input NAND and an Inverter. Although the
widths of the cells are different, the cell heights and the power line heights are the same, providing
continuous power line connection. The width of the NAND (3 μm), and the Inverter (2 μm) are set so
that when the two cell layouts are placed next to each other, as shown, no DRC violations occur e.g.
NPLUS areas need to be spaced by a minimum of 0.44 μm. Note content of the instantiated cells can be
hidden in layout view (Figure 2.2. left) using Ctrl-F key combination, and displayed (Figure 2.2. right)
using Shft-F.
I/O PINS: In order to connect I/O pins of different cells, one should take connection outside of the pixel.
Since the upper and lower borders of the cells are covered by MET1 (VDD and GND lines), it is a
common practice to take the connections outside of the pixel using MET2 with vertical lines. Assuming
the cells are connected in a single row, vertical lines will be MET2, and horizontal lines will be MET1.
This method solves all the routing problems as you will discover by experience. In this example all pins
and interconnects between the two cells, including MET1 and MET2 layers, have 0.34 μm (nonminimum) width.
Figure 2-2 2-Input AND layout using standard NAND and Inverter cells – top level instantiation,
interconnect, and pinout (left), and the same with all layers displayed (right).
P1:
i. Complete standard cell schematic design, and layout of the 2-Input NAND and the Inverter
discussed in this chapter, carefully following the described guidelines. Use the cells to build a 2Input AND gate in both schematic and layout, by instantiating them. Finish the interconnection,
again following the metal layer use guidelines as described. Keep in mind both NAND2 and
Inverter should be designed to have similar tPHL and tPLH characteristics.
ii. Include the pictures for all of your cell schematic and layout views. Measure to verify, and
report the vertical and horizontal dimensions for each of the three cells (Inverter, NAND, AND).
iii. Submit tool execution results to show your final AND layout is clean to both DRC and LVS.
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3. DC SWEEP ANALYSIS
DC sweep is an analysis type for simulating DC response of the circuit for different input signals. These
simulations are used to simulate input/output characteristics of the circuits. For instance, this Chapter
will review the simulation of the voltage transfer characteristics of the inverter. The main steps are the
same as in the transient simulation. Figure 3-1 provides the test bench for the inverter designed as a
standard cell.
Figure 3-1 Inverter Test Bench Circuit for DC Sweep Simulations
➢ Open ADE XL and choose the analysis type from the Analysis > Choose. Select dc from the
Analysis options. Upon pressing the dc, the popup window will be enlarged.
➢ Select Component Parameter under the Sweep Variable menu. Then the window will be
enlarged again.
➢ Press Select Component, go to the schematic window, and click the source component that you
want to sweep (V1 is input source in our case). Upon pressing the input DC source a list will
appear.
➢ Select dc (first line) in that list. Now the DC sweep source and its parameter type have been
successfully selected.
➢ Enter the start and stop points from the Sweep Range.
➢ Select linear sweep mode from the Sweep Type and enter step size (0.05 is enough).
➢ Enter OK from the top menu of this popup window. Figure 3-2 shows the popup window that
you will fill out.
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Figure 3-2 Analysis pop-up window filled in for DC sweep.
➢ Select the outputs you want to observe (input and output in this case). Finally, run the simulator.
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➢ At the end of the simulation you should see two graphs plotted with respect to Vin voltage (V1).
One is the desired output (Vout vs Vin) voltage, and the other one is the input voltage (Vin vs
Vin). For a fully symmetric inverter, the intersection point will be at Vin=Vdd/2.
➢ Figure 3-3 depicts the final DC simulation result for the inverter standard cell design discussed
in Chapter 2.
➢ Note by right-clicking on the legend on top of the simulation window, you can change the graph
properties, colors, etc.
Figure 3-3 Voltage transfer characteristic of the inverter designed in Chapter 2.
P2:
i. Complete a DC sweep analysis for the inverter you previously designed to plot the voltage
transfer characteristics. Submit your plot in the report.
ii. Complete a DC sweep analysis for each of the inputs of the 2-Input AND gate by building a
similar test bench for this circuit. Fix one of the inputs (at VDD) while you are linearly ramping the
other input as you did for the inverter. Submit your simulation plot. Explain, based on your
observed simulation result, if the AND gate will be expected to have a symmetric noise margin
between high and low (or if the rise and fall times are expected to be equal).
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4. TRANSIENT ANALYSIS
Use the test bench shown in Figure 4-1 to simulate the 2-input AND gate you designed in Chapter 2.
Utilize the vpwl (from analog library), a piecewise linear voltage source, at both inputs in order to
capture all high-to-low and low-to-high transition scenarios. In the test bench, set rise time to 20 ps at
the inputs, voltage supply of 1.8 V, and output load of 5 fF.
Figure 4-1 Test bench schematic for 2-Input AND detailed transient analysis.
Measure tpHL and tpLH for relevant combinations of input vector transitions, shown in Table 4.1. Use the
“Create Marker” (red flag) button in top menu or under “Marker” selection. Create a vertical marker
and position it by dragging to 50% of the input signal. Then hit ‘d’ for delay, and position the new cursor
to 50% of the corresponding output signal for each transition in the Virtuoso waveform window. If you
select Window>Assistants>Marker ToolBox, you can easily drag cursors to measure all delays of
interest and then Window>Assistants>Vert Marker Table will print all measured delays into a table at
the bottom. Using this method, fill in Table 4.1 by filling in the column for your delay results. Make
sure your simulation timing allows the output signal to be fully transitioned before the next input
transition starts. Otherwise, your measurements may be inaccurate for full swing signals.
P3:
i. Are the measured differences in timing consistent with your expectations? What happens when
both inputs transition to 0 together? What happens if one of the inputs transition to 0 while the
other is 1, and vice versa? What are the worst case tPHL and tPLH? What is the worst case
propagation delay, tpd?
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ii. After you mark different scenarios in your waveform, submit the filled version of Table 4.1 to
demonstrate your results, together with the schematic or drawing that shows the connectivity
between inputs A and B and particular MOSFETs. Make sure you comment on the results.
Back-Annotation of Parasitics
You can always back-annotate the parasitic R, C, L values from layout to schematic in order to get a
more accurate idea of the performance. First, follow through the relevant sections of CAD Assignment
1 in order to generate an “av_extracted” (parasitic) cell view for the 2-Input AND gate. Go to “Launch”
menu > “Parasitics” in the 2-input AND schematic. A new menu item named “Parasitics” will appear
on top. Select “Parasitics” → “Setup”. Make sure under extracted cellview cell name and view name
(av_extracted) are correct. You can then select “Show Parasitics” under the same menu. Only the
capacitive parasitics will be useful to you. Therefore, you can hide the other resistance/inductance
information by deselecting these options in “Options” under “Parasitics” menu item. You can also
generate a report through “Report Parasitics” selection.
P4:
Extract the 2-Input AND parasitics (intrinsic capacitance), and redo the previous timing
simulation again. Identify any differences from the data table provided in (P3) by first generating
a new marker data table for the same transition types. Make sure to submit your new table, clearly
annotating the results.
5. POWER DISSIPATION ANALYSIS
You will take advantage of the transient simulations in the previous Chapter in order to estimate the
dynamic power dissipation. As the waveform to be plotted, the current of the VDD pin should be chosen.
For this, click on Outputs > To be plotted > Select on Schematics on Analog environment menu, and
click on the upper node of the "vdc". This node will be circled. Choose also the input and output voltage
nets to be plotted. After you run the simulation, investigate the menu selections associated with the
waveforms, in order to split the current waveform to a different plot (strip), as depicted by light blue
waveform in Figure 5-1.
As observed, dynamic power is only dissipated at the points when the state of the inverter changes. In
order to calculate the average of this current waveform, do the following:
➢ Invoke the calculator from Tools > Calculator from the wavefom window.
➢ Select “special functions” in the lower menu (where it by default usually picks math). Pick
average.
➢ When you evaluate the buffer, current value should be displayed in the calculator buffer as
averaged over the full simulation time. It is possible to zoom into the particular part of the
waveform, and use “clip” function of the calculator to average the waveform only over the
zoomed timing window. To do this, you need to first clip a certain time range of the waveform,
and then average its value.
You can use the “Math” functions in the calculator to generate a power waveform by multiplying the
current waveform with the constant VDD (1.8 V in this case). This is represented as the green waveform
in the lower strip in Figure 5.1. You may also plot the energy consumption over time by using the
indefinite integral function (iinteg) under “Special functions” to integrate the power curve, as shown by
the red curve in the lower strip of Figure 5-1. Note the scale of the red energy curve shows on the right
hand side of the plot – energy dissipation is initially 0, and increases in magnitude over time as expected.
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Figure 5-1 Current, power and energy simulations (below) across the switching activity of interest
(above).
P5:
i. Submit the power and energy simulation plots in your report for your defined input waveforms.
ii. Which input transition(s) result(s) in the largest peak in power dissipation? Explain why.
iii. Which input transition(s) result(s) in the largest energy dissipation? Again explain.
6. An Alternative Way for Digital Circuits Simulation
To simulate digital circuits we can use “vbit” as a source. It can be found under analogLib and
generates digital output according to the data pattern. In Figure 6-1, it is used for transient analysis
of the two input AND gate.
Figure 6-1 Schematic of the Circuit
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The properties of the “vbit” is given in Figure 6-2.
Pattern Parameter data: series output data
Period: Time for 1-bit data
Figure 6-2 Properties of "Vbit"
In Figure 6-3, transient simulation results are given where data patterns are chosen arbitrarily.
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Figure 6-3 Waveforms
Note: Notice that all the figures in the assignment are belong
to Cadance and ADE softwares. They are added just for
cross-check. The order of tasks will be same but electric vlsi
design system and ltspice softwares’ interfaces will be
different
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