DIGITAL.
INTEGRATED
CIRCUITS
THOMAS A. DEMASSA
ARIZONA STATE UNIVERSITY
ZACK CICCONE
VLSI TECHNOLOGY INC.
JOHN WILEY & SONS
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Copyright © 1996, by John Wiley & Sons, Inc.
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Libran; of Congress Cataloging in P11blication Data
DeMassa, Thomas A
Digital integrated circuits/ Thomas A. DcMassa, Zack Ciccone.
p.
cm.
Includes index.
ISBN 0-471-10805-7 (cloth: alk. paper)
1. Digital integrated circuits. I. Ciccone, Zack. II. Title.
TK7874.65.D38
1996
95-312
621.3815-dc20
CIP
10 9 S 7 6 5
To my patient and loving wife, Joann;
To Kari, Tom and Dcbb,
Andrea, as well as Mary and Karen
-with particular thanks to my mom and dad for their lifelong support
Tha111as A OcMassn
To the memory of Louise Ciccone and David E. Duick
Zack Jahn Ciccone
BACKGROUND
GOALS
Digital Integrated Circuits is intended as a textbook
suitable for electrical engineering students as well as
electronic technology students. This text has been
used in note form for a senior/first-year graduatelevel electrical engineering course and an upper-level
electronic technology course with excellent results. It
can also serve as a self-teaching tool for practicing
circuit designers in the IC development profession or
as a reference for engineers in industry that need
familiarization with the operation and design of various digital integrated circuits.
The text, written in a clear and concise manner,
provides maximum coverage of the material and
requires a minimum of instructor support. This
is achieved by providing complete, qualitative
descriptions of circuit operation followed by indepth analysis and SPICE simulations whenever appropriate. There are numerous example problems
throughout the text, and solutions have been provided. These problems enhance the text material and
provide an additional learning tool for the reader.
Both static and transient operation are considered in
detail.
The text provides the most extensive coverage
of digital integrated circuit principles available in a
single resource. The circuit families described in
detail are: transistor-transistor logic (TTL, STTL,
and ASTTL), emitter-coupled logic (ECL), NMOS
logic, CMOS logic, dynamic CMOS, BiCMOS
structures, and various GASFET technologies. In
addition to presentations of the basic inverter
circuits for each digital logic family, complete details
of other logic circuits for these families are presented. The logic circuits include NAND, AND,
NOR, OR, XOR, XNOR, complex logic functions
such as AOI and OAI, as well as latches, flip-flops,
memory elements, and Schmitt trigger gates. A manual is provided with the book which contains the
solutions to the end-of-chapter problems, and
a detailed outline for a general course study of 15
weeks.
We had definite goals in mind as we were preparing
this manuscript for publication. Some of those goals
were:
V
1.
To offer extensive knowledge and a broad background base for the operation and design of
digital integrated circuits by furnishing easy-toread descriptions and including numerous
examples
2.
To describe the details of the internal operation
and use of digital integrated circuits
3.
To emphasize CMOS digital logic, since this
circuit family has become the most extensively
used
4.
To provide extensive and detailed descriptions of
the operation and design of gallium arsenide
digital-logic families
5.
To present a thorough description of the operation of various logic gates from each family, not
just the inverters. Entire chapters are dedicated
to the following:
a. TTL design of AND, NOR, OR, complex
AOI and OAI, Schmitt trigger, and tri-state
gates
b. ECL design of AND and NAND (not just OR
and NOR) gates using collector dotting and
series gating methods
c. CMOS and NMOS design of NAND, NOR,
complex AOI and OAI, XOR, XNOR, tristate, Schmitt trigger, as well as dynamic
CMOS gates
6.
To explain the DC behavior, as well as the transient behavior of digital integrated circuits
7.
To compare SPICE modeling for each of the
digital logic families with theoretical circuit
analysis
8.
To demonstrate the operation and design
of latches, memory circuits, and BiCMOS
gates
VI
Preface
IMPROVEMENTS ON THE
COMPETITION
In writing this text, extremely important topics have
been addressed without skipping steps. There are
over 200 clearly written examples that have been
worked out. Furthermore, learning is promoted by
the fact that the order of each family has been done
in a similar fashion. Additionally, a new technique of
Kirchoff's Voltage law (KVLt shown along a dashed
path in a complex circuit figure, allows the reader to
rnaximize ltis understanding of this new approach. A
great deal of the material contained in the STTL,
ECL, NMOS, CMOS, and gallium arsenide digital
integrated circuit chapters is not available in any
other textbook.
Chapter 1 introduces the basic properties and
definitions of digital integrated circuits and the five
basic combinational logic operations for digital
electronic circuits (NOT, AND, OK NAND, and
NOR).
Chapter 2 describes the behavior of semiconductor PN junction diodes and metal-semiconductor
MN Schottky diodes. These two-terminal devices are
used in digital logic circuits to perform logic operations, provide DC voltage level shifting, as well as to
operate as variable capacitors and clamping diodes
at logic circuit inputs and outputs. The diode SPICE
model also is completely detailed.
Chapter 3 indicates basic methods used to fabricate bipolar junction transistors (BJTs) in digital
logic families. Also, the BJT modes of operation and
the BJT models, Ebers-Moll, Gummel-Poon, and
SPICE are described.
Chapters 4-15 deal with bipolar digital integrated circuits. The resistor-transistor logic (RTL)
family is described in Chapters 4 and 5. This family
was the first logic family to be commercially available. RTL has very poor power-speed performance,
due primarily to the use of resistors. To improve RTL
circuits, diode-transistor logic (DTL) was introduced
based on the design of preexisting circuits. Basic and
modified DTL circuits are described in Chapter 6. As
the name implies, circuits of the DTL logic family use
diodes and transistors in their design. However, because this family uses a resistor as the passive pullup element DTL circuits provide poor pull-up
speeds. In 1965, the transistor-transistor logic (TTL)
family was introduced. This name implies that the
usage of diodes in DTL was replaced with transistors
in TfL. Basic TTL circuits are described in Chapter
7. The resulting TTL circuits provided increased fanout, improved transient response, and a reduction in
chip area. The main improvement in TTL design over
DTL was the inclusion of an active pull-up subcircuit.
This resulted in faster charging of the equivalent output capacitance which improves the output rise time.
Standard TTL circuits, however, continue to have the
disadvantage of long propagation delay time because
these circuits provide operation in the saturation
mode. This can be avoided when Schottky transistors
are used in place of ordinary bipolar transistors. In
1970, Schottky transistor-transistor logic (STTL) was
introduced. The major advantage of using STTL circuits was a much-improved delay time because the
Schottky-clamped BJTs can not operate in the saturation mode. Hence, the switching speed was improved and the time delays shortened. In 1985, advanced Schottky TTL (ASTTL) was introduced. These
circuits were made possible in part by improving BJT
fabrication techniques. Ion implantation, 3 µ minimum size, and oxide isolation were major improvements that reduced the ASTTL propagation delays,
while maintaining the typical power dissipation.
Schottky TTL circuits are described in Chapters 8-10.
Another important bipolar digital logic family is
emitter-coupled logic (ECL). ECL circuits are described in Chapters 11-15. The BJTs in ECL circuits
operate only in the forward-active and cutoff regions.
Therefore, the major improvements of ECL circuits
are the faster switching time and larger fan-out.
Moreover, ECL has a smaller logic swing than TTL.
This small logic swing combined with the use of
emitter-coupled pairs eliminate current spikes and
result in a lower susceptibility to noise. However, the
improved performance is achieved at the expense of
much higher power dissipation among all of the logic
families.
In Chapter 16, silicon MOS transistors are introduced. This chapter contains the semiconductor
field-effect transistors (MOSFETs) including geometry, modes of operations, parameters, and the
SPICE MOSFET model.
In Chapters 18-22, NMOS digital circuits are described. The NMOS digital logic families detailed are:
The resistor loaded NMOS, the saturated enhancement-only loaded NMOS, the linear enhancementonly-loaded NMOS, and the enhancement-deple-
Preface
tion loaded NMOS. The basic NMOS circuits can be
augmented to perform all of the combinational logic
functions. These circuits are presented in Chapter 22.
Chapter 23 introduces the important features of
complementary MOS (CMOS) inverters, including
modes of operation, power dissipation, fan-out, and
latch-up. Currently, CMOS is the most widely used
digital circuit technology and this family is emphasized throughout this text. CMOS logic families have
the lowest power dissipation and the highest packing
density of all logic families.
In Chapters 24-27, the various combinational
CMOS digital logic circuits are presented. CMOS tristate gates are discussed as well as a presentation of
output contention. CMOS Schmitt trigger circuits
exhibiting output hysteresis are implemented using
source-follower feedback MOSFETs. The hysteresis
is the result of the output feedback to intermediate
points of stacked NMOS and PMOS transistors.
Gates with such an output hysteresis have a high
noise immunity and are useful for noisy inputs, non
rail-to-rail inputs, and slow inputs.
Chapter 28 deals with additional forms of CMOS
logic referred to as dynamic CMOS logic; pseudo
NMOS logic, dynamic CMOS logic, and CMOS
domino logic.
Chapter 29 compares digital logic families. These
include the various silicon integrated circuits families
(both bipolar and MOS) as well as the high speed
gallium arsenide logic families.
Chapter 30 describes circuits referred to as
BiCMOS. This is an advanced technology digital in-
VU
tegrated circuit family that consists of both bipolar as
well as CMOS transistor structures on the same chip.
Such BiCMOS circuits provide the advantages of bipolar and CMOS technologies.
Chapter 31 contains a detailed description of
both latches and flip-flops. These are the memory
elements in the digital integrated circuit area. Edgetriggered and tri-statc gates are also described.
In Chapters 32 and 33, semiconductor memory
circuits are provided. Chapter 32 includes the readonly memories (ROMs) and Chapter 33 describes
static random access memories (RAMs). Diode, transistor, NMOS, and CMOS memories are described
in detail.
Chapter 34 provides details of the metal-semiconductor FET called the MESFET. A model is developed for these devices that leads to the SPICE
NMESFET model.
Chapters 35-37 detail the important gallium arsenide digital logic circuits. The important families
described are: (1) the direct-coupled NMESFET logic
(DCFL) family, (2) the Schottky diode NMESFET
logic (SDFL) family, and (3) the buffered NMESFET
logic (BFL) family.
Finally, Chapters 38 and 39 provide descriptions
of various other gallium arsenide digital logic families. Chapter 39 also includes various gates such as
DCFL OR gates, BFL NOR gates, and a DCFL XOR
gate. Additionally, transmission gates and RAM
memory elements are discussed in Chapter 39.
Thomas A. DeMassa
Zack Ciccone
ACKNOWLEDGMENTS
The authors would like to thank the many colleagues
and students who suggested corrections and changes
to the original manuscript. In addition, thanks are
extended to
Manda J. Turley
Linda Rawles
Marney Thompson
Sherrie Benton
Jennifer Yee
Jeff Miles
Beth J. Quang
Steve J. Macia
Victor Tiginini
Ron Roedel
Ginny Reggiani
Deborah Thornber
Douglas Cochran
Chris Springfield
Chris J. Ciccone
Tom J. Ciccone
Richard J. Huebner
Wendell Wells
Debra DeMassa
Edward Gyeki
Suzanne Azzarella
Shankar Chandrashekaran
Hiram Upadhyay
Joseph Perez
Bhaskar Aravind
Mathew Joseph
Sharada Yeluri
Peter J. Young
Mindy J. McCormick
Brian G. Kirkland
Shannon Bushard
Rakesh Cheerla
Denise J. Marques
Tim Beatty
Carl Liepold
Melanie J. Nemetz
Dawn J. Johnson
Dena J. Douglas
John Crum
Marc Buer
Edie J. Eiker
Val J. Lipton
Jim J. Corbett
Chuck J. Day
Allen Sulliven
The authors would also like to thank the following
reviewers for their comments and suggestions:
Arthur D. van Rheenen
University of Minnesota
Richard B. Brown
University of Michigan
Krzyszof Iniewski
University of Toronto
Edward Maby
Rensselaer Polytechnicd Institute
Walter Varhue
University of Vermont
Darrell L. Vines
Texas Tech University
Special thanks are extended to Steven J. Nemetz.
ix
CONTENT
1
PROPERTIES AND DEFINITIONS
OF DIGITAL ICS
1
1.1
1.2
1.3
1.4
1.5
1.6
1. 7
1.8
1.9
Inverting and Non-Inverting Gates 1
Ideal Logic Elements 2
Inverter Voltage Transfer Characteristic
Logic Swing and Transition Width 6
Noise in Digital Circuits 6
Fan-In and Fan-Out 7
Transient Characteristics 8
Power Dissipation 10
Power-Delay Product 11
2
DIODES
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
PN Junction and MN Schottky Diodes 15
Diode Modelling 15
Diode Capacitance 18
SPICE Diode Model 18
Diode- Resistor Logic 19
Level-Shifted Diode-Resistor Logic 21
Clamping Diodes 23
Level-Shifting Diodes 24
3
BIPOLAR JUNCTION
TRANSISTORS
5
15
27
Junction Isolated NPN BJT 27
Oxide Isolated NPN BJT 27
3.3
Multi-Emitter BJT 27
3.4
Schottky-Clamped BJT 28
3.5
Lateral PNP BJTs 31
3.6 The Ebers-Moll BJT Model 31
3.7 BJT Modes of Operation 32
3.8 The Gummel-Poon BJT Model 35
3.9
SPICE BJT Model 37
3.10 Integrated Circuit Resistors 39
3.2
4.1
4.2
4.3
4.4
INTRODUCTION TO BIPOLAR
DIGITAL CIRCUITS
Analysis of BJT Circuits with Known
States 42
BJT Inverter 45
TTL Super-Circuitry 46
Level-Shifting BJTs 48
4.6
4.7
4
3.1
4
4.5
RESISTOR-TRANSISTOR
LOGIC (RTL)
56
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
5.9
5.10
Basic RTL Inverter 56
Basic RTL NOR Gate 56
Basic RTL NAND Gate 57
RTL Fan-Out 59
RTL Power Dissipation 62
Basic RTL Non-Inverter 62
Basic RTL OR and AND Gates 64
RTL with Active Pull-Up 64
RTL SPICE Simulation 67
Direct Coupled Transistor Logic and Current
Hogging 68
6
DIODE-TRANSISTOR
LOGIC (DTL)
6.1
6.2
6.3
6.4
6.5
6.6
6.7
Basic DTL Inverter 72
Modified DTL 73
Transistor Modified DTL 74
DTL NAND Gate 75
DTL Fan-Out 75
DTL Power Dissipation 78
DTL SPICE Simulation 80
7
TRANSISTOR-TRANSISTOR
LOGIC (TTL)
7.1
7.2
7.3
42
Discharge Paths and Base Driving
Circuitry 48
Self-Biasing BJTs 49
Power Dissipation of Bipolar Logic
Circuits 50
7.4
7.5
7.6
7.7
72
83
Basic TTL Inverter 83
Comparison of Stored-Charge Removal from
DTL and TTL 84
Basic TTL NAND Gate and the MultipleEmitter BJT 85
Standard TTL NAND Gate with Totem Pole
Output 85
Standard TTL Voltage Transfer
Characteristic 87
TTL Fan-Out 89
TTL Power Dissipation 91
xii
Table of Contents
7.8
Open -Collector TI"'L 91
7. 9 Low Power TTL (L TTL) 92
7.10 High Speed TTL (HTTL) 92
7.11 TfL SPICE Simulation 93
8
SCHOTTKY TRANSISTORTRANSISTOR LOGIC (STTL)
8.1
8.2
8.3
8.4
8.5
8.6
8.7
Schottky-Barrier Diodes 98
Schottky-Clamped BJTs 98
Schottky-Clamped TTL (STTL) 101
STIL Fan-Out 104
STTL Power Dissipation 104
Low-Power STTL (LSTTL) 107
STTL SPICE Simulation 110
9
ADVANCED SCHOTTKY
TRANSISTOR-TRANSISTOR
LOGIC (ASTTL)
9.1
9.2
9.3
98
12
TEMPERATURE
COMPENSATING EMITTERCOUPLED LOGIC
12.1
12.5
12.6
12.7
MECL II with Temperature Compensating
Bias Network 171
DC Analysis of the Bias Network 173
The Need For Temperature
Compensation 174
Bias Network Compensation for
Temperature Variation 176
Fan-Out of MECL II 177
Power Dissipation of MECL II 177
MECL II SPICE Simulation 179
13
MECL III and ECL 10K
12.2
12.3
12.4
115
Advanced LSTTL (ALSTTL) 115
Fairchild Advanced Schottky TTL
(FAST) 118
Advanced Schottky Transistor-Transistor
Logic (ASTTL) 121
13.1 MECL III 182
13.2 MECL III Voltage Transfer
Characteristic 183
13.3 MECL III Fan-Out 185
13.4 MECL III Power Dissipation 187
13.5 ECL 10K Series 189
13.6 ECL 10K Series SPICE Simulation
14
10
OTHER TTL GATES
124
10.1
10.2
10.3
10.4
10.5
10.6
TTL AND Gates 124
TTL NOR Gates 129
TTL OR Gates 131
TTL AND-OR-Invert (AOI) Gates 133
TTL XOR Gates 137
TTL Schmitt Trigger Inverters and NAND
Gates 140
10.7 TTL Tri-State Buffers 144
11
BASIC EMITTER-COUPLED
LOGIC (ECL)
11.1 BJT Current Switch 155
11.2 ECL Current Switch Voltage Transfer
Characteristic 156
11.3 ECL Super-Circuitry 158
11.4 Basic ECL NOR/OR Gate 159
11.5 MECL I NOR/OR Gate with Output
Buffers 161
11.6 MECL I Voltage Transfer Characteristic
11.7 MECL I Fan-Out 163
11.8 MECL I Power Dissipation 165
11.9 MECL I SPICE Simulation 167
1n
182
189
MODERN EMITTER-COUPLED
LOGIC
194
14.1 100K ECL Subfamily 194
14.2 DC Analysis of the 100K ECL Bias
Network 196
14.3 Bias Network Compensation for
Temperature Variation 198
14.4 Power Dissipation of 100K ECL
Subfamily 199
14.5 Other ECL Families 199
155
15
OTHER ECL GATES
15.1
Use of NOR/OR Gates as AND/NAND
Gates with Inverted Inputs 201
Collector Dotting Wired-AND Gates 202
Collector Dotting Complex OR-AND Logic
Gates 206
Series Gating-Basic ECL NANO/AND
Current Switch 208
Series Gating NANO/AND Gate 211
Series Gating Complex OR-AND
Gates 215
ECL XOR/XNOR Gates 216
ECL Decoding Tree 219
15.2
15.3
15.4
162
15.5
15.6
15.7
15.8
201
Table of Contents
16
METAL OXIDE
SEMICONDUCTOR FIELD
EFFECT TRANSISTORS
19.2
221
16.1
16.2
16.3
16.4
16.5
16.6
16. 7
16.8
16.9
16.10
Metal Gate N-Channel MOSFETs 221
Silicon Gate N-Channel MOSFETs 221
MOSFET Modes of Operation 221
MOSFET Transconductance Parameter 225
MOSFET Threshold Voltage 226
P-Channel MOSFET 227
MOSFET Capacitances 227
SPICE MOSFET Model 228
CMOS Devices 230
Integrated Circuit Capacitors 232
17
INTRODUCTION TO MOS
DIGITAL CIRCUITS
RESISTOR LOADED NMOS
INVERTER
Graphical Determination of Saturated
Enhancement-Only Loaded NMOS Inverter
VTC 263
19.3 Calculation of VTC Critical Points for
Saturated Enhancement-Only Loaded
NMOS Inverter 264
19.4 Body Bias Considerations for Saturated
Enhancement-Only Loaded NMOS
Inverter 266
19.5 Power Dissipation of Saturated
Enhancement-Only Loaded NMOS 270
19.6 Saturated Enhancement-Only Loaded
NMOS SPICE Simulation 271
20
234
17.1 General NMOS Inverter 234
17.2 The Zero Drain Current Active
MOSFET 234
17.3 Graphical Solution of the NMOS
Inverter 237
17.4 Partial Differentials 239
17.5 Analytical Solution of the NMOS
Inverter 240
17.6 Power Dissipation 240
17.7 MOSFan-Out 240
18
xiii
LINEAR ENHANCEMENT-ONLY
LOADED NMOS INVERTER
274
20.1
244
18.1
Operation of Resistor Loaded NMOS
Inverter 244
18.2 Graphical Determination of VTC for Resistor
Loaded NMOS Inverter 245
18.3 Calculation of VTC Critical Points for
Resistor Loaded NMOS Inverter 247
18.4 Power Dissipation of Resistor Loaded NMOS
Inverter 250
18.5 Resistor Loaded NMOS Inverter Dynamic
Response 252
18.6 Resistor Loaded NMOS SPICE
Simulation 258
19
SATURATED ENHANCEMENTONLY LOADED NMOS
261
INVERTER
19.1
Operation of Saturated Enhancement-Only
Loaded NMOS Inverter 261
Operation of Linear Enhancemnet-Only
Loaded NMOS Inverter 274
20.2 Graphical Determination of Linear
Enhancement-Only Loaded NMOS Inverter
VTC 276
20.3 Calculation of VTC Critical Points for Linear
Enhancement-Only Loaded NMOS
Inverter 277
20.4 Body Bias Consideration for Linear
Enhancement-Only Loaded NMOS
Inverter 281
20.5 Power Dissipation of Linear EnhancementOnly Loaded NMOS 284
20.6 Linear Enhancement-Only Loaded NMOS
SPICE Simulation 285
21
21.1
ENHANCEMENT-DEPLETION
LOADED NMOS INVERTER
288
Operation of Enhancement-Depletion
Loaded NMOS Inverter 288
21.2 Graphical Determination of EnhancementDepletion NMOS Inverter VTC 289
21.3 Calculation of VTC Critical Points for
Depletion Loaded NMOS Inverter 290
21.4 Body Bias Considerations for EnhancementDepletion Loaded NMOS Inverter 294
21.5 Enhancement-Depletion Loaded NMOS
Power Dissipation 297
21.6 Enhancement-Depletion Loaded NMOS
SPICE Simulation 298
XIV
Table of Contents
22
NMOS GATES
22.1
22.2
22.3
22.4
22.5
22.6
22.7
NMOS
NMOS
NMOS
NMOS
OAls)
NMOS
NMOS
NMOS
23
CMOS INVERTER
23.1
Operation of Complementary MOS (CMOS)
Inverter 336
Power Dissipation of CMOS 338
Graphical Determination of CMOS Inverter
VTC 339
Calculation of VTC Critical Points for CMOS
Inverter 340
The Symmetric CMOS Inverter 343
The Minimum Size CMOS Inverter 345
CMOS Inverter Capacitances 346
CMOS Inverter Dynamic Response 349
CMOS Fan-Out 358
CMOS Inverter SPICE Simulation 361
Design of CMOS Inverters 364
CMOS Latch-Up 367
Electro-Static Discharge and Input Clamping
Sections 369
23.2
23.3
23.4
23.5
23.6
23.7
23.8
23.9
23.10
23.11
23.12
23.13
24
24.1
CMOS COMBINATIONAL
LOGIC GATES
24.6
CMOS Inverter Pull-Up and Pull-Down
Review 373
CMOS NANO Cate 374
CMOS NOR Gate 379
CMOS AND and OR Gates 384
CMOS Complex Logic Gates (AOis and
OAis) 384
CMOS XOR/XNOR Gates 399
25
CMOS TRI-STATE GATES
24.2
24.3
24.4
24.5
25.1
301
NOR Gate 303
NANO Gate 305
OR and AND Gates 308
Complex Logic Gates (AOis and
308
XNOR/XOR Logic Gates 313
Schmitt Triggers 316
Transmission Gates 323
25.6
25.7
25.8
25.9
25.10
336
373
26
CMOS SCHMITT TRIGGER
GATES
26.1
26.2
26.3
26.7
Hysteresis 437
CMOS Schmitt Inverter 439
Operation and Voltage Transfer
Characteristic of the CMOS Schmitt
Inverter 441
Design of CMOS Schmitt Inverter 444
CMOS Schmitt Inverter with Buffered
Output 446
CMOS Schmitt Inverter with Buffered
Output and Feedback 447
CMOS Schmitt NANO Gates 451
27
CMOS DRIVERS
27.1
Cascaded CMOS Inverters Driving a Load
Capacitance 454
CMOS Multi-Stage Inverter Drivers 457
CMOS Tri-State Pin Drivers (Pad
Drivers) 461
Pad Driver with Break-Before-Make
Embodiment 463
26.4
26.5
26.6
27.2
27.3
27.4
411
CMOS Logic Gates with High Impedance
Z-States 411
25.2 CMOS Logic Gates with Contention
X-States 414
25.3 CMOS Tri-State (Clocked) Inverters 417
25.4 Application of Tri-State Inverters 419
25.5 Integrated Circuit BUSes Utilizing Tri-State
Inverters 422
Ordering of Stack Transistors in Tri-State
Inverters 422
Tri-State Logic of Multi-Input Logic
Functions 422
CMOS Bi-Directional Transmission Gate
(Switch) 426
Application of CMOS Bi-Directional
Transmission Gates 431
Disadvantages of CMOS Bi-Directional
Transmission Gates (Non-Fnult
Gmdnbility) 432
28
DYNAMIC CMOS
28.1
28.2
Pseudo-NMOS Logic 467
CMOS Precharging and Discharging of a
Load Capacitance 467
Dynamic CMOS Logic 469
CMOS Domino Logic 4 71
283.
28.4
29
29.1
COMPARISON AND
INTERFACING OF
LOGIC FAMILIES
Comparison of Silicon IC Logic
Families 477
437
453
467
477
Table of Contents
33
29.3
Comparison with Gallium Arsenide Digital
Logic Families 478
Interfacing Logic Families 478
30
BiCMOS
33.1
29.2
486
30.1 Reason for BiCMOS 486
30.2 BiCMOS Devices 486
30.3 BiCMOS Inverters with Resistive
Shunts 488
30.4 BiCMOS Inverters with Active Shunts 488
30.5 BiCMOS Inverters with Parallel Output
CMOS Inverter 488
30.6 BiCMOS NAND Gates with Resistive
Shunts 490
30.7 BiCMOS NAND Gates with Active
Shunts 491
30.8 BiCMOS Drivers 492
30.9 Full Swing Methods 494
31
LATCHES AND FLIP-FLOPS
31.1
Basic Definitions for Sequential Logic
Gates 498
Cross Coupled Inverters 501
Reset-Set (RS) Latch 504
Gated RS Latches 511
Gated RS Latches with Asynchronous Clear
and Preset 513
Edge-Triggered Master-Slave RS FlipFlops 515
JK Latch 526
Edge-Triggered Master-Slave JK Flip-Flops
0KFF) 528
Basic Data (D) Latch 534
Gated Data (D) Latch 536
Tri-State Embodied Gated Data (D)
Latches 540
Edge-Triggered Master-Slave D
Flip-Flops 543
31.2
31.3
31.4
31.5
31.6
31.7
31.8
31.9
31.10
31.11
31.12
32
32.1
32.2
32.3
32.4
32.5
32.6
32.7
498
SEMICONDUCTOR READ-ONLY
MEMORIES
556
Diode Read-Only Memories 557
BJT Read-Only Memories 563
Bipolar ROM Line Amplifier 572
NMOS NOR Read-Only Memories 572
NMOS NAND Read-Only Memories 580
CMOS Precharging and Discharging of a
Load Capacitance 583
CMOS Read-Only Memories 585
33.2
33.3
34
34.1
34.2
34.3
34.4
34.5
34.6
34.7
34.8
34.9
35
SEMICONDUCTOR STATIC
RANDOM-ACCESS
MEMORIES
Static RAM Cell with Transmission
Gates 603
MOSFET Static RAM Cell Technologies
BJT Static RAM Cell Technologies 608
GALLIUM ARSENIDE METAL
SEMICONDUCTOR FIELD
EFFECT TRANSISTORS
XV
603
607
613
N-Channel MESFETs (NMESFETs) 613
Enhancement-Depletion NMESFETs 615
Enhancement-Only NMESFETs 616
NMESFET Modes of Operation 616
NMESFET Transconductance
Parameter 618
NMESFET Threshold Voltage 618
NMESFET Capacitance 619
NMESFET Choice 619
SPICE NMESFET Model 620
DIRECT COUPLED NMESFET
LOGIC (DCFL) INVERTER
622
35.1
Direct-Coupled Enhancement-Only
NMESFET Inverters 622
35.2 Operation of Direct Coupled NMESFET
Inverter 622
35.3 Graphical Determination of Direct Coupled
Inverter VTC 624
35.4 Calculation of VTC Critical Points for DCFL
Inverter 624
35.5 Optimum f3 0 /f3L (W0 /W 1J Ratio for DCFL
Inverter 627
35.6 Power Dissipation of DCFL Inverter 628
35.7 DCFL Fan-Out 628
35.8 DCFL Inverter SPICE Simulation 629
36
36.1
SCHOTTKY DIODE NMESFET
LOGIC (SDFL) INVERTER
633
Schottky Diode Enhancement-Depletion
Inverters 633
36.2 Operation of SDFL Inverter 633
36.3 Calculation of VTC Critical Voltages for the
SDFL Inverter 635
36.4 Optimum f3t)f3L = Wn/WL Ratio for SDFL
Inverter 636
XVI
Table of Contents
36.5 Power Dissipation of SDFL Inverter 637
36.6 SDFL Fan-Out 638
36.7 SDFL Inverter SPICE Simulation 639
37
37.1
37.2
37.3
37.4
37.5
37.6
38
BUFFERED NMESFET LOGIC
(BFL) INVERTER
39.4
39.5
39.6
39.7
39.8
642
Buffered Enhancement-Depletion NMESFET
Inverters 642
Operation of BFL Inverter 642
Calculation of vrc Critical Voltages for the
BFL Inverter 643
Power Dissipation of BFL Inverter 645
BFL Fan-Out 646
BFL Inverter SPICE Simulation 646
OTHER GALLIUM ARSENIDE
LOGIC FAMILY INVERTERS
649
38.1
Capacitor Coupled NMESFET Logic (CCFL)
Inverter 649
38.2 Capacitor-Diode NMESFET Logic (CDFL)
Inverter 649
38.3 Source Coupled NMESFET Logic (SCFL)
Inverter 650
38.4 Low Pinch-Off Voltage NMESFET Logic
(LPFL) Inverter 651
38.5 Gallium Arsenide Transmission Gates 652
38.6 Power Dissipation 653
39
GALLIUM ARSENIDE
NMESFET GATES
39.1 DCFL NOR Gate 655
39.2 DCFL NANO Gate 656
39.3 DCFL OR Gate 657
655
39.9
39.10
39.11
39.12
SDFL NOR Gate 657
SDFL NANO Gate 658
BFL NOR Gate 659
BFL NANO Gate 659
Gallium Arsenide NMESFET Complex ANDOR-Invert (AOI) and OR-AND-Invert (OAI)
Gates 659
DCFL XOR Gate 660
Other OR/NOR Gates 661
Gallium Arsenide Transmission Gate
Logic 662
Gallium Arsenide Static RAM Memory
Elements 663
APPENDIX A
A.1
A.2
A.3
A.4
Development of the Stored Charge
Equation 666
Shockley's Expression 667
Diode Turn-On Transient 668
Diode Turn-Off Transient 669
APPENDIX B
B.1
B.2
B.3
DIODE SWITCHING
TIMES
666
BJT SWITCHING
TIMES
670
Development of the Stored Charge
Equation 670
BJT Turn-On Transient 670
BJT Turn-Off Transient 671
SUPPLEMENTARY READING
672
SELECTED ANSWERS
674
INDEX
679
PROPE TIES A D
DEFINITIONS OF
DIGITAL ICS
This chapter introduces the general properties and
definitions of digital circuits. These properties and
definitions are common to all digital integrated circuit families and are used throughout this text.
Digital electronic circuits are represented by five
basic logic operations. These are as follows:
•
We begin by describing the basic building blocks
of digital integrated circuits, the inverter and the
non -inverter.
1.1 INVERTING AND
NON-INVERTING GATES
NOT
• AND
• OR
Inverter
• NAND
Figure 1.1 displays circuit symbols that are used to
represent gates that perform logic inversion. That is,
if the input voltage is low, the output voltage will be
high and vice versa. This device is usually referred to
as an inverter or NOT gate, since it performs the logical NOT operation.
The small circle in Figure l.la and b is referred
to as an inverting bubble or inverting circle. The small
circle denotes logical inversion and is used extensively in digital logic circuits. It makes no difference whether the inverting circle is at the input or
output.
• NOR
When one of these operations is carried out by an
electronic circuit, the citcuit that performs this logic
function is referred to as a gate. The logic gates that
perform one or more of the basic operations are referred to as combinational gates. In these cases, the
outputs depend only upon the present value of the
inputs. We will describe many electronic circuits that
are used to carry out combinational logic operations
throughout the text. Circuits that perform sequential
logic operations are also presented in later chapters.
Sequential gates have output(s) that depend upon
past values of input(s), as well as present values. Implementation of these digital logic functions is also
accomplished feasibly using quite a few different digital electronic circuits.
The voltages (or currents) in digital logic circuits
have two possible states indicating that the variables
are binary. Considering voltage as a variable, the two
possible states correspond to a low voltage or a high
voltage, where we usually define the low voltage to
correspond to a binary O and the high voltage to a
binary 1. This is referred to as positive voltage logic
and is used for all IC logic families throughout this
text.
Non-Inverter (Buffer)
Another basic digital circuit device is the non-inverting gate which is sometimes referred to as a buffer.
Alternate circuit symbols for these devices are shown
in Figure 1.2. Buffers are used to regenerate voltage
levels, making degraded high levels higher and degraded low levels lower.
The inverting and non-inverting elements are
the fundamental building blocks for all digital logic
families. The basic inverter and its operation are
described for each logic family in succeeding chapters.
1
2
Chapter 1/Properties and Definitions of Digital !CS
1.2
IDEAL LOGIC ELEMENTS
Ideal Static and Power Characteristic
(a)
(b)
Figure 1.3a shows an ideal logic inverter. It operates
with a single power supply (Vcc in this case). A typical operating voltage of many logic families is 5 V.
The current Ice drawn from Vcc is ideally zero, giving
a power dissipation P cc of zero. In actual digital circuits the power dissipated is minimized for optimum
design. Figure 1.3b shows how voltage levels are ideally used to represent the input and output logical 0
and logical 1 states in digital circuits. The logical 1
output voltage is ideally at the power supply voltage
Vcc· The logical O output voltage is ideally at ground
(O V). Logic gates with output voltage transitions
from ground to the power supply voltage are said to
operate "rail-to-rail".
The transition between output logic states ideally occurs abruptly at an input of Vcc/2. Thus, logical input O is represented by the voltage range O :s;
V1;--.: < Vcc/2, since an input in this range will gen-
Alternate Inverter Logic Symbols
FIGURE 1.1
~ ~
(a)
FIGURE 1.Z
(b)
Alternate Non-inverting Logic Symbols
(a)
YaurCV)
logical 1
output
Yee I"""_
_ _.....,
YIN(V)
t,_
V
cc
logical O
input
i
logical 1
input
►
t
►
t
Yaur(V)
◄---
+
Yee,-!---,
logical 0
output
L___ _ __ . . _. . . . ._ _~ - - -
Ya/2
YIN(V)
Yee
(c)
(b)
FIGURE 1.3 Ideal Logic Inverter: (a) Operates from a single power supply, (b) Voltage transfer characteristic,
(c) Transient response
1.2 Ideal Logic Elements
Ideal Transient Characteristic
erate a logical 1 output state. Similarly, logical input
1 is represented by the voltage range Vcc/2 < V1;-..: :::::
Vee• The input voltage V1;-..: = Vcc/2 has an undefined
output and will cause unpredictable results, and is
therefore avoided. As will be seen in Chapter 23, the
CMOS logic family comes closest to meeting these
ideal static characteristics.
Figure 1.3c illustrates the transient response of the
ideal logic inverter. Upon transition of the input from
logical O to logical 1, the output instantaneously, and
without delay, switches from logical 1 to logical 0.
(As will be seen in section 1.7 the switching speed is
Your
-►
Iour
V' IN
1~ ►
. I'
i
IN
- - - - -- - load gates
I
driving gate
(b)
FIGURE 1.4
3
(a) Modelling of inverter input and output impedance, (b) Static driving of multiple (identical) inverters
4
Chapter 1/Propertics and Definitions of Digital !CS
V'om:
I
:;:: C'IN
I
load gate
driving gate
(c)
FIGURE 1.4 (continued) (c) Charging of load capacitance
not instantaneous and a delay between the output
and input transitions is present.)
Ideal Input and
Output Gate Impedances
The transient response, as well as the driving ability
(referred to as fan-out and discussed in section 1.6)
of logic gates is directly dependent upon the gate's
input and output impedance. Figure 1.4a shows a
model of the input and output impedance of a logic
inverter. The input can be modelled as a parallel resistance and capacitance. The output is modelled as
resistance in series with a complemented voltage
source. Examining Figure 1.4b, which shows an inverter driving multiple (identical) logic inverters, it is
observed that the driving gate must provide enough
output current to drive all the load gates. Quantitatively speaking, for N load gates, the output current
must be
where the primed terms of Figure 1.4 refer to the load
gates. For a very large input resistance, the input current is zero and the driving capabilities are maximized. Ideally, an infinite input resistance is desired,
giving infinite driving capability.
Referring to Figure 1.4c, which shows cascaded
inverters with infinite input resistance, it can be seen
that the input capacitance of load gates must be
charged through the output resistance of the driving
inverter. Thus, a smaller output resistance will provide a larger charging current for the load capacitance and a faster switching time, suggesting an ideal
zero output resistance. Of course, a smaller input capacitance will also speed up the switching time of
load gates. This is provided when fewer gates are
attached at the output.
1.3 INVERTER VOLTAGE
TRANSFER CHARACTERISTIC
The voltage transfer characteristic (VTC) for logic inverters have been standardized. Figure 1.5 displays
the linearized form of an idealized voltage transfer
characteristic. Indicated on the output (vertical) axis
are the voltages VoH and Vm, which correspond to
the output high and output low voltage levels, respectively. On the input (horizontal) axis, the input low
voltage is Vn_ and the input high voltage is V11+ Note
that as the input voltage is increased from 0, V1L is
the maximum input voltage that provides a high output voltage (logical 1 output). Furthermore, V1H has
the definition of being the minimum input voltage
that provides a low output voltage (logical O output).
The values Vc)H, V0 1,, V,L, and V1H are referred to as
the critical voltages of the voltage transfer characteristic.
It is customary to list output voltages VoL and
VoH on the input axis. This is because these outputs
for the present inverter will be inputs to the next
] .3 Inverter Voltage Transfer Characteristic
5
Vour(V)
T
VOH
t
5
4.3
4
3
2
1
0.2 1..-'.,----+tt--------,------+--+-t--+------Vm (V)
2
3
4 I
5
V DL=O.~ 1
p.9
V 0 H=4.3
0.7
FIGURE 1.5 Idealized Inverter Voltage Transfer
Characteristic
gate. Additionally, in order that the high and low
voltage levels always be distinguishable, we must always have
FIGURE 1.6 Voltage Transfer Characteristic for
Examples 1.1, 1.2, and 1.3
Solution The highest and lowest output voltages
are 4.3 V and 0.2 V, respectively. Thus
and
Vi,H = 4.3
VoL
<
V1L
Manufacturers usually specify worst case values for
the four voltages Vrn,, VoL, V1H, and Vu.
One final critical point labeled on the VTC of
Figure 1.5 is the midpoint voltage VM, sometimes referred to as the threshold voltage Vth (not to be confused with the MOSFET threshold voltage Vr)- The
midpoint voltage is defined as the point on the transfer characteristic where VoUT = V,N and ideally appears at the center of the transition r_egion. VM c~n
be found graphically by superirnposmg (the urnty
slope) Your = V,N and finding its intersection with
the VTC.
Example 1.1 Voltage Transfer Characteristic
Critical Points
What are the critical voltages V oH, VoL, Yiu V,H, and
VM for the voltage transfer characteristic of Figure
1.6?
V
and
VOL= 0.2 V
The input voltage at which the output begins to drop
is 0.7 V. The output reaches its lowest value at an
input of 0.9 V. Hence
Vrt = 0.7
V
and
Vu 1 = 0.9 V
The point on the VTC at which the input and output
are equal is calculated to be 0.87 V. The midpoint
voltage is therefore
VM = 0.9 V
which is far from being ideal. (Note the output low
and high voltages are labeled on the input axis.)
6
Chapter 1/Properties and Definitions of Digital !CS
1.4 LOGIC SWING AND
TRANSITION WIDTH
digital circuits is referred to as voltage level degradation and is termed noise.
Two important parameters that are obtained from
voltage differences of VTC critical voltages on a mutual axis are logic swing and transition width.
Logic Swing
Logic swing is defined as the magnitude of voltage
difference between the output high and low voltage
levels. Hence, the logic swing is equal to
Transition Width
The transition width is the amount of voltage change
that is required of the input voltage to cause a change
in the output voltage from the high to the low level
(or vice-versa). Hence, from the VTC the transition
width is equal to
Example 1.2 Logic Swing and Transition
Width
Determine the logic swing and transition width for
the VTC of Figure 1.6.
Solution Substituting the critical points determined in Example 1.1 directly into the definitions for
the logic swing and transition width yields
VLs
= (4.3) - (0.2) = 4.1
Vyw
=
V
Noise Margins
Since variations in the high and low logic levels occur, terminology is used to describe these fluctuations. From the idealized inverter VTC of Figure 1.5
with the defined voltages VoH, V0u Vn-1, and VrL, the
following definitions are made:
VNMH
=
Vm1 -
VNML
=
V1L -
V111
and
Var_
where NM stands for noise margin, VNMH is the high
noise margin (for the logic 1 level), and VNML is the
low noise margin (for the logic 0 level). The voltage
noise margins represent a safety margin for the high
and low voltage levels. Extraneous noise voltages
must have magnitudes less than the voltage noise
margins. The exact magnitudes of the high and low
voltage level is not important. However, the high or
low magnitude of voltage must remain in the range
of voltages that provide positive noise margins.
Noise Sensitivities
The effects of input variations are quantified in terms
of the noise sensitivities. The high and low noise sensitivities are defined as the difference between the
input and midpoint voltage for V 1N at V 0H and V0u
respectively. Expressions for each are
VNsH
=
Vo11 -
VM
and
and
1.5
(0.9) - (0.7) = 0.2 V
NOISE IN DIGITAL CIRCUITS
Noise Immunities
The quantity noise immunity is the ability of a gate to
reject noise. The high and low noise immunities are
quantitatively defined as the quotient of the noise
sensitivities and the logic swing as follows:
Noise
Variations in the steady-state voltage levels of digital
circuits (i.e. the logical 1 and the logical 0 states) are
undesirable and cause logic errors if the fluctuation
from the desired or specified voltage levels is too
great. This variation of steady state voltage levels in
VNill
-
VNS/i
V
LS
and
1.6 Fan-In and Fan-Out
The maximum fan-out possible during the driving
gate's logical O output state is
Example 1.3 Noise Margins, Noise
Sensitivities and Noise Immunities
By direct substitution the noise margins
are
V NM// = (4.3) - (0.9) = 3.4 V
and
VN,vlL
= (0.7) - (0.2) = 0.5 V
Using the results of Examples 1.1 and 1.2, the noise
sensitivities are by direct substitution
(4.3) - (0.9) = 3.4
VNSI/
=
VNS/
= (0.9) -
V
and
(0.2) = 0.7 V
The noise immunities by direct substitution are then
(3.4)
VNIH
_ lourUow)
N
Determine the noise margins, noise sensitivities, and
noise immunities for the VTC displayed in Figure 1.6.
Solution
7
/mu -
['
IN
(/
OW
)
The maximum fan-out of a digital gate is limited by
both of the previous expressions and is determined
from the lesser of the two.
Further, the fan-out (and fan-in) is an integer
because fractions of gates have no meaning as indicated in the following example. Fan-in is of lesser
concern and is determined in a similar manner.
Example 1.4
Maximum Fan-Out
The inverter of Figure 1.7 has the terminal currents
I,N(low) = 2.43 mA (out), 11N(high) = 98.9 µA (in),
IourOow) = 54.3 mA (in), and Iocr(high) = 71.4 mA
(out). What is the maximum fan-out?
Solution The maximum fan-out for the driving
gate with logical 1 output state is
= -(-) = 0.83
(71.4111)
4.1
N1i;:,;1i
= (98 _9 µ,) = 721.9
and
For the driving gate logical O output state, we have
(0.7)
VNIL
1.6
= -() =
4.1
FAN-IN AND FAN-OUT
A general logic gate has multiple inputs and multiple
outputs. By multiple outputs we mean the output of
a given gate is connected to (driving) the inputs of
several load gates. The term fan-in is used to describe
the number of inputs of a gate. Similarly, the term
fan-out is used to describe the number of outputs of
a gate. The maximum fan-out of a digital logic circuit
is restricted by its input and output currents as discussed in section 1.2. Not mentioned in section 1.2
is that the input and output currents of a gate are in
general different for the logical Oand logical 1 states.
Also, the input and output currents can be either into
or out of the gate. The maximum fan-out possible
during the driving gate's logical 1 output state is
N
_ lm 17 (high)
1; N(high)
1,igi, -
(54.3111)
N101,, = (
) = 22.3
0.17
2.4 3111
The maximum fan-out is clearly limited by the output low state of the driving gate. The least greatest
integer of N 10w is 22, and this is the maximum fanout.
As will be seen with logic circuits utilizing MOSFETs, the input current of such a logic gate is limited
to the MOSFET's infinitesimal gate current. This
suggests that logic circuits using MOSFET technol-
Irn(low) = 2.43 mA (out)
IIN(high) = 98.9 µA (in)
FIGURE 1.7
Logic States
I0 ur(low) = 54.3 mA (in)
lour(high) = 71.4 mA (out)
Inverter with Terminal Currents for both
8
Chapter 1/Properties and Definitions of Digital JCS
ogy have an infinite fan-out. However, this is not the
case. As will be seen in Chapter 16, the fan-out of
MOSFET digital circuits is limited by the input
capacitance of the gate which is the gate oxide
capacitance.
As just mentioned, the transient characteristics of
digital circuits employing MOSFETs are limited by
the gate oxide capacitance. This will be further discussed in later chapters.
Switching Speed Definitions
1.7
Figure 1.8 shows an input pulse and the output response of a logic inverting circuit. On the output response, which does not necessarily reach V cc (i.e.
usually YoH < Yee), the 10% YoH and 90% YoH
points are marked on both the rising and falling
edges of the output voltage. The characteristic
switching speed times are then defined in general in
terms of these output values as follows:
TRANSIENT CHARACTERISTICS
Digital logic circuits have finite switching speeds.
That is, switching a voltage from high to low (or viceversa) requires a finite amount of time. Additionally,
when the input voltage changes from one level to
another, the output voltage response is delayed in
time. This is referred to as propagation delay. These
limitations are present for all circuits and in particular
digital logic circuits. For digital circuits employing
BJTs, these time limitations are caused by the time
required to store and remove charge from the base
region. Section 4.5 discusses methods for decreasing
the storage and removal times required by the base.
0
=
=
=
=
t., 11 =
toff =
td
tr
t,
tr
delay time
rise time
storage time
fall time
turn on time = td
turn off time = ts
~------------------+--------------- t(ns)
(a)
Your<V)
--------,----
-------------~-------------------,..-
90% -- -:- -- ---- --------- -- ------ ---- ---- ---- ----- -- ---'. --- --- ---- ---'
10%
- ·--r -- -- - --- . -- . ··--- ------ ----
------------
-
-----
'
(b)
FIGURE 1.8
+ tr
+ tr
Switching Speed Definitions: (a) Input pulse, (b) Output pulse
1. 7 Tr,msien t Characteristics
9
The overall propagation delav time t"(avg) is defined as the average of these two, given by
The rise time and fall time are the times associates
with charging and discharging load capacitances.
The delay time and storage time are associated with
stored charge of PN junctions. The turn on time and
turn off time are sums of these quantities. See Figure
1.8b.
Propagation Delays
Example 1.5
Figure 1.9 shows an input waveform and output response of a logic circuit. The output delay is typical
of all digital logic gates and represents the response
of the output voltage to a change in the input voltage. The 50% V0 H points are labeled on the rising
and falling edges of both the input and output waveforms. The 50% points are used to define the time
required for the output to respond to the input.
These response times are called the propagation delay
times. The /ow-to-11igh propagation delay time tl'LH
refers to the low-to-high transition of the output and
the high-to-low propagation delay time tp 11 L is for the
output high-to-low transition. TI1e definitions of tp 11 L
and t,u, are as shown in Figure 1.9.
Transient Characteristics
For the input and output waveforms of Figure 1.10,
determine
(a) the switching times t, and t 1
(b) the propagation delay times tl'LJJ and tl'llL·
Solution (a) By direct examination of Figure 1.10
t, = 168
11S
tr= 168
11S
and
Note that the output falling edge is to the left of the
output rising edge.
L___----------------------~--~--- ►
(a)
VOUT(V)
(b)
FIGURE 1.9
Propagation Delay Definitions: (a) Input waveforms, (b) Output response
t(ns)
10
Chapter 1/Properties and Definitions of Digital JCS
VOH
f---- --------------------------------------------------
VOL
i-------"
90% ·
10% ·---- ------------------------------------~--+----+----+-----+-----+-----+------1-----+----------+---,► t(ns)
100
200
300
400
500
600
700
800
900
1000
1100
(a)
VOH - - - - - - - - - - -...
I
90% ---- -----------------------
VOL'
~--+----+----+-----+-----+-----+--~-----------,1-----+----------+--~ ►
100
200
300
400
500
600
700
800
900
1000
t(ns)
1100
(b)
FIGURE 1.10
Input and Output Waveforms of Example 1.5
Solution (b) The propagation delay times are
tPI/L
= 100
115
Calculation of average power dissipation for actual
digital circuits entails the determination of the current supplied by the power source for both output
logic states and is determined as follows:
tl'LI/
=
115
Pcc(avg) = Icc(OH) + lec(OL) Vee
and
250
2
1.8
POWER DISSIPATION
In section 1.2, it is stated that an ideal gate has a
single power supply as shown in Figure 1.3a. The
power dissipation for such a gate is obtained by realizing it is equal to the power supplied. Furthermore, the power dissipated in this gate for the output
high (logical 1 output) and output low (logical Ooutput) states, P cc(OH) and P cc(OL), respectively, will
generally be different. Manufacturers therefore in
general specify the average power dissipation for a gate
with two possible output states as follows:
p
( )
Pcc(OH) + Pec(OL)
cc avg =
2
Some logic circuits have two power supplies, one
with a positive voltage and one with a negative voltage. Figure 1.11 shows such a gate. In this case, both
currents Ice and IEE are obtained for each of the output high and output low logic states. The average
PEE= IP.EVEE
FIGURE 1.11 Power Dissipation in a Logic Gate with
Two Power Supplies
Chapter 1 Problems
power supplied by this gate with two possible states
is then defined c1s
Pcdavg) + Pn (avg)
Icc(OH) + Icc(OL) V
cc
2
+ hi:(OH) + Ii:i:COL) V
2
E£
Pee = IccVcc
PEE
= IFEVEE
Note that the current IEE flowing into -VEE does yield
a positive power dissipation.
Example 1.6
Average Power Dissipation
Determine the average power dissipation for a gate
supplied by a 5 V power supply with I(OH) = 1 mA
and I(OL) = 3.18 mA.
Solution The average power dissipation by direct
substitution is
P(avg)
(1m) + (3.18111) ( )
=- - - - 5 = 10.5
2
m
W
However, as will be seen, faster propagation delay
times are achieved at the cost of increased power
dissipation. Conversely, lower power dissipation results in longer propagation delays. Thus, a practical
figure of merit used for digital logic gates is the product of the Jverage power dissipation P(avg) and the
average propagation delay time tr(avg). This is referred to as the power-delay product and is written as
follows:
PD
POWER-DELAY PRODUCT
= Prnss(avg)tp(avg)
This value is sometimes referred to as the speed-power
product. The smaller the power-delay product is for
a given gate, the more ideal the gate is. For the ideal
gJte, PD = 0. Note thJt since power has units of
watts and propagation delay has units of seconds,
the power-delay product has units of joules.
Example 1. 7
Power-Delay Product
The gate of example 1.6 has propagation de!Jy times
of tPHL = 1.4 ns and tPLH = 3.2 ns. Calculate the
power-delay product for this gate.
Solution The average propagation delay is
tp (avg) =
1.9
11
(1.411)
+ (3.2n)
2
=
2.3 ns
The power-delay product is therefore
PD = (10.5111)(2.311) = 24.2
Low power dissipation and short propagation delay
times are both desirable for digital logic circuits.
pf
CHAPTER 1 PROBLEMS
Ymrr(V)
1.1
1.2
1.3
1.4
1.5
The voltage transfer characteristic (VTC) for a logic
inverter is shown in Figure Pl.1. For this inverter,
determine the following:
(a) Vo11, You V1L, Vll 1, and VM
(b) the logic swing
(c) the transition width
(d) the noise margins, noise sensitivities, and noise
immunity levels
Repeat Problem 1.1 for the VTC of Figure Pl.2.
Repeat Problem 1.1 for the VTC of Figure P1.3.
Repeat Problem 1.1 for the VTC of the non-inverting
logic gate of Figure P1.4. (For a non-inverter, V1L is
the highest input that provides a low output and Vll 1
is the lowest input that provides a high output.)
Sketch the VTC for a logic inverter with V011 = 5 V,
Vm = 0.2 V, v,L = 1.4 V, and V11-l = 1.6 V. Also,
determine the logic swing, transition width, and the
noise margins.
3 - - -....
2
0.2
~ - - - - - + + - J - - - - - + - - - - - - + - - - - VIN
1
FIGURE Pl.I
2
3
(V)
12
Chapter 1/Properties and Definitions of Digital !CS
V 011,(V)
Yaur(V)
A
5-1----
51
4.3" --- - ------ 41-
4
I
3
3t
I
2f
2
1LJ:
i
'
o.~ .
I\~--------
I
,'
'--------++'-t'---+----+----t------.------+-----VIN (V)
1
1.
2
3
4
i
3
4
1.9
FIGURE Pl.4
Yaur(V)
-1.5
munity levels for the VTCs described in Problems 1.5 through 1.9.
VIN (V)
-0.5
1.11
Find the maximum fan-out for a gate with I011 =
12 mA (out), IoL = 7 mA (in), ! 111 = 0, and In. =
124 µ,A (out).
1.12
Find the maximum fan-out for a gate with Ioi 1 =
4 mA (out), IoL = 6.2 mA (in), I1r1 = 240 µ,A (in),
and Ill.= 0.
1.13
Find the maximum fan-out for a gate with IoL =
57.5 mA (in), 11L = 1.09 mA, and lu 1 = 0.
Find the maximum fan-out for a gate with IoL =
79.3 mA (in), I1L = 1 mA, and 1111 = 0.
-0.8
-1.0
-1.5
-1.6
1.14
1.15
FIGURE P1.3
1.6
Repeat Problems 1.5 for Vm1 = 3.6 V, VoL = 0.2 V,
ViL = 0.5 V, and V111 = 1.2 V.
1.7
Repeat Problem 1.5 for Vrn-i = 4.3 V, Vm = 0.5 V,
V1L = 0.9 V, and V1H = 1.1 V.
Repeat Problem 1.5 for VoH = -0.77 V, Vm =
-1.58 V, V 1L = -1.225 V, and V111 = -1.125 V.
1.10
I
121
~-1
-1.2
1.9
:
:'
0.2·'
5
1.4
FIGURE Pl.2
1.8
:
Repeat Problem 1.5 for V011 = 5 V, Vm = 0 V, V1L
= -2 V, and V1r1 = 3 V.
1.16
1.17
A non-inverter has a voltage pulse applied at the
input and the corresponding output voltage response as shown in Figure Pl.17. Determine the delay, rise, storage, and fall times. Also, find the propagation delays.
1.18
Repeat Problem 1.17 for Figure Pl.18.
1.19
Sketch the input and output waveshapes for a TTL
inverter with t, = 10 ns and t, = 30 ns.
1.20
Repeat Problem 1.19 for an STIL inverter with t, =
5 ns and t, = 7 ns.
1.21
Repeat Problem 1. 19 for an ASITL inverter with t, =
2 ns and t1 = 3 ns.
(a) Find the high and low noise sensitivities for the
VTCs described in Problems 1.5 through 1.9. Assume the midpoint voltage is in the center of the
transition region for each VTC.
(b) Using the results of part (a), find the noise im-
Find the maximum fan-out for a gate with IoL =
199 mA (in), I1L = 1.32 mA, and 1111 = 0.
A rookie electrical engineer designs a digital gate
with Irn 1 = 3.9 mA (out), Im= 5.4 mA (in), I111 =
0 mA, and 11L = 56 µ,A (in). Is there anything inherently wrong with this design? If so, what?
Chapter 1 Problems
13
VIN(V)
v•• t
I
I
~:- ~ - - - - - - - - - - - - - ~ - - - - - - - - - - - - - t ( µ s )
'
~ - 20~
Yom(Y)
'
VIT - - - - - - -90%
10%
~~-~~-----t(µs)
f'---15 __.!:
FIGURE P1.17
VIN(V)
t
v•• I
~•- ~ - - - - - - - - - - - - - - ~ - - - - - - - - - - t ( µ s )
90%
~------;--------------------~-------+---•t(µs)
~·-40---~
I
:---20~
I
I
•
FIGURE Pl.18
1.22
A gate is powered by a single 5 V supply. The current
delivered by the power supply is 4.2 mA for the output high state and 1.7 mA for the output low state.
What is the average power supplied?
=
0.52 mA and
1.23
Repeat Problem 1.22 for Icc(OH)
Icc(OL) = 42 µA
1.24
Find the average power supplied to the inverter of
Figure Pl.24.
14
Chapter 1/Properties and Definitions of Digital !CS
Vee= 5V
1.25
What is the power-delay product for P(avg) = 2 mW
and
(a) tp(avg) = 100 ns?
(b) tp(avg) = 250 ns?
(c) tp(avg) = 500 ns?
1.26
Repeat Problem 1.25 for P(avg)
0
FIGURE P1.24
= 10.2 mW.
In this chapter, two-terminal semiconductor PN
junction and MN Schottky diodes are introduced.
These important elements are used in digital logic
circuits to perform various logic operations, as well
as variable capacitors, DC voltage level shifting, and
clamping diodes at logic circuit inputs.
The chapter begins by describing semiconductor
diode circuit models. Diode-resistor logic is also presented. This is the simplest of all logic families but
also possesses many intolerable disadvantages. In
the latter sections, the function of clamping diodes
and level-shifting diodes are described.
mize the BJT performance and it is not feasible to use
additional layers for diodes.
Schottky-Barrier (MN Junction) Diodes
For MN diodes, the N- semiconductor region and a
particular metal form the Schottky diode. Schottky
diodes are rectifying junctions entirely analogous to
PN diodes, except that the P-region is replaced with
a particular metal that provides a barrier to electron
flow in one direction. Not all metals provide Schottky
diodes with N doped silicon.
When N-type silicon is the semiconductor material, platinum silicide (Pt 5 Si 2) is the metal most often used to form the MN Schottky diode. This is accomplished by depositing Pt on Si and heating
(annealing) at 600°C to form Pt 5 Si 2 .
PN JUNCTION AND
MN SCHOTTKY DIODES
2.1
PN junction semiconductor diodes and Schottky barrier MN diodes are important elements in digital integrated circuits. The circuit symbols for these two
terminal devices are shown in Figure 2.1 along with
definitions of forward current and voltage. Diodes
are used in bipolar IC families as actual circuit components, as well as clamping diodes at logic circuit
inputs. When used as clamping diodes, their purpose
is to reduce transient voltages that result from
switching transitions. However, these clamping diodes do not affect normal circuit operation. Figure
2.2 displays device cross-sections for digital IC PN
and MN diodes. Typical cross-sections arc indicated
for the case of a double diffused implanted epitaxial
bipolar IC. The particular diode geometries of Figure
2.2 are chosen because of fabrication compatibility
with the double diffused epitaxial BJT discussed in
the following chapter.
DIODE MODELLING
2.2
Shockley's Current-Voltage Expression
The theoretical current-voltage relation that represents the DC current dependence on voltage for PN
junction and MN Schottky diodes is
10 = 15 (ev,,i<t,r - 1)
where
I5 = reverse saturation current [A]
cf>T = thermal voltage [V] calculated by
kT
q
q>T = -
= Boltzmann's constant= 1.34
T = Temperature [°K]
k
x 10- 23 J/°K
q = elementary electronic charge
= 1.60 X 10- 19 C
PN Junction Diodes
This expression, often referred to as Shockley's
equation, is temperature dependent, as seen by the
Usually, the PN junction diodes utilize two out of the
three regions of a bipolar junction transistor, instead
of a separate device structure. This is because the
various P and N layers have been selected to opti-
temperature dependence of the thermal voltage q>y.
The reverse saturation current is the minute leakage
current that flows through a reverse biased diode and
15
16
Chapter 2/Diodcs
'it
.
(a)
Shockley's Equation
at Room Temperature
(b)
At room temperature (T = 27°C or 3OO°K) ¢ 1
is given by
FIGURE 2.1 Diode Symbols: (a) PN junction diode,
(b) MN Schottky barrier diode
PN junction
;
ohmic contact
P+
(
--
'
N- epitxiai layer
-(
-
)
N+ buried layer
I
_ \ P+
/
)
Tips, Tricks, and Gimmicks
__
)
Note that the 1/¢T term in the exponential has
a magnitude of approximately ·40 for room
temperature leading to the more compact expression
I
-1
(
P substrate
20
_.
K = (1.34 X 10- )(300) _
¢,(3000 )
(1.6Ox10-l'J)
-25.9111V
In(T = 3OO°K) = I 5 (e 40 vn - 1)
which is valid only at room temperature.
\
(a)
Solution By direction substitution
Schottky MN contact
Si02
/ohmi'.:,contact
~\-_-\-~+-}_->-'.--,~.~~~,{
\
L
,
~
P substrate
In(VD
Io(Vn
I
,
(
~
In(Vo
(b)
In(Vn
ln(Vn
In(Vn
In(Vo
=
=
=
=
=
=
=
(1O-14)[e40(0
0.2)
oo- 14) [e4o(o 21
0.5)
oo-14)[e40(05) - 1)]
0.7)
(10-14)[e40(01) _ l) l
is typically a pA or less for PN junction diodes and a
µA or less for MN Schottky diodes.
The following examples indicate magnitudes for
positive and negative diode voltages.
Example 2.1 Relative Forward-Biased
PN Junction Diode Current Magnitudes
Use Shockley's expression to determine the diode
current for V0 = 0.1, 0.2, 0.5, 0.7, 0.8, 1, and 2.3 V.
Use Is = 10- 14 A and assume room temperature.
I) _
_
0.8)
(1O-H)[e40(0~) _ 1)]
1.0)
(1O-l4)[e4ll(IO) _ 1)]
2.3)
oo-14) [e40(23) _ 1)]
=
FIGURE 2.2 Diode Cross Sections: (a) PN junction
diode, (b) MN Schottky barrier diode
l)j = 536 JA
l) l = 29.8 pA
0.1)
=
=
=
=
4.85 µA
14.5 mA
790 111A
2.35 kA
9.02 X 10 25 A
As can be seen, the diode current's exponential dependence on VD is quite pronounced. For a diode
voltage of 0.5 V the diode current is a few microamps
and approaches zero rapidly for smaller voltages. For
currents in the milliamp range, the diode voltage is
0.7 V and the diode current reaches hundreds of 111i//iamps for another 0.1 V increase to 0.8 V. For a diode
voltage of 1 V, the current magnitude is at a normally
unobtainable hundreds of amps. Note that for VD =
2.3 V the diode current is an unprecedented 9.02 X
10 25 A and the IDVI) power dissipated in the diode
exceeds the entire power output of our sun. The diode would surely become damaged long before this
would happen.
2.2 Diode Modelling
Example 2.2 Relative Reverse-Biased
PN Junction Diode Current Magnitudes
17
Tips, Tricks, and Gimmicks
ex >> 1 or e-x << 1
Use Shockley's expression to determine the diode
current for VD = -1, -10, -100, and -200 m V. As
in Example 2.1 use 15 = 10- 14 A and assume room
temperature.
The two previous examples suggest the following approximations:
Solution By direct substitution
and
Io(Vo = -1 mV) = (10- 14)[e'l0(-llll)
IoWo
InWo
-
> 0.1) = fsev[)1<1>1
< -0.1) = -]5
1)]
= -392 aA
InWo = -10 mV) = (10-14)[e40(-10,11l - 1)]
= -3.30 fA
Io(VD
=
-100 mV)
=
(1o-14)[e40(-100111)
1)]
-9.82fA
][)(VD= -200 mV) = (1o-14)[e40(-200111) - 1)]
-10.0 fA
-10-14 A
As seen, at V0 s -0.2 V the reverse diode current
has a magnitude equal to 15, accurate to three decimal places. Hence, 15 is called the reverse saturation
current.
The following section utilizes the computational infonnation of the previous examples in suggesting a reasonable piecewise linear model for diodes.
Piecewise Linear Diode Model
Example 2.1 indicates that a forward diode voltage
of 0.5 V corresponds to a diode current of only a few
microamps. Furthermore, increasing the forward
voltage to 0.8 V increases the current to hundreds of
milliamps. For currents up to a few milliamps, which
is a practical order of magnitude for active IC device
currents, the diode voltage is approximately 0. 7 V.
This suggests that a practical diode model for hand
l>t- -
cutoff
- - - - - - - - - / - ~ ~ ~ ~ ~ ~ - - - VD (V)
Vo(ON)=0.7
(a)
FIGURE 2.3
(b)
Piecewise Linear Diode Model: (a) Diode current versus diode voltage, (b) Diode symbol
18
Chapter 2/Diodes
TABLE 2.1
Diode Modes of Operation
PN Junction Bias
Reverse
Forward
Cl){1
junction capacitance [F]
Mode of Operation
Cutoff
Conducting
¢n
= junction potential
m
= grading coefficient
(typically 0. 7 to 0.9 V)
TT
analysis is the piecewise linear model shown in Figure 2.3. This model has two linear regions:
I0 = 0 for V0 :s: V0 (0N)
and
Vn = Vi/ON) for I 0
2:
0
where a practical value for VD(ON) is the aforementioned 0.7 V. Thus, for diode voltages less than
V0(ON), the diode is cutoff and for diodes conducting forward current, a forward voltage of 0.7 V is
present. A similar model for MN Schottky diodes is
also used but with a s1T1aller turn on voltage
Vstm(ON) of 0.3 V for silicon.
From the above discussion, a diode can be seen
to have two modes of operation, cutoff and conducting, the operating mode of a diode depe'.,ding upon
the magnitude and polarity of the diode junction bias
VD. These modes and the corresponding junction biases are tabulated in Table 2.1. The diode breakdown
region of operation is avoided in digital circuits and
no 1nodeling for this mode is necessary.
2.3
DIODE CAP A CIT AN CE
A PN junction diode has a capacitance associated
with it due to charge in the depletion region and for
forward bias, charge stored in the semiconductor
bulk regions due to injected minority carriers. The
capacitance contributes to transient response limitations. Furthermore, this capacitance must be fully
charged to switch the diode into the conducting state
and discharged to switch the diode to the cutoff state.
Thus, the capacitance of a diode is voltage-dependent and can be represented by the expression
= zero-bias (i.e. VI) = O)
=
(m = ½ or 1/3 for digital IC diodes)
minority carrier transit time
It is further noted that the first term is due to stored
minority charge, whereas the second term is due to
depletion region charge. The magnitudes of these
pJrarneters can be calculated from the diode's physical attributes and fabrication processing paran,eters,
such as doping densities.
Varactor Diodes
The PN junction capacitance can be utilized in ICs
by applying a negative bias to a diode. Diodes used
for this purpose are referred to as varactor diodes and
have the modified diode circuit symbol of Figure 2.4.
For this device, the forward diode voltage VD is negative. As will be seen in Chapter 9, advanced STrL
logic families utilize varactors in a configuration that
improves the overall transient response of the logic
gate.
2.4
SPICE DIODE MODEL
This section introduces the SPICE diode model and the
physical significance of each cf the SPICE diode model
pa m111etcrs.
The large signal diode model used in SPICE is
shown in Figure 2.5.
SPICE Diode DC Characteristic
"n1e nonlinear current source lb has a value according to the empirically modified Shockley expression
Ib
- 1)
.-------t>l 1---FIGURE 2.4
where
= JS(evniN<t,,
Varactor Diode (Voltage Dependent
Capocitor for Vn < 0)
19
2.5 Diode-Resistor Logic
+
Q0 = TT X IS(ev1,1N,t,T
+ CJO
Rs
_
f" (1 - ~rM
1)
-
dV
For V0 > FC</> 0 , where FC is a model parameter
specified as a fraction, the forward biased diode capacitance is calculated by the expression
__J
I'D
FIGURE 2.5
SPICE Diode Model
where the quantity N is called the emission coefficient
and is typically 1 but may be slightly higher as sometimes is the case for Schottky diodes. The resistance
RS in Figure 2.5 represents the sum of the ohmic
resistances on both sides of the diode junction. The
parameters IS, N, and RS are used to calculate the
DC response of the diode in SPICE and are tabulated
in Table 2.2.
[
C]O
+ --"---~
(1 -
0)M
1 - FC(1
+ M) +
MV]
<PT
X ----------
(1 -
FC)(1+M)
The parameters TT, CJO, VJ, M, and FC, which determine the transient response of the SPICE diode,
are tabulated in Table 2.3. Note that TT and CJO
both have default values of zero. Therefore, in order
for SPICE to calculate a transient response, one or
both of these values must be specified by the user.
SPICE Diode Transient Response
The transient response of the diode in SPICE is calculated considering the capacitor C0 . This variable
capacitor is determined by the expression
= TT _I_S_ ev,,1N<1,, +
C
o
N<f>T
C]O
(
1v1
1 - ~;
)
The capacitor C 0 can be equivalently represented as
a charge storage element with
TABLE 2.2
2.5
DIODE-RESISTOR LOGIC
This section presents the simplest logic circuits that
can be constructed from semiconductor devices.
These logic circuits consist only of diodes and resistors and are referred to as members of the dioderesistor logic family. The two logic functions available
with diode-resistor logic are AND gates and OR
gates.
SPICE DC Diode Model Parameters
Symbol
Name
Parameter
Units
Default
Is
IS
RS
N
Saturation current
Parasitic resistance
Emission coefficient
A
.(1
lE-14
0
1
Rs
Typical
lE-14
10
1
TABLE 2.3
SPICE Transient Diode Model Parameters
Symbol
Name
Parameter
Units
Default
Typical
cDo
TT
C]O
</Jo
VJ
s
F
V
m
M
FC
Transit Time
Zero-bias junction capacitance
Junction potential
Junction grading coefficient
Forward bias depletion capacitance coefficient
0
0
1
0.5
0.5
0.1NS
2PF
0.8
0.5
TT
20
Chapter 2/Diodes
Diode AND Gate
Diode OR Gate
Figure 2.6a displays the first circuit belonging to the
diode-resistor logic family. It is easily seen that this
circuit provides the AND function. If any input V1N
is less than VDc - V 0 (ONt then the corresponding
input diode is allowed to conduct and
The diode-resistor circuit in Figure 2.7a provides the
OR logic function. With all inputs less than VD(ON),
all input diodes are cut-off and
VouT =
Also, for V1N
=
ViN +
VouT = 0 = VcJL
If any inputs are greater than V D(ON), a current then
Vo(ON)
flows through Rand the output voltage is
0,
VouT
VoUT = Vo(ON) = VoL
With all inputs greater than Vnc - VD(ON) all
input diodes are reverse biased (cutoff) and no current flows through R. The output-high voltage is
therefore
=
- Vo(ON)
The VTC for the diode-resistor OR gate is shown
in Figure 2. 7b where V1N = ViNA = V1r--.:ll• This VTC is
also piecewise linear. The output begins to rise from
a minimum Vm = Vn(ON) at an input of V1N
VD(ON) and rises with unity-slope.
The current through R is
VoH
= VIN
Voe
The voltage transfer characteristic of this dioderesistor AND gate is shown in Figure 2.6b, where V1:---:
= VIN/\ = ViNB· Note that the VTC is piece-wise linear. The output rises from a minimum voltage of VoL
= VD(ON) with unity slope, and reaches a maximum
ofVoH = Voe at an input of
Example 2.3
Diode-Resistor AND Gate
For the two-input diode-resistor AND gate of Figure
2.6, show that if V1r--.:/\ is 1 V above ViNB, DA is cutoff.
Solution To show that DA is cutoff for this situation
in Figure 2.6, consider the voltage across each input
diode, given by:
and
V1N = Vix: - Vo(ON).
V TN.A
0-------Klf--------j
D.
Vm.e o - ~ 1<1----·
----------D
Vour
~ - - - - - - - - - + - - - - - - - . V m (V)
Voc- Vo(ON)
(a)
FIGURE 2.6
Diode AND Gate: (a) Circuit, (b) Voltage transfer characteristic
(b)
2.6 Level-Shifted Diode-Resistor Logic
21
YourCV)
DA
VIN.A
o--------{>1---
v!NJj
o-------------1>1- - -
---0
V our
De
R
- - - - - - - - - - - - - - - - - - V I N (V)
V 0 (0N)
(b)
(a)
FIGURE 2.7
Diode OR Gate: (a) Circuit, (b) Voltage transfer characteristic
Assuming D /\ is conducting, the junction voltage for
DI\ is VD/\ = 0. 7 V. The output voltage in Figure 2.6
is then Your = VINA + 0.7 V and the voltage across
D8 is
+ 0.7) - ViNB
By substitution of V1N/\ = V1Ns + 1 V, the voltage
Voll
=
W1NA
across DB is
v[)Ll
1f
= (VIN/l + 1) + 0.7 -
VwB
= 1.7 V
However, this diode voltage is not attainable and indicates that the original assumption of DA conducting is not correct. Hence, DA is open circuited. With
DA open, D 8 is shorted and the output voltage is V,Ns
+ 0.7 while
VoA
=
VINA -
=
ViNA
= (1)
+ 0.7)
- ViNB - 0.7
(0.7) = 0.3 V
W1NB
further indicating that D /\ is cutoff.
Tips, Tricks, and Gimmicks
Diode Logic: "IN" or "OUT"
A simple memory tool for diode as well as transistor logic circuits is the correspondence between the following words:
IN= OR
OUT= AND
where "IN" and "OUT" refer to the input diodes pointing 0_to the logic circuit or out of the
logic circuit. This correspondence is always true
in logic circuits with diodes at the input. Thus,
since OUT and AND have three letters, while
IN and OR have two letters, a no-thought easy
method of circuit determination is provided.
2.6 LEVEL-SHIFTED
DIODE-RESISTOR LOGIC
The VTCs of the diode-resistor AND or OR gate of
the previous section both rise with unity slope. However, each is offset from the origin with the output and input voltages never zero together. This
offset is referred to as voltage degradation, which is
a reduction or increase in the output voltage level
by one diode drop [V 0 (0N)]. Voltage degradation is easily corrected for by including an additional diode at the output, referred to as a
level-shifting diode, as explained in the following
sub-sections.
22
Chapter 2/Diodes
Your(Y)
!
I
Yee
0
I~~
D,
y IN,A
D1 open
YOH-
~-,<Je-------~--(1
DL
D.
YIN~O---«l<J1----~-x_ __,l>*l------(Q
1
Your
''-------1
__
D_co_pe_n__,/__________ y
OL
(b)
(a)
FIGURE 2.8
Level-Shifting Diode AND Gate: (a) Circuit, (b) Voltage transfer characteristic
11,e output high voltage is then obtained by either
Level-Shifted AND Gate
Figure 2.8a shows the level-shifted diode-resistor
AND gate. A level-shifting diode D 1_ has been added
to the diode-resistor AND gate of the previous section along with a second resistor RL connected from
the output to a negative voltage source -Vrn for
generality.
If any input voltage is low, its corresponding input diode is conducting and the voltage at the point
labeled Xis
The output voltage with DL conducting is then
VouT
=
Vx - Vo1,(0N)
=
V1N
Vo11
= Vee - IDL(ON)Ru - VDI (ON)
_ V
-
cc
_ Vee+ V[E - V[)J_(ON)
R + R
Ru
/I
L
- Vm(ON)
or
Vnu = -Vic[
+ lrn(ON)R1,
Vee+ Vu: - VDL(ON)
VLE + _____::c.=___...c=_ __:_:..::....:__ _;_ R1
Ru+ RL
·
The voltage transfer characteristic for the levelshifted diode-resistor AND gate with VrN = VrNA =
V1:--:R is shown in Figure 2.86. Note that the VTC
passes through the origin.
Note that for an input below -VEE, Vx is less than
-V Er: + VD(ON) and DL is cutoff. Thus, the output
low voltage of this circuit is
Level-Shifted OR Gate
Furthermore, for all input voltages above Vee VD(ON), all input diodes are cutoff. The output voltage is then obtained by first solving for IDL by writing
KVL along dashed path 1 of Figure 2.8 in the form
Figure 2.9a displays a level-shifted diode-resistor OR
gate. Similar to the level-shifted diode-resistor AND
gate already discussed, a level shifting diode DL is
added with a resistor RH between the output and a
high voltage source Vcc•
With all inputs low, all input diodes are cutoff.
The output low voltage is obtained by first solving
for the current through D1_ following dashed path 1
of Figure 2.9a to obtain
Vee
+ VEE - V1x(ON)
IDI = - - - - - - - - .
Ru+ R1,
'2.7 Clamping Diodes
23
DL open
VOH
X
VIN.A O----------J-:>1---~---K:1------+---~-------( J
--------------------
Your
-- ---1------''
(b)
(a)
FIGURE 2.9
Level-Shifting Diode OR Gate: (a) Circuit, (b) Voltage transfer characteristic
IoL
Vee+ VEE - VoL(ON)
=--------
Ru+ RL
The output low voltage is then obtained by either
or
VouT
= - VEE +
+ V DL (ON)
Vee + VEE - Vo(ON) R
-Vu:+
R +R
L
IoLRL
II
L
+ V 0 L(ON)
If either input is high, its corresponding input
diode is conducting and the voltage at the point labeled Xis
Example 2.4
AND Gate
Level-Shifted Diode-Resistor
Find the output low and high voltages for the level
shifted diode-resistor AND gate shown in Figure
2.8a. Use Vee= 4 V, -VEE= -4 V, VD(ON) = 0.7
V, RH = 1 k!l and RL = 2 kfl.
Solution The output low and high voltages for the
level-shifted diode-resistor AND gate are found by
direct substitution into the expressions derived in
this section to obtain
VOL= -4 V
and
Von= (-4) +
= 0.87
(4) + (4) - (0.7) ( k)
(lk) + (2k)
2
V
Vx = VIN - VD1(0N)
The output voltage is then
Von= Vx + Vo1(0N) = V1N
The voltage transfer characteristic for the levelshifted diode-resistor OR gate with V 1N = VrNA =
V1N 11 is shown in Figure 2.96. Note that this VTC
passes through origin.
2. 7 CLAMPING DIODES
When the input to a gate is switched high-to-low,
the input voltage sometimes swings beyond 0 V. This
is referred to as ringing and may cause physical damage to the gate itself. Connecting diodes to each input of a gate as in Figure 2.10 considerably reduces
24
Chapter 2/Diodcs
v,NA o---T---------v 0---_J____ ____ _
INB
I
I
I
I
v!NC f l - - - - - - - + - - ~ - ~ - - - - - - -
¥
input
stage
I
V-=?
VIN;
t
ti:
*
I
FIGURE 2.11
Input Clamping Diodes
such problems by preventing the inputs from falling
below one diode drop of -0.7 V. Furthermore, as
long as the input voltages are positive, these additional input diodes are open circuits. As will be seen
in Chapter 9, advanced TTL sub-families employ
clamping of the output for analogous purposes.
2.8
i
I
+
Vo(ON)
I
J_
FIGURE 2.10
+
Vo(ON)
Level-Shifting Series Diodes for Example
2.5
ensures the desired operation by allowing only one
driver to be on at a given time.
The conducting diode voltage V0 (0N) = 0.7 V
is an ideal element for these purposes. As will be
seen in the next chapter, the base-emitter portion of
a BJT can also be used for level-shifting and has the
advantage of providing additional driving current.
LEVEL-SHIFTING DIODES
It is often desired to change the voltage level across
particular portions of digital circuits. Recall that in
section 2.6 it was shown that diodes can be used to
level shift the output voltage. Another use of the diode forward voltage is to ensure that sub-circuits
with complementary objectives are not conducting
sinmltaneously. For example, certain BJT digital gates
employ two output drivers. Additionally, only one
driver is on for the output-low state while only the
other is on for the output-high state. Placement of a
voltage level-shifting device between the two drivers
Example 2.5
Level-Shifting
What is the level-shifting voltage VsHir-r of the series
diodes in Figure 2.11? Assume both diodes are forward biased with a forward voltage of VD(ON) =
0.7V.
Solution The level-shifting voltage of the diode
configuration is obtained by adding the voltages
across each diode yielding
V5111 n = 2 V 0(0N) = 2(0. 7) = 1.4 V
CHAPThK 2 !'KUHL.EMS
2.1
Draw the two-dimensional cross section of a PN
junction diode and label the different regions. Indicate the doping densities and label the ohmic contact.
2.2
Repeat Problem 2.1 for the Schottky MN junction
diode. Clearly indicate the Schottky MN contact.
2.3
What type of metal are most often used in Schottky
MN silicon diodes? Describe the metal deposition
process.
2.4
Using Shockley's Ill-VD expression for a PN diode,
calculate the reverse saturation current for 10 =
1 mAand VI)= 0.7V.
Chapter 2 Problems
2.5
Under forward bias conditions, use Shockley's
equation to calculate the change in diode voltage
that results when the diode current is increased by
a factor of 10.
2.6
Consider two PN junction diodes with reverse saturation currents of Is 1 = 10-H A and 152 = 10 - 12 A
(a) Calculate the diode current and individual voltages if the diodes are connected in series with
1 V applied across the combination.
(b) Calculate the voltage and individual currents for
the diodes connected in parallel with a total of
1 mA conducting through them.
2.7
2.8
Voe
R
DA
2.9
Calculate I1, from Shockley's equation using ¢ 1 =
0.0259 V and Is = 10- 14 A for VI)= 0.1, 0.2, 0.5, 0.7,
0.8, and 1.0 V. Compare with the values in Example
2.1.
2.10
Repeat Problem 2.9 for negative VD values of -1,
-2, -10, -200, and -500 mV. Compare with Example 2.2.
2.11
Plot values of In JD versus VDs for a diode using
Shockley's expression. Use Is = 10-i-1 A for ¢T =
0.0259 V.
2.12
Repeat Problems 2.9, 2.10, and 2.11 for a diode with
ls = 10 1" A
2.13
Repeat Problems 2.9, 2.10, and 2.11 for a diode with
ls = 10 IJ A
2.14
Calculate the diode capacitance CD using the typical
parameters from the SPICE tables for VD = 0.3 V
and CJO = 10 pF.
2.15
Repeat Problem 2.14 for VD= -0.5 V.
2.16
For the diode AND gate of Figure P2.16, show that
the output low voltage level is degraded by the forward voltage drop of one diode. For input voltages
of O or 5 V, consider all combinations of inputs and
calculate the corresponding outputs. Let V1x: = 5 V.
VIN.A
0
VIN.B
0--
1<1~--D.
FIGURE PZ.16
Consider a Schottky MN diode with current-voltage
variation given by the Shockley equation where Is is
several orders of magnitude larger than that for the
PN diode.
(a) Calculate the value of Is based upon a current
and voltage measurement given by In = 1 mA
and Vn = 0.3 V.
(b) For a PN diode with the same ID-VD variation,
the reverse saturation current is 10 14 A If the
diode voltage is Vu = 0.3 V, what is the diode
current?
Use Shockley's expression to determine the diode
currents for an MN Schottky diode for V0 = 0.1, 0.2,
0.5, 0.7, 0.8, 1, and 2 V. Use Is = 10 nA.
25
DA
VIN.A
D.
VIN.B
R
JFIGURE P2.17
2.17
For the diode OR gate of Figure P2.17 show that the
output voltage level is degraded by the forward voltage drop of a diode. Additionally, if this output is
the input to another similar OR gate, show that the
output is degraded by an additional diode drop.
2.18
Sketch the vrc (VOUT versus V1N) for the diode
level-shifting circuit shown in Figure P2.18 over the
range -Vue :s V1N :s VDc• Use Vuc = 4 V and R11
= RL = 1 k!1. Also, let V0 (ON) = 0.7 V.
2.19
Repeat Problem 2.18 for the diode level shifting circuit shown in Figure P2.19.
FIGURE P2.18
26
Chapter 2/Diodes
2.20
The circuit shown in Figure P2.20 is a diode AND
gate with a level-shifting diode DL. Sketch the vrc
for Vocr versus v,N = v/\ with Vil = 0 and 5 V. Let
VDc = 5 V, -VDc = -5 V, R11 = 5 kfl, RL = 100
kfl, Vl)(ON) = 0. 7 V, and consider O '.'S V/\ '.'S 5 V.
2.21
Repeat Problem 2.18 for the diode level shifting OR
gate of Figure P2.21. Let v,/\ = Vrn = v,N and
V 0 (0N) = 0.7 V.
FIGURE PZ.19
DA
VIN.A
o-~
-t>to.
VIN.A ( } - - - K l - - - - ,
VIN.B o-------t>f~
-Vgg = -5 V
FIGURE PZ.21
FIGURE PZ.20
JU
In this chapter, the fabrication sequence of NPN and
PNP bipolar junction transistors is described. The
Ebers-Moll BJT model and the BJT modes of operation are then discussed. The Gummel-Poon BJT
model and the SPICE BJT model are then described.
and this is accomplished by applying the most negative voltage in the circuit (usually ground) to the
substrate.
3.2
3.1
CTION
JUNCTION ISOLATED NPN BJT
OXIDE ISOLATED NPN BJT
For the oxide isolated NPN BJT of Figure 3.2, a
p- epitaxial layer is grown after the buried layer is
formed. This is followed by oxide layer growth, silicon nitride (Si"N 4) layer deposition and a second oxide layer deposition (see Figure 3.2b). The top Si0 2
layer is then used as a mask to selectively remove
SbN 4 and then Si0 2 . Trenches are then etched in the
P-type epitaxial layer resulting in the cross section of
Figure 3.2c. Another Si0 2 growth step is then carried
out which consumes silicon (as usual) from the
P-epitaxial region, with 0 2 supplied at the surface.
The Si0 2 layer grows downward as well as upward
from the silicon surface. After this step, the crosssection shown in Figure 3.2d results and the Si0 2
trench completely surrounds and isolates the P-type
epitaxial region. The N+ buried layer and the P-substrate form an isolation junction on the bottom.
The last silicon processing steps for this are a
deep N+ collector diffusion, p+ base diffusion, and
N+ emitter diffusion. This is followed by metalization. Figure 3.2e displays the final device crosssection for the oxide isolated NPN BJT and Figure
3.2f shows the 3-D version.
In the fabrication sequence of Figure 3.1, an N-epitaxial layer is grown on the P-substrate, the isolation
diffusion is performed, and two diffusions (or implants) are used to form the emitter and base regions.
The resulting NPN transistor is referred to as a double-diffused epitaxial device. It should be noted that
while this sequence of processing steps for the NPN
BJT is taking place, other devices are fabricated at the
same time at other surface locations. For example, a
resistor using the P base diffused region is formed at
the sa1T1c time as the base is diffused or implanted
by providing an additional window in the pattern.
Both NPN BJT processes begin with a P-type
substrate and buried layer formation, which involves
a N+ selective diffusion or implant through oxide
windows. This step is followed with the growth of
an epitaxial silicon layer. However, the epitaxial layer
is N- in one case and p- in the other. Continuing
with the processing steps in Figure 3.1, after the
N-epitaxial layer growth, the P isolation diffusion is
carried out (Figure 3.lb), followed by the P-base selective diffusion/implant (Figure 3.1c). The next processing step is an N+ emitter-collector diffusion implant (Figure 3. ld) and finally metalization. Figure
3. le displays the final cross-section for the double
diffused epitaxial NPN BJT and Figure 3. lf shows a
3-D version without metalization. Note again that
the isolation junction must always be reverse biased
3.3
MULTI-EMITTER BJT
Other BJTs that are widely used in TTL and STTL are
displayed in Figure 3.3. These devices provide mul-
27
28
Chapter 3/Bipolar Junction Transistors
N+ buried layer
\
\
P substrate
~\~T
P+
(a)
~
/
p
·
~--
~
N+~
:
N- epttaxial layer \
N+ buried layer
)
P+
~
)
P substrate
j' r
N- epttaxial layer \
P+
---{~---N-+-b-un-'ed.~lay_e_r- - - _ ) ~ - ~
-- \
--
(d)
I
)
P subsirtt.itt
\
(b)
P+
c--i
p
P+
N- epitaxial layer
-------~
N+ buried layer
P substrate
P+l'
/
IN+p
\_~-----
~~
___
N· epHaxial layer
_i
\
N_+_b_uri_ed_l~ay~er_ _ _ _) - - -
l
P+ )
f
P substrate
I
--~
)
(e)
(c)
(f)
FIGURE 3.1 Junction Isolated NPN BJT Process
Sequence: (a) Buried layer diffusion/implant,
(b) N- epitaxial layer growth and P+ isolation diffusion,
(c) P base diffusion/implant, (d) N + emitter and collector
diffusion/implant, (e) Metalization, (f) Three-dimensional
cross section (without metalization)
tiple inputs for these logic families and consist of a
multi-emitter NPN BJT. Essentially no additional
processing steps are required for their fabrication.
However, more chip area is used. Multi-emitter NPN
BJTs are shown using both the junction and the Si0 2
isolation in Figure 3.3a and b respectively.
3.4
SCHOTTKY-CLAMPED BJT
Figure 3.4a displays a modified NPN BJT which is
called a Schottky-clamped BJT. The base contact is
extended over the N collector region, thus placing a
Schottky MN diode in parallel with the base-collec-
3.4
Schottky-Clamped BJT
Si02
Si 3N4
29
-~---7
\
____ __ _____ N+ buried layer
__,1
I
P substrate
-
\
--------------"
1
(a)
Si 3 N4
Si02
i
S10,
(
}
P· epitaxial layer
~
P substrate
N+ buried layer
(d)
P substrate
Si02
8
(b)
u
I
\
--c
\
P· epitaxial layer
N+ buried layer
P substrate
C
S10,
Si 3 N4
Si02
E
~~
P substrate
s
(e)
(c)
s
(f)
FIGURE 3.2 Oxide Isolated NPN BJT Process
Sequence: (a) Buried layer diffusion/implant,
(b) P- epitaxial growth, Si0 2, Si 3 N 4, Si0 2 growth,
(c) Trenches etched in P- epi-layer, (d) Oxide growth,
!
(
N+ buried layer
----------- - - ------
- -
P- epitaxial layer
S10,
(e) N+ collector, P+ base, N+ emitter, aluminum
metalization, (f) Three-dimensional cross section
(without metalization)
30
Chapter 3/Bipolar Junction Transistors
Si0 2
"'
P+
P substrate
(a)
Si02
e
...
....
...,
,,..
C
C
C
""
SiO,
P substrate
s
(b)
FIGURE 3.3
Multi-emitter NPN BJTs: (a) Junction isolation technology, (b) Oxide isolation technology
Si0 2
E
B
s
C
P+
N+ buried layer
P substrate
(a)
Si02
E,
E,
E,
B
C
s
P+
N+ buried layer
P substrate
(b)
FIGURE 3.4
Schottky-clamped BJTs using Junction Isolation: (a) Single emitter, (b) Multi-emitter
3.6
tor PN junction. The device has a huge advantage
over the standard BJT, as we will see.
Multi-emitter BJTs are also converted to
Schottky-clamped BJTs by placing a Schottky MN
diode in parallel with the PN base-collector junction
as shown in Figure 3.4b.
3.5
hi,ndVllE) = lcs(e\lml<br -
1)
lruic(Vllc) = lcs(e\11<c 1<l'r
1)
!
I,
collecto,
DBC
-
VBC
+
IB
~
base ,
+
DBB
VBE
3.6 THE EBERS-MOLL BJT MODEL
A simple model that represents the first order DC
operation of a BJT is the Ebers-Moll model (1954),
FIGURE 3.5
Lateral PNP BJT
31
shown for an NPN BJT in Figure 3.6. This model can
be used to calculate the terminal currents for all
modes of operation with the same set of two equations. The base-emitter and base-collector PN junctions are represented by Shockley diodes labeled DBE
and DBc• The currents through these diodes are dependent upon their respective junction voltages:
LATERAL PNP BJTs
In some bipolar circuits, it is convenient to use PNP
transistors along with the NPN BJTs. In particular,
the digital logic families ASTfL and ALSTfL use
such complimentary devices. However, the fabrication of PNP BJTs along with NPN BJTs is difficult to
accomplish in a compatible manner. One technique
that has been successful for the case of double diffused epitaxial NPNs has resulted in the PNP structure as shown in Figure 3.5. This device is referred
to as a lateral PNP transistor because the current flow
from emitter to collector is lateral (i.e. parallel to the
surface).
Note that the emitter and collector regions of
this PNP use the P-base diffused region of the NPN.
These lateral PNPs have a much reduced f3F primarily because the base width is about an order of magnitude larger than that of the NPN. Additionally, /3r
for the PNP is reduced because of uniform N base
doping as well as reduced emitter carrier collection
at the collector (as compared with the NPN).
The Ebers- Moll BJT Model
FIGURE 3.6
Ebcrs-Moll NPN BJT Model
32
Chapter 3/Bipolar Junction Transistors
where the base-emitter and base-collector reverse
saturation currents li, 5 and Ics (for modern small
BJTs) are typically in the range 10- 16 to 10-n_
For an NPN BJT, the current Io.BE consists primarily of electrons (flowing in a direction opposite
to that of the current). A fraction of these electrons
injected from the emitter into the base region reach
the collector. These electrons contribute to the collector current and are represented by the dependent
current source with magnitude
In Figure 3.6, this current source appears in parallel
with the base-collector diode having current ID.BC·
The other dependent current source in Figure 3.6. of
magnitude
is in parallel with ID,BE and these elements are present for analogous reasons. aF and aR are called the
common base forward and reverse rnrrent amplification
factors, with typical values of a 1 slightly less than 1
and aR between 0.2 and 0.6.
Expressions for the emitter and collector termi-
nal currents are the sum of each region's diode and
dependent source currents and are collectively referred to as the Ebers-Moll equations and are given
by
and
Then, from Kirchhoff's current law, the base current
is simply
Ill = h
le
The Ebe rs- Moll model for the PNP BJT is the
same as that for the NPN with the directions of the
voltage polarities, diodes, diode currents, and dependent current sources reversed, as shown in Figure
3. 7. The Ebers-Moll equations for the PNP BJT are
given by
h = hs(evrni,t,, -
1) - aRlcs(eVcn 1"' 1
-
1)
and
the proof of which is left as an exercise to the reader
in the homework problems.
Reciprocity Theorem
collector
The Ebers-Moll equations show that the BJT terminal
currents are described by two voltage variables,
namely the junction biases V13 E and Vrn, as well as
four device parameters, 11:s, Ics, aF, and aR. The four
parameters are related by the reciprocity theorem
for the ideal BJT:
base
cl-------,
where ls is known as the transport saturation current.
3. 7
+
emitter
FIGURE 3.7
Ebers-Moll PNP BJT Model
BJT MODES OF OPERATION
In section 3.2, the diode is shown to have two modes
of operation, conducting and cutoff, which depend
upon the polarity of the PN junction bias voltage.
Considering the Ebers-Moll model for the NPN BJT
in Figure 3.6, it is observed that there are two PN
junction voltages to consider: the base-emitter PN
junction, and the base-collector PN junction. Considering all possible combinations of forward and reverse biasing of these two PN junctions, there are
3.7
TABLE 3.1
BJT Modes of Operation
Base-Emitter PN
Junction Bias
Base-Collector
PN Junction Bias
Reverse
Forward
Forward
Reverse
Reverse
Reverse
Forward
Forward
Mode of
Operation
Cutoff
Forward active
Saturation
Reverse active
four possible modes of operation for the BJT. These
four modes are tabulated along with their corresponding junction biasing (forward or reverse) in Table 3.1. The remainder of this section discusses these
modes of operation and formulates reduced BJT circuit models for each of the operational modes.
Cutoff Mode
BJT Modes of Operation
range by a factor of about 10h, and are certainly negligible. Figure 3.8 shows the reduced BJT model for
the cutoff mode and consists of open circuits between all three terminals.
Forward Active Mode
In the forward active mode of operation, the baseemitter PN junction is forward biased and the basecollector PN junction is reverse biased. For the reverse biased base-collector PN junction, we again
approximate ID.Be = 0 (and therefore a 1.)D.BC = 0).
Assuming the forward biased base-emitter PN junction also has the piecewise linear characteristic of
Figure 2.3, and a non-zero emitter current exists, the
base-emitter PN junction can be represented by a
voltage source of magnitude
v/lE(FA)
For the cutoff mode of operation, both PN junctions
of the BJT are reverse biased. Assuming the EbersMoll base-emitter and base-collector diodes DBE and
Dile adhere to the piecewise linear characteristic of
Figure 2.3, both ID.BE and ID.Be are zero. The dependent current sources ar-ID.BE and a RID.BC are also zero
as a result. Terminal currents in the cutoff mode are
therefore given simply by the expressions
lr(OFF) = 0
and
Ic(OFF)
33
= o.7 v
for silicon diodes. The collector current for the forward active mode of operation reduces to
lc(FA)
=
arl[
Substituting IE = I8 + le and solving for le gives the
more common expression
where the common-emitter current amplification factor
/3, is related to ll'r as follows
= 0
The actual currents are in the nanoamp range, which
is less than the current magnitudes in the active
Figure 3.9 shows the reduced BJT model for the forward active mode of operation.
Saturation Mode
I.== 0
~
base
o ·
For the saturation mode of operation, both the baseemitter and base-collector PN junctions are forward
biased. Also, large collector, base, and emitter currents may be present. The base-emitter voltage for
this magnitude of current is larger than V8 E(FA) =
0. 7 V since the currents are larger. Hence, the baseemitter PN junction is represented by a voltage
source of larger magnitude, given by
V8 r(SAT) = 0.8 V
FIGURE 3.8 Reduced NPN BJT Model for the Cutoff
Mode of Operation
Due to lighter doping the base-collector voltage will
typically not exceed the forward voltage of
VBc(SAT) = 0.6 V
34
Chapter 3/Bipolar Junction Transistors
ool1'cto,
I!~
<XplB = P.Je
le
---11..►
base o---------
,+
J..I'_
emitter
VBB(FA) = 0.7 V
l
I"
'
FIGURE 3.9 Reduced NPN BJT Model for the Forward
Active Mode of Operation
Reverse Active Mode
The reverse active mode of operation for the BJT is
defined to occur when the base-emitter PN junction
is reverse biased and the base-collector PN junction
is forward biased. The reduced BJT model shown in
Figure 3.11 is obtained in an analogous manner as
the forward active case. Note that the positive currents flow out of the collector and into the emitter. le
and IE are specified as negative in comparison with
their standard current directions. Expressions for this
rnode of operation are given by
ViidRA) = 0.7 V
h(RA) = D'1)c = -{3Rlil < 0
where
Hence, the voltage between the collector and emitter
for the saturation mode is therefore
VcdSAT) = 0.2 V
A saturation parameter u is used to indicate the relationship between le and IB and is defined
leu=f3Flil
where er :S 1.
Note that a = 1 denotes forward active operation and/or edge of saturation operation. Figure 3.10
shows the nwdel for a BJT in the saturation mode of
operation. Note that all terminal voltages are known
relative to one another when the BJT is operating in
saturation.
collwm
base
r!~
As seen in the previous chapter, a BJT is not a symmetric device and use of the collector as an emitter
and emitter as collector will exhibit poor amplification performance. Thus, f3R << f3F• Since amplification of currents is generally not of concern in digital
circuits, the reverse active mode of operation is occasionally utilized.
Family of Curves
Figure 3.12 shows a family of Ic versus Vcrc characteristics for changes in I8 of amount ~ as predicted
by the Ebers-Moll model. For equal increments in 18 ,
the curves in the active regions are approximately
ooll~tm
I!
Vec(RA) = 0.7 V
V0 c(SAT) = 0.6 V
.
~<0
+
+
base,,--_ _ _____,
I!
+
t Ui.lc = PRIB
V0 s(SAT) = 0.8 V
,nritttt
I,
FIGURE 3.10 Reduced NPN BJT Model for the
Saturated Mode of Operation
<mitte,
~!I,
<O
FIGURE 3.11 Reduced NPN BJT Model for the
Reverse Active Mode of Operation
3.8
The Gummel-Poon BJT Model
Is =4A
forward
active
\
l
35
r.
increasing
cutoff
IIs I
increasing
j
FIGURE 3.12
-A -_
-_
-_
-_,
,
IsIs=
=-2A
_______-_
Ia =-3A
Ia=-4A
Ia =-SA
Ia=
-6A
----...1.li~-----"I
------""'-----,
-_
-_
-_
-_
-,,,,
_____-_
Family of Ic versus VcE Characteristics with Ill as a Parameter
evenly spaced, although the curves in the reverse active region are much closer together than those in
the forward active region. This indicates that the
Ebers-Moll model predicts that f3F and f3R are independent of the terminal current magnitudes. As will
be shown in the following section, this is not entirely
true.
THE GUMMEL-POON
BJT MODEL
3.8
The Ebers-Moll model discussed in the previous two
sections made no accounting of second order effects.
The Gummel-Poon BJT model (1970), proposed 16
years after the Ebers- Moll model, considers several
second-order effects by using a charge-control relation
that links junction voltages, collector current, and
charge stored in the base. Some of these second order effects are the following:
• The Early effect (base-width modulation)
which contributes a VcE dependence on Ic
Sah-Noyce-Shockley effect (spacecharge-layer generation at high current levels
and recombination at low current levels)
• The Webster effect (conductivity modulation
in the base)
• The Kirk effect (base width widening)
• Emitter crowding
• The
The second order effects of the Gummel-Poon
model that are discussed in this section are those
included in the SPICE BJT model (the Early, SahNoyce-Shockley, and Kirk effects).
The Early Effect
(Base-Width Modulation)
The family of le versus VcE curves obtained from the
Ebers-Moll model, shown in Figure 3.12, exhibit no
dependence of Ic on VCE· However, a dependence of
le on VcE is observed due to the Early effect and is
demonstrated in Figure 3.13. The slopes of the Ic
versus VcE curves are seen to increase as I8 increases.
Note that when the linear portion of the curves are
36
Chapter 3/Bipolar Junction Transistors
extrapolated to the negative Vn: axis, they intersect
at a common voltage -VA· VA is referred to as the
Early voltage. The Early effect is also present in the
reverse active mode. The simplest form of equations
exhibiting the forward Early effect are
Ic
=
ls(evH,11>., - evHci<f,.,)( 1
Is
_.:._ (e\/acl<t,., -
1)
/31,
The Kirk Effect (Base Width Widening)
The le dependence on Vn given above is somewhat
idealized. \A/hen the minority carrier concentration
across the base-collector junction increases, the electron concentration becomes comparable to the doping density of the collector. This has the effect of widening the base region and reducing the injected
minority carriers that reach the collector and, hence,
/3 1 is reduced.
J
and
O"IAT r11lr'-ro"l"lf
.iU'IJWW
J
oirrol nn.T'l.lo-1-~lla ....
'--'11..&...li.Jl'l.,JI.JlL Jl.,j'i..,W1il..,.I.
,JL..,l'i..,l'.1.1(....L.1.U.I..I.
J
'1111:Trt.lr't
.L.JUJ\J.1.
Recombination
In section 3.2 it was shown that SPICE uses a modified Shockley diode equation with an emission coefficient Nin the denominator of the exponent given
bv
where
These equations reduce to the Ebers-Moll equations
in the limit as the Early voltage approaches infinity
(see problem 3.15).
Ifi
=
L;(ev"iN<1,., - 1)
For a BJT, depletion layer recombination increases
the base current and therefore decreases the current
VA= forward Early voltage
l
FIGURE 3.13
VCE Dependence on Ic due to the Early Effect
IB
increasing
3.9
collector
gain. This is modelled by varying emission coefficients in the base-emitter and base-collector diode
currents of the Ebers-Moll model.
0
3. 9 SPICE BJT MODEL
This section introduces the SPICE BJT model and the
physical significance of each of t/1e SPICE BJT model parameters.
Figure 3.14 shows the modified Gummel-Poon
model used in SPICE to represent the large signal
behavior of a BJT. As can be seen, this model contains junction capacitances, including that for the
collector-substrate junction, and parasitic resistances
for the collector, base, and emitter terminals.
37
SPICE BJT Model
fc~-t¼
~~~I
6
substrate
RB
base o---.1\/1./\r------
SPICE BJT DC Characteristic
The nonlinear current sources exhibit the GummelPoon DC characteristics presented in section 3. 7 with
the inclusion of emission coefficients for both junctions. The expressions are given by
Ics = IS(ev",INF<l>T - eVeclNR<Pr)( 1
~)
VAF
emitter
_IS
_ (ev",-INR,/,r _ 1)
BR
FIGURE 3.14
Poon model)
and
duce the SPICE model to the simpler Ebers-Moll
model.
where
IBr = Ill + Irn
The parameters used to calculate the DC operation
of a BJT are tabulated in Tables 3.2, 3.3, and 3.4. Note
that the parameters corresponding to the GummelPoon model in Table 3.3 have default values that re-
TABLE 3.2
SPICE BJT Model (Modified Gummel-
SPICE BJT Transient Response
The BJT parameters that contribute to the transient
response calculated by SPICE are tabulated in Table
3.5. The three capacitances of Figure 3.14 have the
SPICE DC BJT Model Parameters Corresponding to the Ebers-Moll Model
Symbol
Name
Parameter
Units
Default
Typical
Is
IS
BF
NF
BR
NR
Junction saturation current
Ideal maximum forward beta
Forward current emission coefficient
Ideal maximum reverse beta
Reverse current emission coefficient
A
lE-16
100
1.0
1
1
lE-16
100
1
0.1
1
/31
f3R
38
Chapter 3/Bipolar Jun cti on Transisto rs
TABLE 3.3
SPICE DC BJT Model Parameters Corresponding to the Gummel-Poon Model
Symbol
Name
Parame ter
VA
VAF
IKF
ISE
NE
VAR
IKR
ISC
NC
Forward Earl y voltage
Co rn e r for forward beta high cu rrent roll-off
Base-emitter leakage saturation current
Base -emitter leakage em ission coefficient
Reverse Early voltage
Co rner for reverse beta high current roll-off
Base-collector leakage saturation current
Base-coll ector lea kage emission coefficie nt
TABLE 3.4
Name
RB
RB
RBM
IRB
RE
RC
Re
Parameter
Zero-bias base resistance
Minimum base resistance a t hi gh currents
Curre nt a t w hi ch RB fa lls hal fway to RB M
Emitter resista nce
Collector resistance
TABLE 3.5
SPICE Transient BJT Model Parameters
Symbol
Name
C11rn
<pBE
mE
TF
CJE
VJE
MJE
TF
XTF
VTF
ITF
Clleo
</>ne
me
'TR
Cesa
</J es
m,
Default
V
C/J
A
A
C/J
Typical
V
00
A
00
A
0
2
200
lOE-3
lE-13
2
200
lE-3
lE-13
1.5
Units
Default
Typical
0
100
10
0.1
1
10
0
1.5
SPICE DC BJT Parasitic Resistance Model Parameters
Symbol
RE
Units
PTF
CJC
VJC
MJC
XCJC
TR
CJS
VJS
MJS
FC
Param eter
fl,
n
RB
A
00
n
n
0
0
Units
Zero-bias base-emitter depl e tion capacitance
Base-e mitter built-in potential
Base-em itte r juncti on grading coefficie nt
Idea l forward transit tim e
TF bias depend ence coefficient
TF dependency on V11 e
TF dependency on le
Excess phase a t frequency l/(27T X TF) Hz
Zero-bias base-collector deple ti on capaci tan ce
Base-collecto r built-in potential
Base -collector junction grad ing coefficie nt
Fracti o n of CHc co nnected inte rn al to R11
Idea l reverse trans it
Collec tor-substrate zero-bias deple ti o n capacitance
Collec tor-substrate built-in po tenti al
Collecto r-substrate junction grading coefficient
Forward-bias de ple tion capacitance coeffici ent
F
V
s
V
A
deg
F
V
s
F
V
Default
Typical
0
0.75
0.33
0
0
2PF
0.85
0.33
OJNS
00
0
0
0
0.75
0.33
1
0
0
0.75
0
0.5
30
2PF
0.8
0.5
lONS
2PF
0.8
0.5
and
va lu es
V
- -llC
-
VJC )
MJC
As with the diod e, th ese capaci tances can also be
modelled as charge storage elem ents:
3.10
T F x IS (cv" 11 NE,t,1
(\/HI (
+ CJ E
Jo
-
1)
V )-MJE
1 - VJ E
Integrated Circuit Resistors
39
that are used in integrated circuits along with an
ideal resistor.
d\l
and
A model parameter F C similar to that for the diode
is also available for modeling the forward biased
junction capacitances of the SPICE BJT.
3.10 INTEGRATED CIRCUIT
RESISTORS
Although resistors in digital and analog ICs have
been replaced in many instances with transistors,
TTL and ECL families continue to use these passive
components. Figure 3.15 displays several IC resistors
Ideal Rectangular Resistor
Figure 3.15a shows an ideal rectangular resistor with
the resistance expression in terms of constant resistivity p, length L and cross-sectional area A This resistance is included for comparison with the IC resistors. The ideal resistance Rab is defined between
planes a and b as follows:
R,,1, =
L
PA
The integrated circuit resistors shown in the
other portions of Figure 3.15 are compatible with the
double diffused epitaxial BJT and use different layers
of this device for the resistor structure.
Diffused Base Resistor
Figure 3.15b shows a resistor that uses the base diffusion/implant region for the resistor. The sheet re-
p
N
P substrate
(a)
(b)
N+
p
N+
p
N
N
P substrate
P substrate
(c)
(d)
FIGURE 3.15 Integrated Circuit Resistor Crosssections: (a) Ideal rectangular resistor, (b) Diffused base
resistor, (c) Diffused emitter resistor, (d) Pinch resistor
40
Chapter 3/Bipolar Junction Transistors
sistivity PsB of this region is comparatively large and
is useful for larger IC resistors. Typically p 513 = 200
!!/square. The resistance expression for this structure
is
Diffused Emitter Resistor
Figure 3.15c uses the emitter N+ region for the resistor and is used for small valued resistors. Typically,
PsE = 2 fl/square. The resistance expression is
Pinch Resistor
Figure 3.15d shows a pinch resistor which has the
largest value of resistance for a fixed length/width
ratio of any of the IC resistors. This is because the
cross section of the resistor has been reduced by the
N+ diffusion. The reduced cross-section has the effect of increasing the sheet resistivity and hence the
resistor value. For the reduced sheet resistivity PsB,
the resistance is
CHAPTER 3 PROBLEMS
3.1
Outline the basic processing steps for the fabrication
of a double diffused NPN BJT.
3.8
Derive equations for Vcr(SAT) and VmJSAT) from
the Ebers-Moll equations.
3.2
Repeat Problem 3.1 for the NPN BJT that uses oxide
isolation.
3.9
3.3
Draw the two-dimensional cross-section of a double
diffused NPN BJT and label the different regions. Be
sure to indicate the relative doping densities, i.e. N·,
N, N+, p-, P, or p+_
From the equations of Problem 3.8, calculate values
for V81 (SAT) and Vn(SAT) for the circuit of Figure
P3.9. Use aF = 0.98,aR = 0.5, I1.:s = 10- 1" A, Ics =
2 X 10- 10 A. Choose initial values of V8 F = 0.7 V
and Vn = 0.2 V and iterate.
3.10
3.4
Repeat Problem 3.3 for the oxide isolatd NPN BJT.
For the forward active mode, use the Ebers-Moll
equations to show that
3.5
Show that the multi-emitter NPN BJT of Figure P3.5
acts as a single-emitter BJT. (Hint: What PN junctions are reverse-biased?)
3.6
What part of an NPN BJT is modified to create a
Schottky-clamped BJT?
3.7
Repeat Problem 3.3 for the lateral PNP BJT.
and
Va:= 5V
f
10 Jill
FIGURE P3.5
FIGURE P3.9
l
Chapter 3 Problems
3.11
Calculate the BJT capacitance values using the typical parameters from the SPICE tables. Use VBE =
0.7 V, Vrn = 5 V, and C1" = 10 pF (for the emitter
and collector junctions).
3.12
Repeat Problem 3.11 for a BJT in saturation.
3.13
List the three types of integrated circuit resistors discussed in this chapter in order of increasing resistance per square.
3.14
For the circuit shown in Figure P3.14, calculate the
values of IRE ( = - IF), Vm and VER· Let a" = 0.05
and Vile= 0.7 V. What is the operating state of the
transistor?
3.15
Show that the Gummel-Poon equations reduce to
the Ebers-Moll equations as the Early voltage approached infinity.
FIGURE P3.14
41
4
INTRODUCTION
TO BIPOLAR
DIGITAL
CIRCUITS
This chapter is a preview of bipolar digital circuit
analysis methods with accompanying calculations
that are very beneficial in later chapters. As will be
seen, the analysis of bipolar digital circuits follows an
inherent pattern. Since each transistor, diode, and
resistor in the circuit is intended for a specific purpose and/or operates in a specific mode, knowing the
state of each transistor and diode allows a quick and
simple method of circuit solution.
In this chapter basic types of logic circuits are
presented in order to convey digital circuit principles.
The basic circuits to be considered here are the diode-resistor logic circuits and the BJT inverter. The
BJT inverter provides simple logic inversion using a
common-emitter configuration. These basic logic circuits lead into transistor-transistor logic (TTL) circuits. To complete this chapter, a general block
diagran1 for TTL logic families is presented along
with basic diode and BJT operating configurations.
This material is extremely useful in laler chapters.
of operation are shown in Figures 4.la, b, and c. For
the cutoff mode of operation, which occurs for VBE
< VBdFA) = 0. 7 V, all terminal currents are zero. For
the forward active and saturation modes of operation, relationships between each of the BJT terminal
currents and some of the terminal voltage differences
are inherent. The reverse active mode of BJT operation was also presented in the previous chapter. The
terminal current and voltage relationships for this
mode are shown in Figure 4.2.
If the state of a BJT in a circuit is known, the
known voltage differences can be used to determine
the node voltages in the circuit and the branch currents in the circuit. The following example demonstrates this method of determination for the saturation mode.
Example 4.1
BJT Saturation
Determine the base and collector currents and u for
the saturated BJT in Figure 4.3. Let f3F = 65.
Solution Since the BJT in Figure 4.3 is in saturation
and the emitter is at ground, V8 = V13 E(SAT) = 0.8 V
and Vc = V0,(SAT) = 0.2 V. The base and collector
currents are now easily determined to be
ANALYSIS OF BJT CIRCUITS
WITH KNOWN STATES
4.1
The four modes of BJT operation were presented in
the previous chapter and are
1.
cutoff mode
2.
forward active mode
3.
saturation mode
4.
reverse active mode
(5)
(0.8) _
µA
(Sk)
- 840
and
Each of these modes have characteristic terminal
current and voltage relationships. The relationships
for the cutoff, forward active, and saturation modes
(5) - (0. 2) = 7.5 mA
(640)
42
4.1
J\nalvsis of BJT Circuits with Known States
43
(b)
(a)
- I lc(SAT) = ap,J.
v.c(SAT)
=0.6V
l
+
YciSAT)
=0.2 V
(0 <a< 1)
Q(SAT)
V•.(SAT)
=0.8 V
FIGURE 4.1
(SAT)
BJT Terminal Current and Voltage Relationships: (a) Cutoff (OFF), (b) Forward active (FA), (c) Saturation
The saturation parameter is then
(7.Slll)
(65)(840µ,) =
0 137
·
This example demonstrates techniques used to analyze digital circuits. The state of the BJT is known
and the voltages for the solution are therefore also
known. The calculations then necessary to determine
the currents only involve applying Ohm's law. More
complex circuits can be analyzed just as easily.
Analysis of circuits containing B]Ts in the reverse active mode of operation can also be analyzed in a similar manner. As will be seen in the following examples (and in the chapters on bipolar digital circuits),
when the operating states of the diodes and transistors in a digital circuit are known, this is sufficient
information for complete circuit analysis.
Yee= 5V
0
I
J
+-I,(RA)" M
1.
-++
v.c(RA)
=0.7V
R.
5 k.Q
6400
Re
j
Q(RA)
+-le= I.+ (-I,,)
Yca(SAT)
Q(SAT)
~+
I.
V•.(SAT)
-:-
FIGURE 4.2 Reverse Active (RA) BJT Terminal Current
and Voltage Relationship
FIGURE 4.3 BJT Digital Sub-circuit with Known State
of Operation for Example 4.1
44
Chapter 4/lntroduction to Bipolar Digital Circuits
Example 4.2 BJT Analysis with Known States
Figure 4.4 shows a portion of a digital circuit where
the state of each transistor is known. Solve for the
voltages at the base and emitter of each BJT.
Solution The state of each BJT is given and thus
voltages between transistor terminals are known.
The emitter of the output BJT Q0 is at ground and
thus
VE,O = 0
With Q 0 forward active, V8 F.,o = 0.7 V giving
VB,o
=
V8 E,o(FA)
=
0.7 V
Hence, VE,s = V 8 , 0 and since Q5 is also forward active, VB,s is the sum of two forward-active B-E voltages
Vs,s = VBE,o(FA) + VsE,s(FA)
= 2V8 E(FA) = 2(0.7) = 1.4 V
With the input transistor Q1 saturated, VcE,I is known
and thus
VE,1 = VeE,o(FA) + VsE,s(FA) - VcE,J(SAT)
= 2(0.7) - (0.2) = 1.2 V
Just as the operating state of BJTs provides a tool
for analysis of digital circuits, a similar situation is
found with PN junction semiconductor diodes. The
next example demonstrates the procedure.
Example 4.3 Diode Analysis
with Known States
Determine the current I through the branch in Figure
4.5. Also, find the voltage at the base of the transistor
Q. Assume the BJT base current is negligible.
Solution Using KVL for the output branch gives
GND - IR, - IR 2
V01 (0N)
-
- V02 (0N) - lR3 = -Vff
Solving for I, we have
I= VEE - 2V0 (0N)
R1 + R2 + R3
(5.2) - 2(0.7)
= 3.04 mA
(200) + (750) + (300)
The state of Q is not given but is not needed since
the voltage at its base can be obtained without
knowing the state of Q, where
Finally,
Va,1 = Vc,1 + V 8 c,1(SAT)
= (1.2) + (0.8) = 2.0 V
Notice that in this analysis none of the BJT terminal
currents were of concern.
Q(SAT)
~(FA)
-::-
FIGURE 4.4 BJT Digital Sub-circuit with Known States
of Operation for Example 4.2
-V.,,,_ = -5.2 V
FIGURE 4.5 BJT/Diode Digital Sub-circuit with Known
States of Operation for Example 4.3
4.2
Vil= CND - IR 1
= (0) - (3.04111)(200) = -608 111V
The previous examples demonstrate the use of
BJT and diode terminal voltage differences for analysis of digital circuits. At the end of this chapter there
are many probleff1S of this type, none of which
1f
BJT Inverter
45
should take more than a minute to solve. The reader
is encouraged to solve these problems and become
familiar with this style of circuit solution.
4.2
BJT INVERTER
Figure 4.6a displays the first active gate to be considered. The circuit consists of a BJT with base and collector resistors and one voltage source Vcc• This simple arrangement is a logic inverter.
Tips, Tricks, and Gimmicks
BJT Analysis with
Known Operating States
To summarize this section, knowing the state
of a BJT or diode in a digital circuit allows certain voltage and current calculations. Important operating voltages and currents are listed
as follows:
Diode conducting: VD(ON) = 0.7 V
Fo1ward-active: VBE(FA) = 0.7 V and Ic =
f3FIB
Saturation: V13 E(SAT) = 0.8 V and VcE(SAT)
= 0.2 V
Reverse-active: V8 c:(RA) = 0.7 V and IE =
-/3Rifl
As will be seen in the digital circuits employing
metal-semiconductor
(usually
Al-NSi)
Schottky barrier MN diodes and Schottkyclamped NPN BJTs the following additional expressions are of great importance:
Schottky diode (N-Si) conducting: V58 D(ON)
= 0.3 V
Schottky clamped BJT Jonuard-active
(Schottky-barrier diode not conducting):
VBE(ON)
= 0.7 V
Schottky-clamped BJT on hard: VBF.(HARD)
= 0.8 V, V8 c(ON) = VsrdON) = 0.3 V,
and VcE(HARD) = 0.5 V
Note that operation of Schottky barrier MN diodes is identical to that of PN semiconductor
diodes, except that the diode ON voltage is reduced. Furthermore, a Schottky-clamped BJT is
simply a BJT with a Schottky barrier diode connected between the base and collector. This diode prevents the BJT from operating in the saturation region.
Output High Voltage= VoH
For VBE < V13 E(FA), the BJT is cutoff and Ic = IRc =
0. With no voltage drop across Re, the output voltage
is given by
Input Low Voltage= V1L
When V8 E reaches VBE(FA), the BJT is at the edge of
conduction, where the cutoff and forward active
regions meet. As VIN passes V8 E(FA), the voltage
VIN - V8 E(FA) across R8 corresponds to a base current I8 = IRB and collector current Ic = f3FIB. The
output is now diminished by IcRc. Hence,
VIL= VBr(FA)
Output Low Voltage = VoL
Increasing VIN to the point of saturating the BJT gives
Vo1
=
Vcr(SAT)
which is the minimum collector-emitter voltage.
Input High Voltage
= Vrn
Vu-1 is the input voltage at the edge of saturation
which is also defined to be at the edge of the active
region. With the collector-emitter voltage at
VcE(SAT), the collector current is given by
_ Vee - VcE(SAT)
I cRc
At the edge of saturation, u- = 1 and the base and
collector currents are still related by Ic = f3Fl 8 . Thus,
IB(EOS)
= Ic = Vee - VcE(SAT)
f3r
/3rRc
46
Chapter 4/lntroduction to Bipolar Digital Circuits
edge of conduction
/
Your
edge of saturation
VoL = Vce(SAT)
I
Q(SAT)
t
'------Mf-------------vIN
,vm
(a)
(V)
VIL= V BE(FA)
(b)
FIGURE 4.6
BJT Inverter: (a) Circuit, (b) Voltage transfer characteristic
With V8 E = V8 E(SAT), the input high voltage is
Vu.1
=
V8 E(SAT)
+
Thus, by definition from the previous chapter
I 8 (EOS)R 8
VNM/-1
= V (SAT) + Vee - VcE(SAT) R
f3rRc
BE
=
VOi-{ -
V111
= (5) - (1.6) = 3.4 V
and
B
The voltage transfer characteristic for this basic
BJT inverter is displayed in Figure 4.66. The logical
NOT function is clearly exhibited outside the narrow
amplifier region.
Vivi&
= Vn - VoL = (0.7) - (0.2) = 0.5 V
As we shall see, the low noise margin of the simple
BJT inverter is unacceptably small. However, the basic RTL inverter plays an integral part in the structure
of more complex bipolar logic circuits, as will be seen
in future chapters.
Example 4.4 BJT Inverter Voltage
Transfer Characteristic
For the BJT inverter of Figure 4.6, determine the high
and low noise margins for Vcc = 5 V, R 8 = 10 kfl,
Re = 1 kfl, and f3F = 60.
Solution Substituting these values and the known
BJT voltages directly into the expressions derived in
this section yields
V0 u = 5 V
ViL =
TTL SUPER-CIRCUITRY
To provide a preview to succeeding chapters, this
section considers all TTL logic families to have circuitry designed with the same considerations shown
in Figure 4.7. This is not at all surprising, since new
BJT logic families have been mere improvements of
their basic sub-circuits of TTL circuitry.
0.7 V
Input Section
VoL = 0.2 V
and
Vu 1 = (0.8)
4.3
(5) - (0.2)
+ (60)(lk)
(10k) = 1.6 V
The input section consists of an ANDing of all inputs.
The parallel diode configuration contained within
the diode AND gate of section 2.5 is an example of
this type input. However, a multi-emitter BJT with
4.3
I
--
N0
VINA
..
VINB
.
Diode or
Multi-emitter
AND gate
VAND
Drive
Splitter
~
I
?
I
Yies
I
FIGURE 4.7
TTL Super-Circuitry
Output
High
Pull-up
Driver
VNAND
-
Output
Low
Pull-down
Driver
TTL Family Super-circuitry Block Diagram
the different emitters being the inputs can also serve
this purpose as we shall see.
Drive Splitter
Depending on the result of the input ANDing, the
drive splitter turns on one of the two output sections.
A typical drive splitter is the BJT inverter of the last
section. If the output of the AND gate is logic low,
the input voltage to the drive splitter is also low. A
BJT inverter used for the drive splitter would then be
cutoff. This would cutoff the output-low pull-down
and activate the output-high pull-up portion of the
output. For a logic high output from the AND gate,
the opposite output results. Note that the two output
drivers are never on simultaneously. The drive splitter section also provides additional base driving current to the output-low pull-down driver.
From the block diagram, it can be seen that the
TTL super-circuitry provides the NANO logic function. The input stage ANDs the multiple inputs,
while the drive splitter section provides inversion. If
the circuit has only one input, or if all inputs are
connected together the logic circuit then reduces to
an inverter.
Output-High Pull-Up Driver
As discussed in the previous chapter, as the output
goes low-to-high, current is required to charge the
equivalent input-capacitance of the load gates. The
output-high pull-up section provides sourcing current for this charging. A simple embodiment would
be a voltage driven resistor as in Figure 4.8a. However, an emitter-follower as in Figure 4.8b is an active
solution which provides a higher sourcing current
and hence faster switching time. For even more
sourcing current, a Darlington pair configuration, as
L'.:;::
IACl1Vll
(a)
FIGURE 4.8
47
(b)
Pull-up Current Sources: (a) Passive, (b) Active, (c) Darlington pair active
(c)
VOH
48
Chapter 4/Introduction to Bipolar Digital Circuits
shown in Figure 4.8c, is used. This active pull-up circuit also provides greater fan-out.
Output-Low Pull-Down Driver
The purpose of the output-low pull-down section is
two-fold. A large sinking current must be available
to discharge the capacitive load. In addition, the pulldown circuitry provides larger fan-out by sinking
(non-zero) currents I11, from all the load gates as indicated in Figure 4.9. The current Im is collector
current for a BJT and allows adequate fan-out, as we
shall see.
FIGURE 4.10
Example 4.5
4.4
BJT-diode Voltage Level-shifting for
LEVEL-SHIFTING BJTs
It is often desired to increase the voltage drop across
particular portions of digital circuits. One reason is
to ensure that sub-circuits with complementary objectives are not conducting simultaneously. For example, consider the two output drivers of Figure 4.7.
One is on for the output-low state and the other for
the output-high state. Placement of a voltage levelshifting device between the two drivers provides the
desired isolation.
The conducting diode voltage V1i0N) = 0.7 V
is an ideal element for this purpose. Alternatively,
the base-emitter portion of a BJT can also be used
for level-shifting and has the advantage of providing
additional driving current.
Example 4.5 Level-Shifting
What is the level-shifting voltage VsHiFr of the BJTdiode pair in Figure 4.10? Assume the BJT is forwardactive and the diode is conducting.
Solution The level-shifting voltage of the BJTdiode configuration is obtained by adding the known
voltages as follows:
Vs111FT = VBE,o(FA) + Vo,L(ON)
= (0.7) + (0.7) = 1.4 V
4.5 DISCHARGE PATHS AND BASE
DRIVING CIRCUITRY
As mentioned in section 4.1, in order to turn off a
saturated BJT, all of the stored charge in the base
region must be removed. A path must therefore be
available for base discharge. If the circuitry connected to the base of a BJT is non-conducting, for
instance a reverse biased diode or another BJT in cutoff, a saturated BJT will not be able to discharge the
stored charge from its base. Figure 4.1 la displays a
circuit with an additional resistor R0 that provides
passive charge removal. The current magnitude is
the base voltage of Q0 divided by the resistor, or
IJ<D
Output
Low
Pull-down
Driver
FIGURE 4.9
Fan-out Current Sinking
_
-
Viio
Ro
Figure 4.116 shows an active configuration for
stored charge removal. This circuit provides a much
faster discharge than R0 in Figure 4.lla.
Conversely, the turn-on time of a BJT is dependent on the time required to charge the base of the
BJT. Active base driving current is often supplied to
BJTs that require a brief switching time. An emitter-
4.h
49
Self-Biasing BJTs
-::-
(c)
(b)
(a)
FIGURE 4.11 Stored Charge and Drive Currents: (a) Passive stored charge removal, (b) Active stored charge removal,
(c) Active base driving
VBE(FA) = 0.7 V and Ic = f3FIB, a desired value of
VCE must be selected before values for the resistors
can be chosen. The base and collector currents would
then respectively be
follower BJT configuration usually provides this driving current. Figure 4.11c shows an emitter-follower
Q 5 that provides base driving current to Q 0 .
4.6
SELF-BIASING BJTs
If the resistors in the self-biasing BJT configuration
of Figure 4.12a are chosen properly, the BJT will operate in the forward-active region. The usual application of the self-biased BJT is as a current sink. Since
and
:!I
I
V cr:
RB
r_
1~7
Re
RB
t
V
I
Re
RB
Q
f
L
Re
_
Q
-::-
(a)
FIGURE 4.12
Various Self-biasing BJT Configurations:
(a) Self-biasing BJT, (6) Current sinking self-biasing BJT,
(b)
(c)
(c) Self-biasing BJT operating from a neighboring node
voltage
50
Chapter 4/Introduction to Bipolar Digital Cirn1its
Solving for R8 /Re gives
RH
-
Re
Pcc=lccVcc
Vee - VHE(FA)
= /31 - - - - - Vee - VcE
This shows that the ratio of the resistors is approximately f3F, since V cE = VHE· Note that the base resistor should be the larger resistance, since the base
current is smaller than the collector current. While
the actual magnitude of each resistor determines
how much current is conducted, the ratio Rri/Rc determines how hard the BJT is driven, and thus the
n-1agnitude of stored charge in the base.
Self-Biasing BJT
Determine the ratio Rfi/Re for a self-biasing BJT with
Example 4.6
VcE = 0.6 V. Let Vee= 4 V and f3F = 60.
Solution
Direct substitution into the derived expression yields
;; =
(60)
~:~ =~~::~ = 58.2
The self-biasing BJT is exploited in BJT digital
circuits for the purposes of sinking, current sourcing,
and driving currents. Figure 4.126 shows a configuration in which an incoming current is said to be
sinked. Figure 4.12c shows a configuration where the
operating voltage is determined by a node voltage of
another portion of the circuit.
4.7 POWER DISSIPATION
OF BIPOLAR LOGIC CIRCUITS
The power dissipation of logic circuits is an important
consideration in their design and use. For bipolar
logic circuits that have a single voltage supply (like
the block diagram in Figure 4.13), the power dissipation for a particular gate and operating state is
taken to be the power supplied, given by
Pee
=
FIGURE 4.13
Power Supplied to a Logic Gate
The average power dissipated in a logic circuit
with two output states is defined as the average current supplied by Vcc for the output high and low
logic states multiplied by the magnitude of V cc•
Hence,
Pcc (avg)
Example 4. 7
=
lce(OH)
+ Icc(OL)
2
Vee
A veruge Power Dissipation
Figure 4.15 shows the top portion of a bipolar logic
gate. The resistor currents for the output high state
are IR 8 (OH) = 1.55 mA, 11dOH) · = 24.7 µ,A,
R) ii• .J ii"
I
Q
Ro
[___
Q,
Your
IccVcc
where Ice is the current supplied by Vcc and is obtained by summing all the currents leaving the supply voltage source. For the bipolar logic gate of Figure
4.14, the current supplied by Vee is
Ice
=
I1w
+
I1,c
+
!Rel'
FIGURE 4.14
Current Supplied to a Bipolar Logic Gate
Chapter 4 Problems
51
Solution To find the average power dissipated, the
total current for each output logic state is obtained
by summing the various currents. Hence, for the output high logic state we have
Icc(OH)
= IR 8 (OH) + IRc(OH) + IRco(OH)
= (1.55m) + (24.7µ,) + (1.21m)
= 2.78 mA
For the output low logic state
Icc(OL)
FIGURE 4.15 Output High and Low Currents
Through the Top Portion of a Bipolar Logic Gate for
Example 4.7
= JRll(OL) + IRc(OL) + Im>(OL)
= (1.14111) + (4.48m) + (104µ,)
= 5.72 mA
The average power dissipated is then by definition
I,Kr(OH) = 1.21 mA, and for the output low state
I,w(OL) = 1.14 mA, IRc(OL) = 4.48 mA, and
IRcr(OL) = 104 µA What is the average power dissipated in this gate?
Pee (avg) =
(2. 78111) + (5. 72m) ( )
2
5
= 21.3 mW
CHAPTER 4 PROBLEMS
4.1
Determine I8 , le, and VCE for the circuit in Figure
P4.1 using f3F = 100 and the following values:
(a) V,m = 6.7 V, Vee= 10 V, Rn = 60 kD, and Re
= 1 kD
(b) Vs 8 = 5.7 V, Vee = 30 V, R8 = 100 kD, and
Re= 3 kD
(c) V88 = 2 V, Vee = 5 V, Rn = 4 kD, and Re =
2 kD
(d) V,m = 3 V, Vcc = 5 V, R8 = 10 kD, and Re =
1 k.!1
4.2
4.3
Determine Is, le, and VCE for the circuit in Figure
P4.1 using Rs= 10 kD, Re= 1 kD, Vee= 5 V, and
f3F = 40 for each of the following values of VRB· State
the mode of operation for the BJT in each case.
(a) VBB = 0.2 V
(b) V 1m = 1.7 V
(c) \!Bil = 5 V
Determine u for the circuit of Figure P4.1 for operation in saturation with V,m = Vcc = 5 V, RB =
Re= 5 kD, and f3F = 100. (Remember, Vc:E = 0.2 V
in the saturation mode and Ic is the collector current
at the edge of saturation.)
4.4
For each of the circuits in Figure P4.4 determine the
indicated quantity. Use V0 (ON) = 0.7 V.
4.5
For each of the circuits in Figure P4.5 determine the
power dissipated. Use V0 (ON) = 0.7 V, VBE(FA) =
0.7 V, and Ver:(SAT) = 0.2 V. Neglect base currents.
FIGURE P4.1
=
4.6
Find le for the circuits of Figure P4.6. Assume IE
le (i.e. f3F >> 1) where appropriate.
4.7
For each of the circuits in Figure P4. 7 determine the
indicated quantity.
4.8
For the BJT logic inverter of Figure P4.8, calculate
the output voltage for the input voltages of O and
5 V. Let f3F = 100, VnE(FA) = V8 E(SAT) = 0.7 V, and
VcE(SAT) = 0.2 V. Additionally, calculate the minimum input voltage that causes the BJT to operate in
saturation. Finally, sketch the VTC and determine
the noise margins.
4.9
Repeat Problem 4.8 for R8 reduced to 1 kD.
4.10
Repeat Problem 4.8 for Re reduced to 1 kD.
52
Chapter 4/Introduction to Bipolar Digital Circuits
Vee= 5V
Vee= 5V
0
I
Q,(SAT)
D,(ON)
Qi(SAT)
D,(ON)
y_
D.(ON)
R,
-J,.
t
V
~~Q,(FA)
10 ill
I
V., ~?
6
-VPJJ=-5 V
(a)
-VPJJ = -5.2 V
(b)
(c)
(d)
FIGURE P4.4
Vee= 5V
Vee;:_ 5V
y
R,
731
n
R,
R,
~ 731 fl
I
R,
soon Re
I
".¥-
D,(ON)
R,
R,
R,
2550
1.32 ill
i¾
D,(ON)
R,
R,
~ 1 ill
I
2550
D,(ON)
D,(ON)
D,(ON)
R,
D,(ON)
~
1.32 ldl
R,
20ill Rs
I
f
3.5 ill
-::::::-:-
-VPJJ = -5.2 V
(a)
(b)
0
-VPJJ=-5.2V
(c)
-Vl!l!=-5.2 V
(d)
FIGUREP4.5
4.11
Analyze the circuit of Figure P4.11 to determine the
operating state of the BJT, I, and Ic for the following
values of V 1N:
(a) 0,
(b) 0.2 V,
(c) 0.5 V,
(d) 2 V
Let f3r = 100, R1 = 2 kn, and R2 = 3 kn
4.12
The BJT inverter circuit shown in P4.12 has a resistor
R0 connected to -Vss to provide passive pull-down
of the BJT. Determine Is for V1N = 5 V. Is the transistor saturated? Determine V,L and V111 . Let f3F =
100, V8 dFA) = 0.7 V, V8 E(SAT) = 0.75 V, and
VcE(SAT) = 0.1 V.
4.13
For a BJT inverter similar to the one in Figure P4.8,
determine the values of Rs and Re such that the BJT
Chapter 4 Problems
Vee= 5V
Vee= 5V
Q.(FA)
(b)
(a)
FIGURE P4.6
Q,.(SAT)
(b)
(a)
Your=?
(c)
FIGURE P4.7
Your
(d)
53
54
Chapter 4/Introduction to Bipolar Digital Circuits
operates at the edge of saturation for V111 = 2 V. Let
lc(SAT) = 10 mA, V 8 F(FA) = 0.7 V, V0 ,(SAT) =
0.2 V, f3F = 100, and Vee = 5 V.
Vee= 5 V
Re
i
4.14
For the BJT inverter circuit of Figure P4.8, determine
and sketch the VTC CVour versus V,:,il. Let Vcc =
6 V, R 11 = 20 ki1, Re = 2 kD, f3F = 100, V1lE(FA) =
Vm(SAT) = 0.7 V, and V0 ,(SAT) = 0.2 V. Also, determine the noise margins.
4.15
Determine the maximum fan-out of the BJT inverter
shown in Figure P4.8. Assume the output gates are
identical as shown in Figure P4.15. Let Vee = 5 V,
Rn = 10 kf!, and Re = 1 k!1. For the BJT, let f3F =
50, V 11 E(FA) = 0.7 V, V111 ,(SAT) = 0.8 V, and
Vu(SAT) = 0.2 V.
4 kn
VOUT
FIGURE P4.8
You-r
Q
Q
FIGURE P4.12
FIGURE P4.11
V' cc
V'our
R'8 Q
~ ,
~.
~
____..
--{ }--v_o_u-r_ _---1.
I' Bl
J.
N identical load gates
FIGURE P4.15
Chapter 4 Problems
4.16
55
For the circuit shown in Figure P4.16, V1 and V 2 are
either Oor 5 V. IfVu(SAT) = 0.2 V, what is the fanin of this gate that will maintain the output low voltage less than VBdFA) = 0.7 V?
FIGURE P4.21
Your
y' ' -~----,
Q,
4.22
Y, o--------------
Q,
FIGURE P4.16
4.17
For the top portion of the logic gate shown in Figure
P4.22, Vm(OL) = 2.5 V, VBl(OH) = 0.2 V, Vcs(OL)
= 1 V, and Vcp(OH) = 4.95 V. Vcs is not connected
for the output high state and Vcp is not connected
for the output low state. Calculate the average
power dissipated. Use R8 = 4 kfl, Re = 1.6 kfl, and
Rel'= 120 !l.
For the BJT inverter of Figure P4.8, calculate the
minimum input voltage Vll I required to drive the BJT
into saturation. Let Vee = 10 V, RB = Re = 5 kfl,
/3 1 = 100, Vlll:(FA) = 0.7 V, V1dSAT) = 0.8 V, and
Vc 1 (SAT) = 0.2 V.
4.18
Repeat Problem 4.18 for RR= 2 kfl
4.19
For the BJT inverter of Figure P4.8, calculate the
value of Rt: that provides Vll 1 = 0.8 V. Let Vee =
5 V, Rn= 4.5 kfl, f3F = 100, VB 1(FA) = 0.7V, V1H(FA)
= 0.75 V, and Vc,,(SAT) = 0.15 V.
Ycc=5Y
R,
4.20
For the top portions of the logic gates shown in Figure P4.20a and b, determine the power dissipation.
4.21
For the top portion of a logic gate shown in Figure
P4.21, 11m(OL) = 10 mA, l1rn(OH) = 24 µ.A, IRe(OL)
= 4 mA, !Rc(OH) = 0.6 µ.A, IRCP(OL) = 20 nA, and
!Ru,(OH) = 2.85 mA. Determine the average power
dissipated in this gate.
IRCP
0
Y.,
~t
6
0
Yes
YCP
4.23
Repeat Problem 4.22 for RB and Re doubled in magnitude.
4.24
Draw the block diagram of a TTL circuit and label
the individual blocks. List different circuit arrangements that can be used for each block.
= 5 rnA
1
+
2.3Y _
(a)
I
FIGURE P4.22
4kil
FIGURE P4.20
~1
~
f
1.6 ill
R:
l.OY _'
1
(b)
No connection
5
RESISTORTRANSISTOR
LOGIC [RTL]
modifications that realize AND and OR gates. Improvements in RTL design along with analyses for
determination of maximum fan-out and power dissipation are also presented.
The different BJT families discussed in the following
chapters are presented in essentially chronological
order. About every five years, a new BJT logic subfamily was introduced starting with RTL in 1962.
Subsequent models (DTL, TTL, STIL, ... ) are improvements of previous sub-families with the same
general TfL super-circuitry discussed in section 4.3.
The logic family presented in this chapter is resistor-transistor logic (RTL). As the name implies, circuits of the Resistor-Transistor logic family are constructed from resistors and transistors (BJTs). RTL
was the first logic family to become commercially
available. Inverters (NOT), non-inverters (buffers),
NOR, NAND, OR, and AND gates can all be constructed with RTL logic. In addition, low-, medium-,
and high-power versions of the various RTL gates
were obtained by varying the magnitudes of the resistors. Large resistors are used for low power applications and small resistors for high power.
5.1
5.2
Figure 5.2 shows an RTL configuration of parallel
(ideally matched) BJTs and base resistors using a
common collector resistor. For this circuit, the current through the single collector resistor is the sum
of the BJT collector currents and is given by
II
The output voltage is then
VouT = Vee - IReRe
This circuit is in fact a NOR gate, as can be seen by
examining various combinations of input voltage levels with corresponding output as in the following
sub-sections.
BASIC RTL INVERTER
Figure 5.1 shows the basic RTL inverter and its voltage transfer characteristic. TI1is is the simple BJT inverter presented and analyzed in section 4.2. The
critical voltages are
All Inputs Low
If all inputs V 1, V2, ••• , and Vn are less than VBdFA),
then all BJTs are cutoff. As a result, IRc = 0 and the
output voltage is
Vo11 = Vee
Vo11 = Vee
Vu_ = Vin(FA)
_ V
-
(SAT)
Bl<
(all inputs low)
Any Input High
Vm = Vn(SAT)
V Ill
BASIC RTL NOR GATE
+
Vee - Ve1c(SAT)
/3 R
RIJ
F e
If any input is greater than or equal to VBE(FA), the
corresponding BJT conducts collector current and the
resulting output is less than Yee• If any input reaches
Vn 1 (from Chapter 4) the corresponding BJT enters
saturation and the output drops to
The following sections show that NOR and NAND
gates can be constructed by adding additional transistors and base resistors. Later in the chapter, a noninverting RTL circuit will be presented along with
Vm. = V0 (SAT)
56
(for input high)
5.3
YourCV)
Basic RTL NAND Gate
57
edge of conduction
/
VOH = Vcc
Q(OFF)
~ Vour
edge of saturation
Q(SAT)
(a)
(b)
FIGURE 5.1
Basic RTL Inverter: (a) Circuit, (b) Voltage transfer characteristic
Since the circuit of Figure 5.2 has a high output
voltage for all inputs low and a low output voltage
for any input high, the logical NOR function is realized.
5.3
BASIC RTL NAND GATE
Figure 5.3 shows a two-input RTL configuration with
stacked BJTs. Assuming f3F is large (i.e. f3F >> 1) for
both BJTs, the base currents are negligible in comparison with the collector currents giving
In
=
Ic1
VIN,
0---
FIGURE 5.2
Basic RTL NOR Gate
and
Hence, it is clear that
and thus
As with the RTL inverter and the RTL NOR gate, the
output is given by
58
Chapter 5/Resistor-Transistor Logic (RTL)
Further increc1se of V2 is accompc1nied by a decrec1sing output voltage. When both Q 1 and Q 2 are saturnted, the output is
= 2Vc[(SAT) (both inputs high)
Vc)L
Your
RB2
VIN2
0 - ---------1\/V'v
R.,
-{o
V., o-------'sM
FIGURE 5.3
Q,
,
1•
Since the circuit of Figure 5.3 has a high output
voltage for any input low and a low output voltage
for both inputs high, this gate rec1lizes the logirnl
NAND function.
Multi-Inout RTL NAND Gate
.ii.
An RTL NAND gate with more than two inputs can
be fabricated by including more BJTs in the "stack"
as shown in Figure 5.4. The output low voltc1ge for
the multi-input NAND gate of Figure 5.4 is then
equal to
Two-input Basic RTL NAND Gate
II
VoL =
I
VcE,;(SAT)
i=l
The circuit of Figure 5.3 is an RTL NAND gate and
to verify that it provides this logical function, all combinc1tions of inputs are exc1mined in the following
sub-sections.
As demonstrated in the following example, the number of inputs to an RTL NAND gc1te is extremely limited.
Any Input Low
If the input to the BJT at the bottom of the stack in
~~
Figure 5.3 is less than V8 E(FA), then it will conduct
no collector current. Since the collector currents c1re
equal, the top BJT will also have zero collector current. From this, it is clear that if the bottom BJT is
cutoff, then the top BJT must also be cutoff regardless
of the top BJT input. If the bottom BJT input is high
and the top BJT input low, then the collector current
lc: 2, and therefore IRo is still zero. Thus, if any input
is low, IRc: = 0 and the output voltage is
V011 = Vee
~ Vour
(for input low)
All Inputs High
If the input to the bottom BJT in Figure 5.3 is high
enough to saturate it, the emitter voltage of the top
BJT is
VE2
=
VCJ
=
VCE(SAT)
.~"!
~
Vm, o ~ v v ~Q,
l
For the top BJT input to be forward active, its input
must then be at least
FIGURE 5.4
Multi-input Basic RTL NAND Gate
5.4
Example 5.1
5.4
Multi-Input RTL NAND Gate
What is the maximum fan-in for the basic RTL
NAND gate of Figure 5.4, if all stack BJTs have
VeE(SAT) = 0.17 Vandall load gates have V8 E(FA)
= 0.7 V?
nVeE(SAT) < VBE(FA)
That is, the output low voltage must be low enough
to maintain all load BJT in cutoff. The maximum
number of inputs is thus
< VBdFA)
=
VeE(SAT)
59
RTL FAN-OUT
When an RTL gate, such as the NOR gate of Figure
5.2, is in the output low state, any load gate would
be cutoff and draw no input current, since v;N =
VeE(SAT) < V8 E(FA). For a driving gate in the output
high state, all load gates are operating in saturation
and draw input current. The maximum fan-out of
RTL gates is therefore limited by the output high
state of the load gate. That is, the driving gate must
supply enough driving current to saturate all load
gates. This current must be supplied through Re of
the driving gate as shown in Figure 5.5a. As a result,
in the output high state a driving gate has an output
high voltage degraded by the voltage drop across Re
or
Solution The number of inputs to this gate is limited by the expression
11
RTL Fan-Out
(0.7) = 4.12
(0.17)
The maximum number of inputs is 4, since a fraction
of an input is meaningless.
V'cc
R'c,
V'our1
V'cc
Your= V'IN
.. r
R'C2
VIN o--------1\./V' ~Qo(OFF)
Y'oun
V'cc
..;..
I'.,CSAT)
R'
r
~ Lv'oUTo
-
Q'0 .(SAT)
I'••(SAT)
-:-
(a)
FIGURE 5.5 Development of Equivalent Circuit for RTL Fan-out Calculation: (a) RTL Inverter in output high state
with n identical load gates
60
Chapter 5/Resistor-Transistor Logic (RTL)
Development of Equivalent Circuit
To solve for the maximum fan-out of an RTL gate, it
is convenient to develop an equivalent circuit for
analysis. Figure 5.Sa shows an RTL inverter in the
output high state with several identical RTL inverters
as load gates (with element values primed to indicate
load elements). All of the load gates have inputs that
are high and thus the load BJTs are in saturation. At
the output of the driving gate, each load inverter appears as a base resistor in series with a voltage source
of magnitude VnE(SAT) to ground; as shown in Figure 5.Sb. The driving gate can be represented by just
the source voltage Vcc and the pull-up resistor Re,
as shown in Figure 5.5c, since the BJT is cutoff. Substituting the equivalent representations for the driving and load gates results in the equivalent circuit of
Figure 5.5d.
Since all base resistors in Figure 5.5d are connected to ground through a voltage source of magnitude V8 E(SAT), a further reduction to a single
source, as shown in Figure 5.5e is justified. Finally,
the parallel base resistors (of equal magnitude) of
Figure 5.Se can be combined into a single resistor of
magnitude Ri'i/N, as shown in Figure 5.5f. Hence, the
current through Re is the sum of the input currents
or N times the base current of each load transistor,
given by
11
Fan-Out Analysis
From the equivalent circuit of Figure 5.5f, an expression for the number of gates as a function of operating voltages and device parameters can be derived
by substituting for IRc and I~ to obtain
Vee - VouT = N(VouT - Vi1F.(SAT))
Re
R~
Solving for N and dropping the primes yields
N
=
Vee - VouT
RR
VouT - VRt;(SAT) Re
---=-=-----'--''--'---
V'cc
0
I
R'c
f
r-u V'om
V' IN
Votrr
~~ _____yQ' (SAT)
1-fsin ~
0----------___J\
0
-=-
~
Vee
R'B
V'"' o----'\/\/y-~~- ti'8 (SAT)
V'8 .{SAT)
+
~-
(b)
FIGURE 5.5 (continued) (b) Equivalent model for a
RTI" inverter in the output low state as seen from the
f
Re
Lv(c)
input, (c) Equivalent circuit for driving RTL inverter in
the output high state
5.4
RTL Fan-Out
61
Vee
I
Re
f
VOlif = V' fN
R'Bl
L--cr~-~----------1\/V'v-~
:
I~ -
7
Re
l
+
Il-{
v_.v,.
R'.,
)-------,---U·-~
I~
.i(SAT)
~'.iSAT)
I
-=-
I
I
--
1
I
1'.,(SAT)
I~
B.(SAT)
(e)
(d)
FIGURE 5.5 (continued) (d) All load gates replaced
with equivalent circuits of (b) and driving gate replaced
with equivalent gate of (ct (e) Equivalent circuit for the
driving RTL inverter in the output high state
still be large enough to saturate the load gates. That
is, the output high voltage must be at least VrH, which
was found to be
V0 m=V'fN
'------0-
R',IN
~----O--·----A./1/v----·1
-l--
Icc(OH) = NI'.(SAT)
V011 (min) =
Vi11
+
~'.iSAT)
(f)
FIGURE 5.5 (continued) (f) Parallel base resistors
combined into a single base resistor
As more current is sourced to the load gates through
Re of the driving gate, the voltage across Re increases
and V0 H decreases. The limiting factor in the maximum fan-out of the RTI inverter shown in Figure
5.Sa is that the output voltage of the driver gate must
Hence, substitution of VoH(min) into the previous
expression for N gives an eguation for the maximum
fan-out of RTI gates. The next example provides an
aid to understanding calculations of the maximum
fan-out.
Example 5.2
Busic RTL Maximum Fun-Out
What is the maximum fan-out for a basic RTI gate
with Vee = 5 V, R13 = 10 kfl, and Re = 1 k!1? Let
f3r = 25, V8 E(SAT) = 0.8 V, and VeE(SAT) = 0.2 V.
62
Chapter 5/Resistor-Transistor Logic (RTL)
Solution The minimum output high voltage is
V011 (min)
=
V 111
=
(0.8) +
Average Power Dissipation= Pcdavg)
The average power dissipated is obtained from
(5) - (0.2)
(25) (1k) (10k)
p
(
)
cc avg
=
Icc(OL) + lce(OH)
Vee
2
= 2.7 V
Substitution into the expression for N yields
N
=
(5) - (2. 7) (10k)
(2.7) - (0.8) (1/c)
The maximum tan-out is thus
Example 5.3
=
N:viAX
12
=
_1
12.
RTL Power Dissipation
Find the average power dissipated in a basic RTL
inverter with
(a) no load
(b) a fan-out of 1
5.5
RTL POWER DISSIPATION
To determine the average power dissipation of RTL
gates, the current supplied by Vee for the output high
and low state must be determined. These are the currents through Re for both output states, !Rc(OH) and
IrdOL).
Use Vcc = 5 V, Rll = 10 kf!, and Re = 1 kf!. Let
25, V8E(SAT) = 0.8 Y, and YcE(SAT) = 0.2 V
for the BJTs.
f3F =
Solution (a)
For no load
lcc-(OL) =
(5) - (0.2)
(lk)
= 4.8 mA
and
Output Low Current
Supplied - IcdOL)
lec(OH)
0
The average power dissipated is then
In the output low state, the driver BJT of a basic RTL
inverter is saturated. As discussed in the previous
section on fan-out, any load gates will be cutoff since
the output YoL = Ycr(SAT) < Y8E(FA). Therefore,
the current supplied by Vcc in the output low state
is
(4.8m) + (O)
Pedavg) = - - - - - (5) = 12 mW
2
Solution {b) For a load of one gate, IedOL) is unchanged and IedOH) is the input current to a gate
in the input high state (output low state) given by
!--(OH) = I
=
Output High Current
Supplied = IcdOH)
As shown in the previous section, the current supplied in the output high state depends upon the fanout. For no load gates, Ic:c(OH) = Ic(OFF) = 0, since
the BJT is cutoff. When load gates are connected,
Ic:c(OH) is the sum of the current sourced to all the
load gates. From Figure 5.Sf, this is seen to be
Icc(OH) = NI{i(SAT) = I 1,c
Vee - V~ 1JSAT)
Re+ RfJN
V~1:(SAT)
Re+ R!i
= Vee 111
LC
=
=
(5) - (0.8) = 382
(1k) + (10k)
µA
The average power dissipated is
(4.8111) + (382µ,)
-Pcc(nvg) = - - -2- - - (5) = 12.96 ml/\/
5.6
BASIC RTL NON-INVERTER
The basic RTL inverter can be modified to produce a
non-inverting output. Such a circuit is shown in Fig-
5.6
63
Basic RTL Non-Inverter
Q(SAT)
······:~
edge of
saturation
Your
(b)
(a)
FIGURE 5.6
Basic RTL Non-inverting Gate: (a) Circuit, (b) Voltage transfer characteristic
ure 5.63. The output of this basic RTL non-inverter
is taken at the emitter and has a magnitude equal to
This digital logic circuit is just the emitter-follower
used in analog circuits. The VTC of the RTL noninverter is analyzed in the following sub-sections. As
will be seen, the input high voltage of the RTL noninverter exceeds the supply voltage, sometimes by as
much as 50%, and limits its practical applications.
Output Low Voltage = VOL
Output High Voltage = Vott
With the RTL inverter, the output can only drop to
VcE(SAT) above ground. Conversely, the noninverter output can rise to only V cdSAT) below V cc•
Hence, the output high voltage is
Vol/
= Vee - VcE(SAT)
Input High Voltage = Vrn
The input high voltage is the minimum input necessary to saturate the BJT. With the collector-emitter
voltage at VeE(SAT), the emitter current is
For V,N < V8 E(FA), the BJT in the non-inverter of
Figure 5.6a is cutoff and IE = IRE = 0. With no voltage
drop across RE, the output is
I (SAT) = Vee - Vcr:(SAT)
E
Rr:
VouT = 0 = Vor,
At the edge of saturation, er= 1 and the base current
is related to the emitter current by
Input Low Voltage= V1L
When V13 E reaches V8 E(FA), the BJT enters the forward active region. When V,l'-: is increased beyond
V,i,JFA), BJT terminal currents begin to conduct and
the output voltage begins to increase. The input low
voltage is therefore
IB(EOS) = _J_E_ = Vee - VcdSAT)
{3, + 1
(f3F + l)Rr:
With V8 c
Vm
= V8 c(SAT), the input high voltage is
= Vee + VBc(SAT) +
=V
cc
Iu(EOS)RB
+ V (SAT) + Vee - VcdSAT) RH
BC
f3r + 1
Re:
64
Chapter 5/Rcsistor-Transistor Logic (RTL)
Vee
Note that the input high voltage for the RTL noninverter is greater than the supply voltage Vco thus
limiting its usage as a practical digital circuit.
0
I
VIN,
Example 5.4
R.,
V
Q----------------h,Q,,
Basic RTL Non-inverter VTC
I
Determine the critical voltages for the basic RTL
noninverter in Figure 5.6 and show that V1H is higher
than Vee- Use Vee= 5 V, R8 = 10 kD, and RE =
1 kD. Let f3F = 25, V8 E(FA) = 0.2 V, V8 E(SAT) = 0.8
V, and V0 (SAT) = 0.2 for the BJT.
Solution The critical points are found by substituting directly into the expressions derived in this
section:
R.,
VIN! 0---------J\/V'y
= 0
Vn = 0.7 V
VoL
V 0 u = (5) - (0.2) = 4.8 V
and
VIH = (5)
+
(0.6) +
(5) - (0.2) (10k)
(25) + 1 (lk)
= 7.4 V
The input high voltage of 7.4 Vis almost 50% higher
than Vcc and is too high to be practical.
5.7
Basic RTL AND Gate
FIGURE 5.8
AND gates. The basic RTL multi-input OR and AND
gates are shown in Figures 5.7 and 5.8, respectively.
The proofs that these gates perform the intended
logic functions are left as homework exercises.
BASIC RTL OR AND AND GATES
In sections 5.2 and 5.3 additional inputs were added
to the basic RTL inverter (NOT gate) to form NOR
and NAND gates. Similarly, additional inputs can be
added to the basic RTL non-inverter to form OR and
VIN,
R.J
o---'V\
Q,
5.8
RTL WITH ACTIVE PULL-UP
A metho~o increase the fan-out of RTL gates includes an active pull-up configuration as discussed
f
R.,~
0---------'\!\/\.---(Q,
V 00
~-----'-----------r~------------
FIGURE 5.7
Basic RTL OR Gate
R••~
------V:,------
• 0----------'\IV\~ Q,,
-
J
0 Your
5.8
65
RTL With Active Pull-Up
TABLE 5.2 States of BJTs for Output High
and Low States
:l
l
J
Your
Element
VoH
VoL
Qs
Qp
Qo
Cutoff
Saturated
Cutoff
Saturated
Cutoff
Saturated
ining VBEY for a high input. With the gate input high,
Qs and Q 0 are both saturated. Thus
VRllP
+
ViiE,I'
= VcE,s(SAT) - VcE,o(SAT) = 0
and Qp is cutoff. The purpose of each circuit element
of Figure 5.9 is tabulated in Table 5.1.
The state of all three BJTs for the output high
and low states are indicated in Table 5.2. These operating states are explained in the following subsections.
FIGURE 5.9
RTL Inverter with Active Pull-up
Fan-Out of RTL with Active Pull-Up
in Chapter 4. An RTL inverter using active pull-up is
shown in Figure 5.9. It consists of the BJT Qp, the
resistors RBr and Rep, and provides additional sourcing current in the output high state than did the simpler RTL inverter of Figure 5. la. To accomplish active
pull-up, Rep is smaller than Re by approximately one
order of magnitude. Q 0 operates as a BJT inverter
and supplies active current sinking during the output
low state. The magnitudes of R8 s and Rllo are equal
so that Q 5 and Q 0 turn on and off simultaneously.
The BJT Q 5 operates as a BJT inverter and provides logic inversion to Qp, such that Qp and Q 0 are
not on simultaneously. This can be seen by exam-
TABLE 5.1 Purpose of Each Element
for an RTL Gate with Active Pull-Up
Element
Purpose
Rr,s, Rn()
Matched input resistors
Drive splitter, pull-down of Qp
Along with Qs provides logic inversion to
output-high driver
Limits base current to Qp
Output inverting BJT, output-low driver for
current sourcing pull-down
Provides active current-sourcing pull-up
Part of active pull-up
Qs
R,
The fan-out of RTL with active pull-up can be determined using a method similar to that used for the
basic RTL inverter in section 5.4. An equivalent circuit is first obtained and then analyzed. As with the
basic RTL, the fan-out is limited by the current
sourcing capability of the driving gate in the output
high state.
In the output high state, the driving gate will be
connected to a low input, since the load gates conduct a great deal of current. As a result, Q 5 and Q 0
will be cutoff and Qp will be saturated. Figure 5.10a
shows the equivalent representation of the driving
gate for the output high state. Also shown in Figure
5.106 are the equivalent circuits for a single load gate
with v;i': high. As seen from the input of the load
gate, R{i and Rf 0 are both connected to voltage
sources of magnitude Y8 E(SAT). Since Rf and Rf 0 are
chosen to be equal in magnitude, an equivalent representation for a load gate when its input is high is
a resistance ofRM2 in series with V8 E(SAT), as shown
in Figure 5.106.
Figure 5.10c shows the equivalent representation for a driving gate with N load gates. Note that
a resistance of Rf/2N is present, since each load gate
has an equivalent input resistance of RM2. An expression for the number of load gates as a function
of operating voltages and device parameters can be
written by equating the emitter current of Qp from
66
Chapter 5/Resistor-Transistor Logic (RTL)
V' IN
R'BP
+
T V' .,s(SAT)
J--
0
Q.(SAT)
R'.f2
V'IN ~ +
Your= You
l ~'
(a)
0
.,s(SAT)
(b)
FIGURE 5.10 Development of Equivalent Circuit for
Fan-out Calculation of RTL with Active Pull-up:
(a) Equivalent circuit for output high state, (b) Equivalent
circuit for input high
the driving gate and the total load current NI;H as
follows:
Solving for N yields
N =
Assuming
IEP
= 10
Vee - VeE(SAT)
Vee - VeE(SAT) - VoUT R~
-==-----=.::....:__--..:._--=-=--.:.
-VouT - Vh(SAT)
,,
Vow
---=-=---=-'---'-------'-'-'--'-
Ra
As the number of load gates is increased, more current is sourced to the load gates through Qp of the
driving gate and the voltage drop across Rep in-
VouT - V{ic:(SAT)
R~2N
Q.(SAT)
R'.f2N
--
Your
NI'1H
(c)
FIGURE 5.10 (continued)
2Rep
(c) Circuit for fan-out calculation
5.9
Vo11(min) =
(5) - (0.2)
=
+
Vee
( ) (lk)
25
(10k)
2.7 V
Substituting into the expression for N yields
Substitution of Vrn 1(min) into the expression for N
gives the maximum fan-out of RTL gates with active
pull-up. The following example shows that active
pull-up does increase the fan-out for RTL.
(5) - (0.2) - (2.7) (10k)
(2.7) - (0.8)
2(100)
N =
5.9
Compare the maximum fan-out for the RTL inverter
with active pull-up (shown in Figure 5.9) with that
of basic RTL obtained in Example 5.2. Use the values
of Vee= 5 V, Rill'= R8 s = Rllo = 10 kfl, Re= 1 kfl,
f3F = 25, V1ir:(SAT) = 0.8 V, and VcE(SAT) = 0.2 V,
which are the same values used in Example 5.2. Also,
let Rcr = 100 fl.
RTL SPICE SIMULATION
Figure 5.11 shows the RTL inverter with active pullup with appropriate spice la be lings. The SPICE input
CIRcuit file that represents this circuit is as follows:
RTL inverter with active pull-up
VCC 7 D DC SV
n+ 7
vcc-T
oc sv
n- o
7
RC
lKOHM
RCP
l00OHM
6
RBP
--~
RBS
2
~
QP
l0KOHM
6
1
4
2
4
n~
VINn±
1
RB0
'------_J\/
3
= 55 ·
Thus, the maximum fan-out for RTL with active pullup is 55, an improvement of over 450% as compared
to the basic RTL fan-out found in Example 5.2.
Example 5.5 Maximum Fan-Out of RTL
with Active Pull-Up
4
3
3
\~----l
l0KOHM
FIGURE 5.11
Vi11
= (0.8) +
Vi11
= VBE(SAT)
67
Solution As in Example 5.2, the minimum output
high voltage is
creases, while VOi I decreases. The lirniting factor in
the maximum fan-out of RTL with active pull-up is
that the output voltage of the driver gate must be
large enough to saturate Q~ and Q() of the load gates.
In section 5.4, it was indicated that Vrn I must be at
least v,H or
V011 (min) =
RTL SPICE Simulation
RTL with Active Pull-up and SPICE Labelings
Your
68
Chapter 5/Resistor-Transistor Logic (RTL)
VIN(V)
4
5-..-------.
4
Your (V)
i
3
5
2
1
4
0 _,__-+--+--+---....------41---+--. t(ns)
100 200 300 400
600
0
3
Yaur(V)
•
2
54
-
3
-+-----"""----..,.......,_.,.......,_""i-~V~V)
1
2
3
4
2-
5
1-
0
__;__J-.,..........
~-l----------!'------l----""'~~►
0
(a)
100
200
300
400
500
t(ns)
600
(b)
FIGURE 5.12 Results of Section 5.9 SPICE Simulation
of RTL Inverter with Active Pull-up: (a) Voltage transfer
characteristic obtained from .DC sweep, (b) Transient
response obtained from .TRAN sweep
VIN 1 D DC DV PULSE<DV 5V
10NS 1DNS 200NS SOONS)
RBS 1 2 10KOHM
RB◊ 1 3 10KOHM
RBP 6 5 10KOHM
RC 7 6 1KOHM
-PLOT TRAN V(1) V(4)
-END
□ NS
+
RCP 7 8 1000Hi•i
QS 6 2 D QNPN
QP 8 5 4 QNPN
QO 4 3 D QNPN
-MODEL QNPN NPN<BF=25 CJC=2PF
+ CJE=4PF)
-DC VIN DV 5V □ -1V
-PLOT DC V(4)
-TRAN 1DNS b □ DNS
Note that the BJT model used includes values for
junction capacitance calculations so that a transient
response can be simulated. Graphical results from
this simulation are shown in Figures 5.12a and 5.126.
5.10 DIRECT COUPLED
TRANSISTOR LOGIC
AND CURRENT HOGGING
In an attempt to improve the packing density of RTL
in integrated circuit form, the base resistor RB was
eliminated. This produced another logic family called
Chapter 5 Problems
69
turn-on voltages given by 0.7 V, 0.7 V, 0.7 V, and
0.69 V. Determine the base current for each transistor and the output voltage of the inverter for the output high state (input low).
FIGURE 5.13 Three-input Direct Coupled Transistor
Logic (DCTL) NOR Gate (no base resistors)
£tired ~oupled _!:ransistor logic (DCTL), which was
doomed from its initiation. Figure 5.13 shows a three
input DCTL NOR gate. This gate functions correctly
with zero fan-out.
The problem with DCTL occurs for VoL:T = V01- 1
with fan-out greater than one because BJTs do not
have exactly the same VllE(FA) = 0.7 V. Under these
conditions, since RB = 0 the connected BJTs at the
output have their base-emitter junctions directly in
parallel. Hence, the BJT with the smallest VsE(FA)
will sink all of the current, while the remaining BJTs
are cutoff, since each of these have VBE < VBE(FA).
This phenomena is appropriately named current
hogging, since a single BJT hogs all of the current.
Current hogging is avoided by including bases or
emitter resistors.
Example 5.6
Solution Figure 5.14 is an equivalent circuit to replace the inverter with a fan-out of four. Each connected transistor base-to-emitter circuit has been replaced with a DC voltage and an ideal diode.
Similarly, the BJT has been replaced with an open
circuit, since the input is low. Note that the ideal
diode D 4 is the only diode that conducts current. This
is because when D 4 shorts Yoc'T = 0.69 V which is
insufficient to short ideal diodes Dv D2 , and D3 . The
base current of BJT 4 is therefore
Ill4
=
Vee - 0.69
R
e
Thus, BJT 4 "hogs" all the current and is the only
transistor that conducts current.
DCTL Current Hogging
Consider a direct-coupled RTL inverter without base
resistors (Rll = 0). Also, let the fan-out be four and
the connected BJTs have slightly different V8 E(FA)
FIGURE 5.14 Equivalent Circuit for a DCTL Inverter in
the Output High State with a Fan-out of Four for
Example 5.5
CHAPTER 5 PROBLEMS
5.1
5.2
For the RTL inverter of Figure P5.1 with Vee= 5 V
and Rll = Re = 1 kO., determine Vocr, Ill, and le for
(a) V 1N = 5 V
(b) V 1[': = 0 V
Use f3F = 30, VBl(FA) = 0.7 V, V13 E(SAT) = 0.8 V,
and Vcr(SAT) = 0.2 V.
Repeat Problem 5.1 for RB = 5 kO. and Re = 1 kO..
5.3
Repeat Problem 5.1 for R8 = 10 kO. and Re:= 1 kO..
5.4
Repeat Problem 5.1 for RB= 1 kO. and Re = 500 0..
5.5
Repeat Problem 5.1 for Rll = 4 kO. and Re = 2 kO..
5.6
Find the critical points and sketch the VTC for Problem 5.1.
5.7
Find the critical points and sketch the VTC for Problem 5.2.
70
Chapter 5/Resistor-Transistor Logic (RTL)
5.17
For the RTL NAND gate of Figure P5.17, find In 1,
IH2, !Re, and Vuc-r for all combinations of V1 and V2
equal to 0 and 5 V. Use f3r = 20, VBE(FA) = 0.7 V,
VR 1 (SAT) = 0.8 V, and VCE(SAT) = 0.2 V.
Yee= 5Y
Your
Re
2ill
Your
-::-
R.,
VYrT TDV TIE' -1
rJ,.l.
J. J.UUJ."\..L
y IN2
5.8
Find the critical points and sketch the VTC for Problem 5.3.
5.9
Find the critical points and sketch the VTC for Problem 5.4.
5.10
Find the critical points and sketch the VTC for Problem 5.5.
5.11
Figure P5.1 l shows an RTL inverter driving N identical gates. Determine Vmm IR, and le for N = 4 with
Vee= 5 V and
(a) VrN = 5 V
(b) VIN= 0 V
Hint: Are the load gates cutoff? If not, use an equivalent circuit representation as in Figure 5.5.
r
I
FIGURE P5.17
Repeat Problem 5.19 for V8 E(FA) = 0.7 V and
Vci:(SAT) = 0.15 V.
5.21
Repeat Problem 5.19 for V81 ,(FA) = 0.75 V and
Vu(SAT) = 0.2 V.
5.22
Determine the maximum fan-out for an RTL inverter such that Vrn 1 = 2 V. Let Vcc = 5 V, R8 =
fi.25 kn, and Re = 480 n. Let VB1(SAT) = 0.75 V
for the BJT.
►"'
5.23
Repeat Problem 5.22 for Vrn 1 = 1.8 V and Vm,(SAT)
= 0.8 V.
'J:l
5.24
Find the maximum fan-out for a basic RTL inverter
with Vcc = 5 V, RR = 5 kn, and Re = 1 kn. Let
f3F = 20, VBE(SAT) = 0.8 V, and VcE(SAT) = 0.2 V
for the BJT. Also, determine the average power dissipation with maximum fan-out.
5.25
Repeat Problem 5.24 for Vcc = 4 V, Rll = 10 kn,
and Re = 1 kn.
5.26
Repeat Problem 5.24 for Vee = 3 V, R8 = 10 kn,
and Re: = 1 kn.
5.27
In an attempt to increase the maximum fan-out of
the RTL inverter of Problem 5.24, the resistor values
are lowered to RB = 1 kn and Re = 100 n.
(a) Find the maximum fan-out of this gate with the
smaller resistances. Is N reduced 7
►~
► bl)
]
~
4z
-::-
FIGURE P5.11
5.14
Repeat Problem 5.11 for Rll = 10 kn and Re = 1
kn.
5.15
Repeat Problem 5.11 for RB = 4 kn, Re = 2 kn, and
N = 3.
5.16
Repeat Problem 5.11 for RB = 800
200 n.
n
)Q,
')
5.20
Yee= 5Y
I
4k0
What is the maximum number of inputs that an RTL
NAND gate can have if the BJTs are designed to
have VmJFA) = 0.7 V, 111 (SAT) = 0.8 Vand VcE(SAT)
= 0.11 V? (Sec Example 5.1)
Find the critical voltages and sketch the VTCs for
the RTL inverter of Figure P5.ll with loads of N =
1, 2, 3, 4, and 5 and compare. Use f3F = 50 and
VmlSAT) = 0.8 V.
y OUT = Y'IN
- :
5.19
Repeat Problem 5.11 for N = 1, 2, 3, and 5.
i~
~
Repeat Problem 5.17 for R1n = RB 2 = 10 kn and
Re= 1 kn.
5.13
R.,= lk!l
0
Q,
5.18
5.12
i
v.,
I
o----------1VVv
and Re =
Chapter 5 Problems
71
Vee= 5V
9
I
Re
lOOQ
3.6k.Q
RBP
A~B;
r
►
l~~I~
-::-
Vaur=V'rn:►
I
N identical gates
I
4
1.5k.Q
FIGURE P5.29
5.28
5.29
= 2.
(b) Calculate the average power dissipation for this
5.30
Repeat Problem 5.29 for N
gate with maximum fan-out and compare with
that of Problem 5.24.
5.31
Repeat Problem 5.30 for N = 3.
5.32
Repeat Problem 5.29 for N
5.33
Sketch the VTC for the RTL inverter of Problem 5.29.
A low-power basic RTL inverter has resistances
of RB = 25 k!1 and Re = 10 k!1. Let f3F = 20,
Vm/SAT) = 0 .8 V, and VCE(SAT) = 0 .2 V for the BJT.
(a) Find the fan-out of this gate with larger resistances.
(b) Compare the average power dissipation to those
for the gates of Problems 5.24 and 5.27.
For the RTL inverter with active pull-up in Figure
PS.29, find l 8 p, lcp, and Your for N = 0 (no load)
and
(a) V1N = 0 V
(b) VIN= 5 V
Use /3r- = 100, VnE(FA) = 0.7 V, VnE(SAT) = 0.8 V,
and V0 JSAT) = 0.2 V for all BJTs.
= 4.
5.34
Sketch the VTC for the RTL inverter of Problem 5.30.
5.35
Sketch the VTC for the RTL inverter of Problem 5.31.
5.36
Sketch the VTC for the RTL inverter of Problem 5.32.
5.37
Find the average power dissipated for the RTL inverter of Problem 5.29.
5.38
Find the average power dissipated for the RTL inverter of Problem 5.30.
5.39
Find the average power dissipated for the RTL inverter of Problem 5.31.
5.40
Find the average power dissipated in the RTL inverter of Problem 5.32.
6
DIODETRANSISTOR
LOGIC [DTL]
To improve upon the RTL circuits of the previous
chapter, diode-transistor logic, or DTL, was introduced
based upon the design of preexisting circuits. As the
name implies, circuits of the DTL logic family utilize
diodes and BJTs in their design.
In 1964, a version of DTL was introduced and
became the standard digital IC family for nearly ten
years. This form of DTL, marketed as the 930 series,
is easy to fabricate in IC form and was the standard
digital IC for approximately 10 years after introduced
in 1964. This family was still in use in some applications in the late 1980s.
6.1
Input Low Voltage= V1L
Increasing V1"' to the point where Q0 just turns on
is achieved when
The corresponding increase in Vx is
Vx = V,N
+
V0 ,1 (0N) = Vw(FA)
= vllE,O(FA) +
+
V0 (ON)
Vo,L(ON)
and both DL and Q0 turn on (conduct), where Q0 is
forward active. With Q0 forward active, V0 L7 =
VcE,o and begins to reduce from Vcc for increases in
VrN as Ic, 0 increases.
BASIC DTL INVERTER
Output Low Voltage - VoL
Figure 6.1 shows the basic DTL inverter and its voltage transfer characteristic. This family of logic circuits
was introduced to overcome the low fan-out of RTL
for VouT = VoH• Note that when Vrn 1 is the input
voltage to a load gate, the input diode D; is reverse
biased and sinks only the reverse saturation current.
Output High Voltage
Increasing V1c-: (and therefore Vx) further, eventually
drives Q0 into saturation giving
Vow = Vcco(SAT) = VclL
Input High Voltage= Vrn
= VoH
Transistor Q 0 enters saturation at
V,N
For VrN low, D 1 is forward biased as can be seen by
following dashed path 1 in Figure 6.1. The voltage
between the diodes is given by
Vx = VIN
+
Vo, 1(0N)
= Vm, 0 (SAT) + Vo_,(ON) -V0 , 1(0N)
=
1/lldSA T) =
Vi11
Since Vx can not increase any further, subsequent increasing of V1N opens D 1 . Resistor R8 must
be chosen small enough such that Q0 is in saturation
when Vx increases to
< Vn,L(ON) + Viiw(FA)
and is thus not large enough to turn on Dr. and Q0 .
Hence, Q0 is cutoff and IRc = Ic = 0. The output
voltage can be found by following dashed path 2 to
obtain
The logical NOT function is verified by examination of the resulting voltage transfer characteristic
72
A.2
Modified DTL
73
YourCV)
I
V~ a Vrn(SATJ- ______ ,.._- - - - - - - ~------t-t----------,..
ivIH = 0,8
VIN (V)
Va=0.7
(a)
FIGURE 6.1
(b)
Basic DTL Inverter: (a) Circuit, (b) Voltage transfer characteristic
of Figure 6.lb. Since Vn_ and V111 differ only by
VllE(SAT) - V13 E(FA), the transition width between
output high and low logic states is quite abrupt. The
actual width can be obtained experimentally or by
circuit simulation with results quite close to these.
connected to a BJT inverter. Indeed, as we will see in
section 6.4, the NAND function is inherently provided
Basic DTL NANO Gate
6.2
Notice that addition of another input diode, as
shown in Figure 6.2, resembles a diode AND gate
Additional Level-Shifting
0
DIA
I<]--~----< :,.____---I
VINA O
Dm
V!NB
-:-
o----------l<J----
Your
by the DTL logic family by adding diodes in parallel at
the input pointing outward (OUT).
MODIFIED DTL
Figure 6.3 shows a modified DTL inverter and its
associated voltage transfer characteristic. An additional level-shifting diode D1, 2 has been added in series with DL to shift the logic level transition by
Vn(ON) on the VTC input voltage axis. This improves the low noise margin NML, while still exhibiting an acceptable high noise margin NMH. The additional level-shifting diode also avoids the problem
of Q0 turning on before V1:-.: reaches 0.7 V (it was
assumed in the previous section that D 1, DL, and Q0
all turn on at precisely 0.7 V, however, this is not
achieved exactly). As seen in Figure 6.3b, the addition of Dt, 2 increases V1L and V1H by V0(ON) = 0. 7 V.
~
diode AND gate
FIGURE 6.2
BIT inverter
Basic DTL NAND Gate
Discharge Path
The inclusion of R0 and -VEE at the base of Q 0 provide a path for discharge of the stored base charge
74
Chapter 6/Diode-Transistor Logic (DTL)
YoA(V)
/edge of conduction
Qo(OFF)
/
YoH·------,
VIN
D,
Du
0---k'l----____L-~---
/
~L
1
Ro
additional level
shifting diode
~
YolJf
Qo
~
~~i
i
-V
BE
discharge
path
/
V0 L=VciSAT)-
-----------------i /
Qo(SAT)
... VIN(V)
(b)
Modified DTL: (a) Circuit with additional level-shifting diode and discharge path, (b) Voltage transfer
of Q 0 , when switched from saturation to cutoff. This
enhances the transition period and propagation delay time. The need for an additional source voltage
(and corresponding pin on ICs) can be avoided by
simply taking - VEE to be ground and using a smaller
valued resistance for RD.
6.3
edge of saturation
IYrn = 1.5
Yn.=1.4
(a)
FIGURE 6.3
characteristic
i;
/
Example 6.1
VTC of Transistor Modified DTL
Determine the VTC of the transistor modified DTL
inverter in Figure 6.4. Use V0 (0N) = 0.7 V for the
diodes and VRrJFA) = 0.7 V, Vm.(SAT) = 0.8 V, and
VcdSAT) = 0.2 V for the BJTs.
TRANSISTOR MODIFIED DTL
The fan-out of DTL circuits can be further improved
by replacing the level-shifting diode DL 2 with a BJT
QL and splitting R8 into two resistors, pR8 and
(1 - p)R8 , whose sum is R 6 , as in Figure 6.4. When
QL is on, it is self-biased to operate in the forwardactive region and is used in the emitter-follower configuration. This circuit improves fan-out by QL providing more base-driving current to Q 0 , allowing Q 0
to sink more current from an output load. If p = 1,
the base-collector junction of QL is shorted, causing
QL to act as a diode. The circuit then reduces to the
one in Figure 6.3. The role of each element of the
DTL gate in Figure 6.4 is summarized in Table 6.1.
The state of each diode and BJT is tabulated in Table
6.2.
Re
FIGURE 6.4
6 Jill
Transistor Modified DTL (930 Series)
6.5
TABLE 6.1
Purpose of DTL Elements
Element
6.4
75
DTL Fan-Out
DTL NAND GATE
Purpose
Input diode, limits 1111, and provides
ANDing
Limits I,L
Self biases QL
Base-emitter level-shifting for shift of
transition width and provides base
driving current to Q 0
Level-shifting diode for shift of transition
width
Provides discharge path for saturation
stored charge removal from base of Q 0
Output inverting BJT and output low driver
for current sinking pull-down
Passive current sourcing pull-up
Adding additional inputs to a DTL inverter, as in Figure 6.5, provides a circuit that performs the NAND
function. This can be seen by observing when any or
all inputs are low,
Vx
=
ViN(low) + V0 ,1(0N)
< V8 E.L(FA) + Vo,L(ON) + VaE,o(FA)
and Q0 is cutoff with
VouT
Vim
=
=
V cc
When all inputs are high, Vx is high, allowing Q0 to
saturate (provided that pR 8 is chosen properly) and
VOUT = VCE.o(SAT) = VoL
Solution The VTC for this improved DTL inverter
Thus,
The DTL logic family provides the
logical NANO operation
is found in an analogous manner to the method of
section 6.1. For VIN low, Q0 is cutoff and for VIN high,
Q 0 is saturated. Thus,
Vo11 = Vcc = 5 V
6.5
and
DTL FAN-OUT
Vo1, = Vcw(SAT) = 0.2 V
In determining the maximum fan-out for DTL logic
gates, we consider the case where V0 UT = VcJL for
the driving gate. The opposite case, where VoUT =
V0 H for the driving gate, reverse biases the input di-
Furthermore, Q0 turns on at
V1L
=
+ Vo,L(ON)
V13 E,o(FA)
+ VBE,L(FA) - Vo,1(0N)
= 2Vlll(FA) = 2(0.7) = 1.4 V
and saturates at
V111 = Vllc,o(SAT)
+
+
Vn, 1 (0N)
Vm:, 1 (FA) - V0 ,1(0N)
V13 E(SAT)
= (0.8)
+
+ V8 dFA)
pR.
(0.7) = 1.5 V
Re
I--,
Note that QL can never saturate because the voltage
polarity for the resistor (1 - p)RB maintains a negative VBc,L for QL·
(1-p)R8
TABLE 6.2 State of Diodes and BJTs
for Output High and Low Levels
6ill
2ill
VINA
Your
<2i,
VINB
DIA
Dm
Ro
YoH
YoL
VIN~
D,
QL
DL
On
Cutoff
Cutoff
Cutoff
Cutoff
Forward active
On
Saturated
Du
FIGURE 6.5
DL
Qo
Element
Oo
1.75 ill
5 ill
J.930 Series DTL NAND Gate
76
Chapter 6/Diode-Transistor Logic (DTL)
N=
I
IQL
n,
I'Il.l
N identical load gates
,1
-
I ..A
I
Dm
!
• !NB ~
'
FIGURE 6.6
DTL NAND Gate in Output Low State Driving N Identical Load Gates
odes of all load gates. Such gates sink very little current and hence do not impose a fan-out restriction.
On the other hand, a low driving gate output voltage
is established with all driving gate inputs high and
fan-out is limited for this situation.
The maximum fan-out is obtained by determining how much output current IoL the driving gate
can sink from multiple, identical output gates as depicted in Figure 6.6. Since each load gate will have
the same input current 11u from KCL, we have
Nln
= 10 1,
or
N =
101,
lIL
To determine N, we use Figure 6.7, which shows one
of the load gate explicitly with Your = v;N = Vm.
As previously noted, the individual device and components in the output load gate have a prime to distinguish the load gate components from the driving
gate components.
Input Low Current
= l 1L
IrL is found by following dashed path 1 of Figure 6.7,
and writing this current as the difference in voltage
across the resistors in series divided by the sum of
the resistors. Hence,
Output Low Current
= IoL
Im is found by writing KCL at the collector of Q 0
where
loL = lc,o(SAT) - 11,e
The current through Re is found by following dashed
path 2 of Figure 6. 7, yielding
fRe
Vee - Vc,o(SAT)
= ----·--Re
The collector current of Qo(SAT) is obtained from
lc, 0 (SAT) = crOLf3,IH,o(SAT)
where um is the saturation parameter introduced in
section 3.7. However, for maximum fan-out, Vv'C consider operation at the edge of saturation where er= 1
and
lc, 0 (SAT)
=
lc, 0 (EOS)
=
/3 1 1/l,o(EOS)
To determine this quantitatively, we write KCL at the
base of Q 0 to obtain
6.5
DTL Fan-Out
77
V'cc
1
0
-~1
. -+--
I
pR'•!
R',
Re
6 ill
*
(l-p)R i
---3--------·
0---- K ,-~~--------i
~ ' V',~
D'L
Q'o
'OIIII
IoL
5 ill
?
_
~
____)
driving gate (output low state)
FIGURE 6.7
6k{l
(l-p)R'•!
VOL== V'rn
8
VIN
I'
2
~
load gates (output high state)
Cascaded DTL Gates for Fan-out and Power Dissipation Calculation
where
The emitter current of QL is found by analyzing
the portion of the driver gate including V cc, pR!l,
(1 - p)Rll, Q1,, Du and Q 0 as redrawn in Figure 6.8.
Considering Q1, and (1 - p)R 11 as a super-node, the
current through pR 8 is equal to the emitter current
of Q1,. Assuming IB.L negligible, the emitter current
of Q 1 is
Vee - Viiu(FA) - Vo.L(ON) - VHE,o(SAT)
pRB
The following example indicates the use of these
equations.
Example 6.2
DTL Fan-Out
Calculate the fan-out for the DTL inverter of Figure
6.6 considering the circuit in Figure 6.7 and the sub-
FIGURE 6.8 Portion of DTL Driving Gate for Fan-out
Analysis and Power Dissipation Analysis
78
Chapter 6/Diode-Transistor Logic (DTL)
circuit in Figure 6.8. Let f3F = 49, Vtm(FA) = 0.7 V,
V8 E(SAT) = 0.8 V, and VcE(SAT) = 0.2 V for the BJTs
and V0 (ON) = 0.7 V for the diodes. Also, use cr01.
= 0.85 for the output low state.
Hence, the fan-out of this DTL gate is 54. Note that
I8 _0 = 1.40 mA is indeed large enough to saturate
Qo,
Solution Substituting these values directly into the
derived equations yields
6.6
- I
- (5) - (0.7) - (0.2) - 1 09
In - pRB (3.75k)
- .
IRc
I
=
(5) - (0.2)
(6 k)
=
(5) - 2(0.7) - (0.8)
------(0.467)(3.75k)
E,L
IRD
=
(0.8)
(5k)
A
1/l
=
To determine the average power dissipation of a DTL
gate, we first detenTtine the currents being supplied
by Vcc for both the high and the low output states.
Notice that these currents have already been obtained in the fan-out analysis of the previous section.
= 800 µA
=
Output High Current
Supplied = IcdOH)
A
1. 60 m
For the output high state, the input is low [i.e.
= 160
V 0 :(SAT)], and considering dashed path 3 in Figure
µA
6.7, we have
18 , 0 = (1.60m) - (160/L) = 1.44 mA
Ic,o = (0.85)(49)(1.44111) = 60 mA
IoL = (60m) - (800µ,) = 59.2 mA
N
DTL POWER DISSIPATION
(59.2111)
(1.09,n)
Since Q0 is cutoff, IRc(OH) = 0, and
= 54.3
lcc(OH)
=
1"1w(OH)
8
1.75KOHM
8
4
RCP
6KOHM
7
i
4
2KOHM
I
1/4
VO\J'f
DIA
s
------<·,--~,-a-,-L---3 " ' 'QL
PULSE
DI~
,)1
DL
5
6
6
6
n+~3
VINB ¥PULSE
RCD
0
-::-
DTL Gate with SPICE Labelings
QO
0
5KOHM
0
FIGURE 6.9
7
!
6.6
79
DTL Power Dissipation
Additionally, the current through Re for this output
low state is simply
Output Low Current
Supplied= IcdOL)
For the low output state, the input is high, then
I"1w(OL) = lu
Vee - VBdFA) - V0 (ON) - VBr(SAT)
pRB
Thus,
5--,,..--.
4
3
2
1
O
VNAND (V)
------j1..._--1--------11---.....__---I--• t(ns)
0
50
100
150
200
250
vrn..(V)
5+----,
5-,----4
4
3
3
2
2
1
0 +----+---,&...-.....+----!---+-~ t(ns)
100
150
200
250
0
50
VAND(V)
0
0
2
3
4
5
5-4
32
1
0
----1'-------1------l----LJ....,,,.,,..__
0
(a)
FIGURE 6.10 Results of Section 6.7 SPICE Simulation
of DTL Gate: (a) Voltage transfer characteristic obtained
50
100
150
200
__,._
t(ns)
250
(b)
from .DC sweep, (b) Transient response from .TRAN
sweep
80
Chapter 6/Diode-Transistor Logic (DTL)
Average Power Dissipation= P0 (avg)
The average power dissipated is now found by substituting into
p (
D
) _ Icc(OH)
avg -
+ Icc(OJ.',) V cc
2
=
IpRB(OH) + lpRa(OL) + IRc(OL) Vee
2
Example 6.3
DTL NAND Gate
VCC 8 0 DC 5V
VIN1 1 D DC 5V PULSE(OV 5V OS
+ 2NS 2NS 50NS 1DDNS)
VIN2 2 D DC 5V PULSE(OV 5V OS
+ 2NS 2NS 1DDNS 200NS)
R81 8 4 1-75KOHM
R82 4 3 2KOHM
RC 8 7 bKOHM
RD b D 5KOHM
DI1 3 1 DIODE
1\T-,
DTL Power Dissipuiiun
l/l.C
-,
.:I
-,
C
1\T/\1\r-
lll.Vllt.
6. 7 DTL SPICE SIMULATION
DL 5 b DIODE
-MODEL DIODE D(CJ0=-5PF)
QL 4 3 5 QNPN
QO 7 b D QNPN
-MODEL QNPN NPN(8F=49 CJC=2PF
+ CJE=4PF)
-DC VIN1 DV SV □ -1V
-PLOT V(7)
-TRAN 2NS 250NS
-PLOT TRAN V(VINA) V(VINB)
+ V(7)
-END
Figure 6.9 shows a 930 series DTL NAND gate with
appropriate SPICE labelings. The SPICE input CIRcuit file that represents this circuit is as follows:
The VTC and transient response obtained from simulating this circuit are shown in Figures 6.10a and
6.106.
Calculate the average power dissipation for the DTL
gate in Example 6.2.
Solution Direct substitution of the values calculated in Example 6.2 yields
PD (avg) =
(1.09m) + (1.60111) + (800µ,) ( )
5
2
= 8.73 mW
CHAPTER 6 PROBLEMS
6.1
Vll 1 (FA) = 0.7 V, Vm(SAT) = 0.8 V, and Vu,(SAT)
= 0.2 V for the BJT. Also, determine the high and
low noise margins.
Determine the VTC (V0 uT versus V1N) for the DTL
NAND circuit of Figure P6.l with V1N 1 = V1N 2 = V1:--J.
Let VD(ON) = 0.7 V for the diodes and /3 1 = 100,
6.2
Repeat Problem 6.1 for the DTL circuit of Figure
P6.2.
6.3
Show that the circuit of Figure P6.1 performs the
logical NAND function by determining Von for all
possible combinations of V1r-,: 1 and V1N 2 , where each
of these are either low (0 V) or high (5 V).
6.4
Determine the VTC (Vrn;-i versus V1N) for the DTL
NOR gate of Figure P6.4 with V1N1 = V1N 2 = VIN·
Let VD(ON) = 0.7 V for the diodes and /3 1 = 100,
V8 r(FA) = 0.7 V, Vm(SAT) = 0.8 V, and Vc 1 (SAT)
= 0.2 V for the BJT. Also determine the high and
low noise margins.
6.5
Show that the circuit of Figure P6.5, with the input
diodes reversed (from Figure P6.4) performs the log-
Your
DIA
DL
VINA 0---------kJ·~----,__L_~--f:>f-~--J
VINII
0------ -- ~ - -
FIG URE P6.1
Qo
l
81
Chapter 6 Problems
Let V1)(ON) = 0. 7 V for the diode and /3 1
100,
V81 (FA) = 0.7 V, VtdSAT) = 0.8 V, and Vc 1 (SAT)
= 0.2 V for the BJT.
Vcc=5V
___ _ l ~
Consider the basic DTL inverter of Figure P6.8. Let
VD(ON) = 0. 7 V for the diode and /3, = 50, Vlll;(FA)
= 0.7 V, Vm/SAT) = 0.8 V, and Vn(SAT) = 0.2 V
for the BJT. Sketch the VTC and determine the noise
margins.
6.8
R,
I 5Ml
i[nu~
~---0
D~
VINA
~T---t>f----v
D
V[NB
VOUT
~ Oo
1
Vcc=4 V
f
I
o-------14-__j
- - - - - ___ f _ _ _ - -
FIGURE P6.2
Re
Vcc=5V
2kil
Re
0 VOUT
i
Re
1 kil
D~
INA
---0
Re
~
V~ o-
- ~---
IOMl
V
OUT
FIGURE P6.8
/
- ~Oo
~
FIGURE P6.4
6.9
Repeat Problem 6.8 with DL replaced with three PN
diodes connected in series.
6.10
For the circuit of Problem P6.8, calculate the following:
(a) The input low value of current 111 _
(b) The output low value of current Im.
(c) The maximum fan-out= N = IoLII1L
(d) The average power dissipation
6.11
Repeat Problem 6.10 for R8
ical NAND function by determining Vour for all
possible combinations of V1N 1 and V1N 2 , where each
of these arc either low (0 V) or high (5 V).
= 5 kn and Re = 1 kn.
I
I
pRe
i
i
1.75 kil
Re
5 kil
I
(1-p)Re
o--+(1----i-L
D~
2 kil
-0 Your
VINA
Dm
V!NB
I
o------J<I-~'
J
VlNB
o--l<J---
FIGURE P6.5
Dm
6.6
Repeat Problem 6.4 with a diode in series with Ru.
6.7
For the DTL gate of Figure P6.5, determine !RB, !Re,
In.n, and Vrn;r for all possible combinations of low
(0.2 V) and high (5 V) inputs. Also, sketch the VTC.
(
FIGURE P6.12
Q_
DL
~-0>1------,-~7
82
6.12
Chapter 6/Diode-Transistor Logic (DTL)
Determine the VTC CVuur versus V,") for the transistor modified DTL NAND gate of Figure P6.12
with V1r,.; 1 = V1r,.; 2 = V,r,.;. Let VD(ON) = 0.7 V for the
diode and f3F = 50, VndFA) = 0.7 V, VnE(SAT) =
0.8 V, V0 o(SAT) = 0.2 V, and u 0 L = 0.85 for the BJT.
Also determine the noise margins.
(a) The input low value of current
I,L
(b) The output low value of current Irn.
(c) The maximum fan-out -
N
= 101 /I,L
(d) The average power dissipation
6.15
Repeat Problem 6.14 for RB = Re = 1 kfl and p =
0.4.
6.13
Repeat Problem 6.12 for R8 = Re
p = 0.4.
1 kfl and
6.16
For the circuit of Figure P6.12, determine V 011 and
Vm for a fan-out of N = 10.
6.14
For the circuit and data of Figure P6.12, calculate the
following:
6.17
Repeat Problem 6.14 for p = 0.3 and R8 = 5 kfl.
6.18
Repeat Problem 6.14 for p = 0.5 and RB = 2.5 kfl.
TRANSi
GIC
In 1965, transistor-transistor logic (TTL) was introduced. As the name implies, the usage of diodes in
DTL is replaced with transistors (BJTs) in TTL. The
resulting TTL circuits provide increased fan-out, improved transient response, and a reduction in chip
area required. TTL circuits are the first of the 54X00/
74X00 series of BJT logic families. The 74X00 series
are adequate for most commercial applications and
operate over a temperature range of 0 to 70°C. The
54X00 series have the same logic circuit design as
the 74X00 circuits but operate over the superior temperature range -55 to 125°C and are primarily used
for military applications.
As will be seen, the main improvement in TTL
design over DTL is the inclusion of an active pull-up
sub-circuit. This results in faster charging of the
equivalent output capacitance and thus improved
circuit performance.
7.1
high values and determine the corresponding output
voltage range.
Output High Voltage
== VoH
For V,N low, the base-emitter junction of the input
BJT Q 1 is forward-biased. Following dashed path 1 in
Figure 7.1 yields
Ill.I
Vee - Viiu - V1N
=---~--
RB
The magnitude of this current is in the milliamp
range for typical values of R11, so Q1 operates in saturation for V1N low. The base-emitter bias of the output BJT Q0 is found by following dashed path 2 in
Figure 7.1 to obtain
v/3E,o =
V1N
+
vcE_i(SA T)
From this it is clear that Q0 is cutoff for low V1N
giving
BASIC TTL INVERTER
The basic TTL inverter along with its voltage transfer
characteristic are shown in Figure 7.1. Note that the
input and level-shifting diodes of the basic DTL inverter have been replaced with a single BJT Q1 at the
input. Moreover in this TTL circuit, the base-emitter
junction of Q1 replaces the DTL input diode, the
base-collector junction of Q 1 replaces the DTL levelshifting diode, and the base of the BJT acts as a
common P region. The advantage of the input BJT
over the diodes is two-fold. The BJT requires less silicon surface area than the two diodes and propagation delay time is improved by an order of magnitude, as will be discussed in section 7.2.
To determine the voltage transfer characteristic,
we consider V,N to vary from low values through
Input Low Voltage== V1L
As V 1N is increased, Q0 turns on when V,N reaches
ViN
=
vllco(FA) - vCE_1(SAT) = V1L
which is observed by following dashed path 2 in Figure 7.1. With further increase ofV1N, the output voltage begins to reduce, until Q 0 saturates.
Output Low Voltage
== VoL
As VrN is increased further, the output voltage
reaches its minimum which is VcE.o(SAT) and
Vex
83
= V cE,o(SA T)
84
Chapter 7/Transistor-Transistor Logic (TTL)
Your(V)
•
V~ = V~(SAT)+- -------- :+1_ _ _ _ _ __
- - - - - - ; , + - - - - - - - - - - - . . vIN (V)
lyrn = 0.6
Vn. = 0.5
(a)
FIGURE 7.1
(b)
Basic TTL Inverter: (a) Circuit, (b) Voltage transfer characteristic
Input High Voltage == Vrn
The corresponding input voltage for which Q0 just
saturates is given by
base when undergoing a transition from saturation
to cutoff. The initial current (upon switching) for
stored charge removal is
I SCI<
VrN = Var,o(SAT) - Veu(SAT) = Vin
which is again observed by following dashed path 2
in Figure 7.1. Consequently, Q0 remains saturated
for values of V 1N higher than V,flHowever, as V,N is increased further, the baseemitter junction of Q, eventually becomes reversebiased. Following dashed path 3 of Figure 7.1, it is
seen that
_ VBE,o(SAT)
RD
RD -
For the basic TTL circuit of Figure 7.1, R0 is unnecessary because Q, provides a low resistance path
for charge removal. When V1N is switched from high
to low, Vc, 1 is still at
Vc,r
= V BE,o(SAT)
and the input voltage to Q,,
VBe,r = (Vee - l1l,/RB) - VBE,o(SAT)
and the base-collector junction of Q1 is forward biased. Therefore, for high inputs, Q 1 operates in the
reverse-active mode. Note that a significant current
flows across the base-collector junction of Q1 into the
base of Q0 providing further evidence of Q0 operating in saturation.
_ I
-
Vu
=
VcJL
=
VE,I,
is switched to
Veui(SAT)
where we assume that the input is connected to another TTL gate in the output low state. Since the
base-emitter junction of Q 1 is now forward biased
VB,r = VE,I
+
VBE,i(FA) = VeE(SAT)
+ VaE(FA)
and
7.2 COMPARISON OF
STORED-CHARGE REMOVAL
FROM DTL AND TTL
For DTL circuits, an additional resistor was added to
the base of Q0 to remove stored charge from the
vBc.1
=
v B,1 - v c.1
= Vu(SAT) + VBdFA) - v/JE(SAT)
While the base-collector junction of Q1 is forward
biased, it is insufficient to saturate Q,, and Q 1 therefore operates in the forward active mode. The resulting collector current of Q1 is
7.4
Ic,1 = f3FIB,1 = f3F
=
Standard TTL NAND Gate with Totem Pole Output
Va:
Vee - VB,I
y
RB
I
---- -- - - - -
Vee - VBE(FA) - Vu(SAT)
~f
which provides an enormous initial current (upon
switching) for stored charge removal from the base
of Q0 . This in turn improves propagation delay time
by an equivalent factor.
Example 7.1 Stored Charge Removal
Comparison
Calculate the factor of improvement for stored
charge removal for TTL over DTL. Let Vcc = 5 V, R8
= 2 kfl, and Ro= 5 kfl. Use f3F = 50, VlldFA) = 0.7
V, VllE(SAT) = 0.8 V, and VcE(SAT) = 0.2 V for the
BJT.
Solution Substituting these values directly into the
derived expressions yields the magnitudes of the currents as follows:
Irw =
=
160 µA
and
2
5
IB,o = (50) ( ) - (~;]) - (0. ) = 102.5 mA
The factor of improvement is therefore
102.5m = 640.6
7
I
f3F - - - - - - - - - - = - IB,0
RB
(0.8)
( k)
5
85
Vairr
FIGURE 7.2 Basic TTL NAND Gate with Multi-emitter
BJT Input Stage
To show that this multiple-emitter input provides the NAND function, all combinations of low
and high inputs are considered.
Any Input Low
Considering Figure 7.2, if any input is low the corresponding base-emitter junction is forward biased
allowing a large current to flow in R8 and forcing QI
into saturation. Q0 will be cutoff since insufficient
voltage is present with
VsE,o = ViN(low)
+ Vcu(SAT) < VsdFA)
and thus
160µ,
7.3 BASIC TTL NAND GATE AND
THE MULTIPLE-EMITTER BJT
The inherent similarity between DTL and TTL suggests that
The TTL logic family provides the logical
NAND operation
and this is indeed true. The question at hand then is
how to provide multiple inputs. A separate BJT could
be used for each input with coupled bases and cou pled collectors. However, a unique alternative is to
make use of the multiple-emitter BJT presented in
Figure 3.3, as seen in Figure 7.2, The multiple-emitter
BJT requires much less chip area than using individual transistors for each input and is the "heart" of
TTL.
All Inputs High
With all inputs high, all base-emitter junctions of QI
in Figure 7.2 are reverse biased with the base-collector junction forward biased. Thus, QI is operating in
the reverse-active mode. With QI providing a large
current to the base of Q 0 , Q0 is in saturation and
VouT
=
VCE,o(SAT)
= Vot
Hence, the basic TTL multiple-emitter BJT gate provides the NAND operation.
7.4 STANDARD TTL NAND GATE
WITH TOTEM POLE OUTPUT
Figure 7.3 displays the circuit diagram for the series
5400/7400 Standard TTL gate in a 2-input NAND
86
Chapter 7/Transistor-Transistor Logic (TTL)
with an initial current given by
.
I,, 1111 _11 /'(passzve)
Vee - Vew(SAT)
= ---'--'----="-C..----'---
Re
For the TTL with active pull-up, the equivalent load
capacitance charges through Rm giving
where Rer is typically a tenth of Re. The initial current for the active pull-up circuit can be found folhmnrh
of
FiITT1rP
7 .1
lowine:
u the totem 1nole outn11t
1
- -- -o-·~ -· · ·-,
where
l1,,i11_111 ,(active)
_ Vee - VG,P(SAT) - Vo,L(ON) - VeE,o(SAT)
Rer
Vee - 2VedSAT) - V0 (0N)
Rcr
FIGURE 7.3 Standard 5400/7400 Series TTL NAND
Gate with Totem-pole Output
arrangement. The additional circuit components alleviate speed limitations manifested in the basic TTL
gate of Figures 7.1 and 7.2, as we will see. The stacking of two BJTs, a resistor, and a diode in the output
branch is called a totem pole output. To observe the
improved switching performance, the output load is
modelled as a capacitance CEQ and its charging and
discharging is studied.
Comparison of Load Capacitance
Charging for Basic TTL and TTL
with Totem Pole Output
which is much larger than Ipull-up(passive) because
Rep << Re. Hence, TTL gates with active pull-up
have a much smaller rise time constant and much
larger initial current than the basic TTL gates.
Other Additional Elements
An explanation of the other additional circuit elements in Figure 7.3 is appropriate. First, the addition
of Q 5 provides base driving current to Q 0 to ensure
saturation. Along with Re and DL, Q 5 also provides
logic inversion to Qp in the following manner. When
Q0 is in saturation, Q5 is also in saturation and Q"
is off, since
with
The addition of Rep and Qr to the output high driver
portion of the circuit provides active pull-up. This
means that a large current is available for charging
the equivalent load capacitance when the output
switches from low to high (due to the input switching
high to low). The improvement in rise time is easily
observed by comparing RC time constants and initial
currents provided at the output for the basic TfL gate
of Figure 7.1 with passive pull-up and the standard
m" gate in Figure 7.3. For the basic TTL gate, the
equivalent load capacitance charges directly through
Re, resulting in a rise time constant given by
VE.P
=
VeE,o(SAT) + Vo,L(ON)
and taking the difference yields
Vau = VaE(SAT) - V0 (0N) < V8 dFA)
Hence, Qp and Q0 are never on simultaneously. Additionally, the input BJT Q 1 aids in the pull down
of Q5 .
Second, the resistor R 0 is again necessary to remove stored charge from the base of Q0 , since Ie, 1
no longer directly sinks Q0 . For standard TTL, this
is not as severe as in DTL, since Q0 for TTL does not
become heavily saturated.
7.5
TABLE 7.1 Purpose of Each Element
for a Series 5400/7400 Standard TTL Gate
Element
Purpose
Multi-emitter input BJT, base-collector level
shifting of transition width, pull-down of
Qs
Limits 11L
Drive splitter, provides base driving current
to Q0 , base-emitter level shifting for
shift of transition width, pull-down of
Standard TI'L Voltage Transfer Characteristic
87
Vmrr(V)
t
Vcc=5+
I
4 Q, and Q, turns on
V oH = 3.6 Qo ~
3
V 08 = 2.5
2.
QI'
Along with Qs provides logic inversion to
output-high driver
Output inverting BJT, output low driver for
current sourcing pull-down
Diode level shifting between Vcc and
output
Provides discharge path for saturation
stored charge of Q0
Provides active current-sourcing pull-up
Part of active pull-up and limits current
spikes during output high-to-low
transitions
Input clamping diodes to limit the negative
swing of the inputs to one diode drop
below ground
Q, and ~ enter saturation
VOL= 0.2 ~-i-----t--i--r-----------------------,.-----,-----,------,...--.__.
2
3
4
V 11, = 0.5
V m = 1.4
Vm = 1.2
FIGURE 7.4 Voltage Transfer Characteristic for the
Standard 5400/7400 Series TTL Gate
VIN/\ = v,Nll = v,N- The resulting VTC is displayed
in Figure 7.4 with all critical points labeled.
Output High Voltage = Von
For V1"' low, a large current (following dashed path
1 in Figure 7.3) flows into the base of Q 1, given by
Finally, the clamp diodes beh-veen each input
and ground are required in order to avoid high frequency LC oscillations at the output. These oscillations are a result of any inductance the load may
exhibit. This in turn could cause the output, and its
cascaded inputs, to rise above Vcc when switching
from low to high and drop below VcE(SAT) when
switching from high to low. Rll limits the input current for the first case but voltage spikes can occur at
other nodes of the circuit for the second case. The
clamping diodes serve to limit the negative swing of
the input.
The purpose of each element for the TTL inverter
of Figure 7.3 is summarized in Table 7.1.
7.5 STANDARD TTL VOLTAGE
TRANSFER CHARACTERISTIC
]BI
.
RB
But the collector current of Q 1 is limited to the leakage current of Q 5 (which will momentarily be proven
to be cutoff for low V1N), where
lc, 1
= -IB,s(/eakage) << f3rIB,J
Under these conditions
Ic,1 << IB,1
And Q 1 is saturated. Following dashed path 2 in Figure 7.3, the voltage at the base of Q 5 is given by
Vzi,s = VIN + Ve[,l(SAT) < VudFA)
Hence, Q 5 , and therefore Q 0 , are cutoff for V,:-.i <
VBE,s(FA)
VeE, 1(SAT). With Qs cutoff, IRc = lc,s =
0 (neglecting 18 y) and VB,!' = Vcc- Thus, the baseemitter junction of Qp, and DL, will be forward biased. Following dashed path 3 in Figure 7.3, we have
Vmrr
= Vee - VllE,P(FA) - Vo,L(ON)
Vee - VrJ(ON) - VaE(FA) = Vou
Assuming a cap active load, V01-i is reached when the
load is charged with QP and Q, at the edge of conduction (EOC).
=
To determine the voltage transfer characteristic
(VTC) of the standard TTL gate in Figure 7.3, we
consider the two inputs connected together with
Vee - VuE,/ - VIN(/ow)
=--------
88
Chapter 7/Transistor-Transistor Logic (TTL)
Input Low Voltage= V1L
As Yi:'! is increased and VB,s reaches V 13 E(FA), Qs becomes forward active when
VIN= VBE,s(FA) - VeE,1(SAT)
= VIL
With Q5 conducting current, V OL'T begins to drop
as VIf\c increases because of the increasing voltage
across Re.
Input Breakpoint Voltage= Vrn
A
'\: 7
_
_ _ _I
(
,1
_
. • .
_.
T
_
KS VIN !S lll(:!edseu IU!l!ler, Sll lCe IE,S
~
T
_
lc,s -
T
IRI),
the voltage at the base of Q0 begins to rise. Following dashed path 4 in Figure 7.3, we note that Q0
becomes forward active when
ViN
1l1is value of output voltage is indicated on the VIf\c
axis in Figure 7.4.
Output Low Voltage = VoL
With Q 0 operating in saturation, the output voltage
is given by
VouT
=
Ve£,o(SAT) = V0 1,
Qp is then turned off, as discussed in section 7.4.
The overall VTC is shown in Figure 7.4. Cutoff,
turn on, and saturation operation are indicated on
this diagram. Table 7.2 summarizes the state of each
diode and BJT for the output high, breakpoint, and
low voltages.
= Vi,E,o(FA) + VBE,s(FA) - Veu(SAT)
=
2V8 dFA)
VeE(SAT) = Vrn
Note that Q0 turning on causes a change in slope of
the VTC as indicated in Figure 7.4 at VIN = Vrn,
Example 7.2
Output Breakpoint Voltage = V08
Calculate V of!, VIL, VIH, and V 0L as well as Vrn and
V 08 for the standard TTL gate of Figure 7.3. Let f3F
= 100.
The output voltage corresponding to V 18 can be
found by noting that as Q0 just turns on
IRe
I
=
RD=
V11E,o(FA)
Ro
Solution Substituting values from Figure 7.3 directly into the derived expressions yields
= (5) - 2(0.7) = 3.6 V
VIL = (0.7) - (0.2) = 0.5 V
Vrn = 2(0.7) - (0.2) = 1.2 V
V 011
Thus,
VouT
=
Vee - lr<eRe - VBE,P(FA) - Vo.1(0N)
= Vee - (:: + 1 )ViidFA) -
Vo(ON)
= Voa
V08
Following dashed path 4, Q 0 and Q5 both saturate
when
ViN
Element
Qp
DL
Oo
and
= Va£,o(SAT) + VaE.s(SAT) - Vcu(SAT)
= 2VBc(SAT) - Vu(SAT) = Vi11
TABLE 7.2
(1.6k)
= (5) - (0.7) (lk) - 2(0.7)
= 2.5 V
Viu = 2(0.8) - (0.2) = 1.4 V
Input High Voltage= Vrn
01
Os
TTL Voltage Transfer
Characteristic
VoL
= 0.2 V
States of Diodes and BJTs for Break-points
VoH
VB
VoL
Saturated
Cutoff
EOC
EOC
Cutoff
Saturated
Forward active
Forward active
EOC
Edge of conduction
Reverse active
Saturated
Cutoff
Cutoff
Saturated
7.6
HL Fan-Out
89
I'ILi
I'IL2
~~
N identical load gates
I'ILN
J_
FIGURE 7.5
7.6
TTL Inverter (Driving Identical TTL Inverters) in Output Low State
TTL FAN-OUT
As with DTL, the maximum fan-out for TTL is dependent on the output low state of the driver gate.
The maximum fan-out is again determined by how
rnuch current the driving gate can sink from multiple
(identical) load gates as depicted in Figure 7.5. Thus,
maximum fan-out is obtained from
1. Hence, this current is given by
Output Low Current = IoL
Since Di. is cutoff for the output low state, IoL is the
saturated collector current of Qu(SAT) and is given
by
lcn
Figure 7.6 shows the driving gate with one of the
output gates explicitly drawn. As usu.:t!, all parameters for the output gate are distinguished with a
prime to indicate which gate is under consideration.
In this circuit, Vm:T = v;N = Vm is used for the fanout analysis.
= Ic.o(SAT) = <Tcnf3r11w
where u 0 1. is the saturation parameter for Qu. Writing KCL at the base of Qu gives
IB,o
= l1c,s(SAT) - l1w
where
and also
Input Low Current = l 1L
The input current of a TTL gate is the emitter current
of QI· For the input low state (i.e. output high state),
QI is saturated and Q 5 is cutoff. Since lu = - 15,s,
Ic,I is essentially zero for the input low state. The
input low current is then just the current in R{i in
Figure 7.6 and 111 is found by following dashed path
IE.s(SAT)
=
IB,s
+ lc.s
The collector current Ic,s of Q 5 is found by following
dashed path 2 in Figure 7.6, where
Ic.s = lgc
Vee
Vu.s(SAT) - Vaw(SAT)
Re
90
Chapter ?/Transistor-Transistor Logic (TI'L)
Re
~
120n
: 1.6 kQ
z
'
Q,
Vm=VoH
.;.
I'IL2
I
f--I I'
IL,
L:____
driving gate (output low state)
Cascaded TTL Gates for Fan-out and Average Power Dissipation Calculations
FIGURE 7.6
The base current 18 ,s of Qs is
l/J,s
= lc,i(RA) = (1 + f3rJIB,1
= (1 + f31<)I1ui
where IRll is found by following dashed path 3 in
Figure 7.6, yielding
I
load gates (output high state)
where needed. For the output low state let f3F = 25,
f3R = 0.1, and u 0 L = 0.85. Also use VBdFA) =
VBdRA) = 0.7 V, V11 E(SAT) = 0.8 V, and VedSAT)
= 0.2 V.
Solution Substituting these values directly into the
derived equations yields
_ Vee - VHc,1(RA) - ViiE,s(SAT) - V8 E,o(SAT)
B,/ -
R/l
I
_ (5) - (0.8) - (0.2) _
(4k)
- 1 111A
IL -
The following example serves as an aid in understanding the equations of this section.
Example 7 .3
TTL Fan-Out
Calculate the fan-out for the standard TTL inverter
of Figure 7.5 considering the circuit of Figure 7.6
(0.8)
I1w
= (lk) = 800 µA
lc,s
=
(5) - (0.2) - (0.8)
.
(1. k)
=
2.5 mA
6
Il<B
=
(5) - (0.7) - 2(0.8) _
µA
(4k)
- 6 75
7.8
In,s = [1 + (0.1)](675µ.) = 743 µA
h.s = (743µ.) + (2.5111) = 3.24 111A
11w = (3.24111) - (800µ.) = 2.44 mA
IoL =
N
=
The average power dissipation for an inverter is now
obtained by substituting into
(0.85)(25)(2.44111) = 51.9 mA
( )
Prra~
(51.9m) = 51.9
(1111)
=
TTL POWER DISSIPATION
To determine the average power dissipation of a TTL
gate, we first obtain the sum of all currents being
supplied by Vee for both the output high [Icc(OH)]
and low [Icc(OL)] states. We then obtain the average
current supplied and multiply by Vcc- The values of
these currents are taken directly from the fan-out
analysis of the previous section.
Output High Current
Supplied = IcdOH)
2
rr
2
TTL Power Dissipation
Calculate the power dissipation of the standard TTL
inverter of Figure 7.5.
Solution Direct substitution of the values calculated in Example 7.3 yields
Pee (avg)
=
=
7 .8
For the output high state [the input is low with V1N
= VcE(SAT) ], considering Figure 7.6, we have
Iee(OH) + Iec(OL) V
l1w(OH) + l1w(OL) + 11,e(OL)
= - - - - - - - - - - - Vee
Example 7.4
Iec(OH)
91
Average Power Dissipation= Pcdavg)
Hence, the maximum fan-out of this TTL gate is 51.
Also note that the value if Ill,o = IE,s = 2.44 mA is
sufficient to saturate Q0 .
7.7
Open-Collector TfL
(1111)
+ (675µ.) + (2.5m) ( )
2
5
10.4 mW
OPEN-COLLECTOR TTL
Many of the TTL family logic gates are available with
open-collector outputs. These gates do not include
= 11,ll(OH)
Vee - VBE,i(SAT) - V0 ,o(SAT)
RR
Output Low Current
Supplied == IcdOL)
1.6 k.Q
For the output low state (the input is high), considering Figure 7.6, we have
Q,
Your
and
and IRcP = 0 because QI' is cutoff for the output low
case. Hence,
FIGURE 7.7
Open-collector TTL Gate
92
Chapter ?/Transistor-Transistor Logic (TTL)
the output-high pull-up driver made up of Qp, DL
and Rep shown in Figure 7.3. Figure 7.7 shows a
5400/7400 series open-collector TIL gate. These
gates are indicated in data sheets by specifying
"open-collector" or "OC".
Open-collector TIL gates are often used in data
busses where multiple gate outputs must be ANDed.
This can be accomplished by using a single pull-up
resistor with open-collector TIL gates. This type of
connection is referred to as a wired-AND because the
output is high only when Q0 of all wired gates are
cutoff.
7.9
LOW POWER TTL (LTTL)
To decrease the power dissipated in TTL logic gates,
the resistor magnitudes must be increased. With increased resistances, less current conducts in the gate
and the Ice X Vcc product is decreased. Figure 7.8
shows the 54L00/74L00 low power TIL (LTIL) with
increased resistances. As can be seen, the resistors
are approximately one order of magnitude larger
than those for the 5400/7400 standard TIL gate of
Figure 7.3.
However, along with lower power dissipation,
there are a few unfortunate disadvantages:
1.
decreased fan-out
2.
longer transient response times
These result from decreased currents which sink load
gate input currents and charge load capacitances.
Thus, a tradeoff exists between lower power dissipation and transient response.
Example 7.5 Power Dissipation Comparison
of TTL and LTTL
Compare the power dissipation for LTIL in Figure
7.8 with that of TIL found in Example 7.4. Use the
BJT terminal voltages of Example 7.4.
Solution
Using the equations of sections 7.6 and
7.7 and the LTTL circuit, we have
(5) - (0. 7) - 2(0.8)
(40k)
(5) - (0.2) - (0.8)
(20k)
I
RB
Re
= 675 µA
= 200
µA
(OH) = (5) - (0.8) - (0.2) = 100 .. Ll
(40k)
f-'4'
and
20k.Q
p
(
) _ (67.5µ,)
cc avg -
+
(200µ,)
2
+
(100µ,) ( )
5
= 919 µ,W
Q,
Your
Comparing with Example 7.4, we see that the power
dissipation for the LTIL gate is about one tenth of
that for TIL.
7.10
FIGURE 7.8 54L00/74L00 Low Power TTL (LTTL)
with Increased Resistances
HIGH SPEED TTL (HTTL)
As mentioned in the previous section, a decrease in
power dissipation is accompanied by a reduction in
speed. This suggests that the transient response of
TIL might be improved by decreasing resistance values and increasing the power dissipation. This is in
fact the case and prompted the development of
7.11
·+8k<l
93
high-speed TTL (HTTL). Figure 7.9 shows the
54H00/74H00 series high speed TTL (HTIL). In addition to the decreased resistances, the output-high
driver section includes a Darlington pair configuration, Qp and Qp 2, in place of the single BJT Qr used
in TTL. This allows more current to be sourced for
charging of the load capacitance. REP is included as
a discharge path for Qp 2 .
158 .n
Rep
TTL SPICE Simulation
760.Q
I
~-~-
VIN
I
I
I
7.11
YoUT
-0
Dc2S
TTL SPICE SIMULATION
Figure 7.10 shows a standard 5400/7400 TTL inverter
with appropriate SPICE labelings. The SPICE input
CIRcuit file that represents this circuit is as follows:
I
I
470.Q
Standard 5400/7400 TTL
Inverter
VCC 3 D DC 5V
VIN 1 0 PULSE(OV 5V OS 2NS 2NS
+ SONS 100NS)
RB 3 2 4KOHM
RC 3 4 1-6K◊HM
RCP 3 6 1200HM
I
I
'-----------~------~
-:-
FIGURE 7.9 54H00/74H00 High Speed TTL (HTTL)
with Smaller Resistances and Darlington Pair Output
High Driver
~
3
4 KOHM
RC
®-
VIN
1
0.
QI
9
DP
5
8
io
*
--0 YoUT
8
DC
5
0
5
Standard TTL Inverter with SPICE Labelings
QO
0
0
FIGURE 7.10
1200HM
6
4
PULSE
n-
RCP
1.6KOHM
4
2
n
f
3
94
Chapter 7 /Transistor-Transistor Logic (TTL)
RD 5 D 1KOHM
DP 7 8 DIODE
DC D 1 DIODE
-MODEL DIODE D(CJ0=-5PF)
QI 9 2 1 QNPN
QS 4 9 5 QNPN
QP 6 4 7 QNPN
QO 8 5 D QNPN
-MODEL QNPN NPN(BF=10 □ VA=80
+ IS=1E-14A VA=80 RB=1DOHM
+ RC=20HM CJC=2PF CJE=4PF)
-DC VIN DV 5V □ -1V
-PLOT DC V(8)
-TRAN 1NS 125NS
-PLOT TRAN V(1) V(8)
-END
The VIC and transient response obtained from simulating this circuit are shown in Figures 7.lla and b.
In order to carry out SPICE modelling of multiemitter BJTs, each emitter is regarded as a separate
BJT with all common collectors numbered the same
and all comm.on bases numbered the same. Homevvork Problern 7.17 discusses the rnodification of the
preceding SPICE input CIRcuit file to simulate a two
input 111, NAND gate.
VIN(V)
•
5
4
VOUT (V)
t
3-
5
2
-
1
4
t(ns)
0 -,-
0
3
25
50
75
100
125
YourCV)
...
i
2
5
4
1
3 -
I
o
I
0
I
1
► VIN(V)
2
3
4
2
5
0 -I 0
(a)
FIGURE 7.11 Results of Section 7.11 TTL SPICE
Simulation: (a) Voltage transfer characteristic from .DC
-
25
-------+~ --t 50
75
iOO
►
t(ns)
i25
(b)
sweep, (b) Transient response from .TRAN sweep
Chapter 7 Problems
95
CHAPTER 7 PROBLEMS
7.1
7.2
For the basic TTL inverter of Figure P7.1, determine
11:-.:, I1rn, ls.o and IRc for the following conditions:
(a) V 1N = 0 V
(b) V1N = 3 V
Let /3r- = 100, f3R = 0.05, Vm(FA) = Vnc(RA) = 0.7
V, V1nc(SAT) = 0.8 V, and Vc 1 (SAT) = 0.2 V for the
BJTs.
4kQ
Repeat Problem 7.1 for
(a) Rn= 1 kfl
(b) Rn = 5 kfl
VINA
0----1
V !NB
7.3
'
Q
0
with all other parameters unchanged.
Repeat Problem 7.1 for
(a) Re= 500 fl
(b) Re= 3 kfl
with all other parameters unchanged.
7.4
For the basic TTL inverter of Figure P7.1 with Vee
= 5 V, determine 11N, IRB, IB,o and IRc for the following conditions:
(a)
V1['; = 0 V
= 5V
(b) V 1[';
Let /3 1• = 100, VBE(FA) = Vnc(RA) = 0.7V, VBdSAT)
= 0.8 V, and VuJSAT) = 0.2 V for the BJTs.
FIGURE P7.6
7.7
For the TTL NAND gate of Figure P7.6, assume Q0
and Qp saturate at the same time as Q 0 switches
from saturation to cutoff. Determine the current in
Ru, and Vny, VEY and Vey, What is the operating
state of Q5 7 Let /3r = 100, VnE(FA) = V1ic(RA) =
0.7 V, VniJSAT) = 0.8 V, and Vc 1 (SAT) = 0.2 V for
the BJTs.
7.8
For the standard TTL NAND gate of Figure P7.6,
find the low and high noise margins. Let f3F = 75,
V8 E(FA) = 0.7 V, VBl(SAT) = 0.75 V, and VcE(SAT)
= 0.1 V for the BJTs.
7.9
For the standard TTL NAND gate of Figure P7.6,
calculate the following:
(a) the input low current In.
(b) the output low current IoL
(c) the maximum fan-out= N = I0 L/In.
(d) the average power dissipation
Use /3 1 = 70, f3R = 0.05, V81 (FA) = 0.7 V, V8E(SAT)
= 0.75 V, Vllc(RA) = 0.7 V, and Vu(SAT) = 0.15 V.
Use cr0 = 0.8 for the output low state.
7.10
Repeat Problem 7.9 for
7.11
For the low power TTL inverter of Figure P7. l 1, obtain the following:
(a) Sketch the VTC.
(b) Calculate the maximum fan-out = N = IllL/IIL·
FIGURE P7.1
7.5
7.6
Determine the VTC for the basic TTL inverter of Figure P7.1. Let /3r = 100, V81:(FA) = 0.7 V, V8 c(RA) =
0.7 V, Vllr-(SAT) = 0.8 V, and Vn(SAT) = 0.2 V for
the BJTs. Also, determine the high and low noise
margins.
For the standard TTL NANO gate of Figure P7.6,
determine the currents Ill.I' and Ic, 1, for Q 0 and Qs
operating in saturation. What is the operating state
of Qp?
/3 1 = 80 and cr0 = 0.7.
96
Chapter 7/Transistor-Transistor Logic (TTL)
(c) Calculate the average power dissipation.
Use f3F = 90, /3 1( = (l.05, V!lr(FA) = V1K(RA) = 0.7
V, Vll 1o(SA T) = 0.8 V, and Vc 1 (SAT) = 0.2 V. Use ffo
= 0.85 for the output low state.
Ra,
7.13
For the standard TTL NANO gate of Figure P7.6,
determine the state of the BJTs and the diode for
(a) the output high state
(b) the output low state
7.14
For the standard TTL NANO gate of Figure P7.6, list
the elements that make up
(a) the input stage
(b) the drive splitter
(c) the output high driver
(d) the output low driver
Refer to the TTL super-circuitry block diagram in
Figure 4. 9 of section 1.3.
7.15
For the standard TTL NANO gate of Figure P7.6, list
the purpose of all BJTs, diodes, and resistors.
7.16
Show that Qp in Figure P7.6 is cutoff for the output
low state by finding VBEY in terms of terminal voltages of Qs, Q 0 , and D 1,.
7.17
In order to simulate a TTL NANO gate in SPICE,
separate BJTs must be used for each input, since
SPICE does not support a multi-emitter BJT. Verify
the NANO operation by adding the following lines
to the SPICE listing given in section 7.11:
5000
Your
Qo
Q12 9 2 10 QNPN
VIN2 10 D DC SV PULSEC □ V SV OS
+ 2NS 2NS 1DDNS 2DDNS)
-=FIGURE P7.11
7.12
For the "special" TTL inverter of Figure P7.12, let
f3F = 100, Vlll-:(FA) = 0.7 V, vllE(SAT) = 0.8 V, and
Vu,(SAT) = 0.1 V. Obtain the following:
(a) Sketch the VTC.
(b) Determine the average power dissipation.
VIN o------f
Q.
()_
The schematic for this double BJT Q1 is shown in
Figure P7.17. Note the default DC value of 5 V for
VIN2. This allows the .DC sweep of VINl to provide both output states (if VIN2 were held to the
default DC value of O V, the output would remain
high for the entire .DC sweep).
7.18
Find the VTC for the high speed HTTL inverter (V1i':,\
= V1:--m) of Figure P7.18. Use /3F = 70, Vm(FA) =
V1ic(RA) = 0.7 V, VBE(SAT) = 0.8 V, and Vn(SAT)
= 0.2 V for the BJTs.
7.19
For the HITL inverter (V1:-,;,\ = V,:--:K) of Figure P7.18,
find the following:
(a) the input low current I,L
(b) the output low current Im
(c) the maximum fan-out= N = I0 1.II,L
(d) the average power dissipation (for the inverter)
Use /3 1. = 70, f3R = 0.05, VRl(FA) = V11c(l<A) = 0.7
V, VB 1 (SAT) = 0.8 V, and V0 c(SAT) = 0.2 V. Use a 0
= 0.8 for the output low state.
7.20
Repeat Problem 7.19 for f3 F
7.21
Modify the SPICE listing given in section 7.11 to
simulate the low-power TTL inverter of Figure
P7.11.
7.22
Modify the SPICE listing given in section 7.11 to
simulate the high speed HTTL inverter of Figure
P7.18.
- 0 'lour
'<..I
Qo
Ro
1 kO
L FIGURE P7.12
i_l
= 80.
Chapter 7 Problems
7.23
Show that Qp:2 of the HTIL gate in Figure P7.18 can
not saturate for either the low or high output state.
7.24
For the HTIL NANO gate of Figure P7.18, determine the state of the BJTs for
(a) the output high state
(b) the output low state
58 Q
For the HTIL NANO gate of Figure P7.18, list the
elements that make up
(a) the input stage
(b) the drive splitter
(c) the output high driver
(d) the output low driver
Refer to the TTL super-circuitry block diagram in
Figure 4.9 of section 4.3.
7.26 For the HTIL NANO gate of Figure P7.18, list the
purpose of all BJTs, diodes, and resistors.
7.25
Your
-::-
FIGURE P7.18
97
8
SCHOTTKY
TRANSISTORTRANSISTOR
LOGIC [STTL]
In 1970, Schottky transistor-transistor logic (STIL) was
introduced . 111is logic family is obtained by replacing
the BJTs with Schottky-clamped BJTs (SBJTs). Furthermore, in 1975, a low power STIL (LSTIL) was
first manufactured. To achieve the reduced power
dissipation, the circuit resistor values are increased.
However, as with TTL, increased resistor values produce increased propagation delay times and decrease
fan-out capabilities.
The primary advantage of using Schottkyclamped BJTs is their improved transient times. Since
the Schottky-clamped BJTs cannot operate in saturation, the switching speeds and associated time
delays are considerably shortened . We begin this
chapter with a review of Schottky diodes and
Schottky-clamped BJTs.
8.1
diode. The circuit symbo l for the MN SBD is shown
in Figure 8.16 and the current-voltage characteristic
is simi lar to that of a PN-junction diode, as observed
in Figure 8.lc for an AI-NSi diode. The important
difference is that Schottky- barrier diodes using sili con as the semiconductor have a larger forward current for a smaller fotward voltage. This results in a
turn-on voltage that is smaller than that of the PN
silicon diod e. A typical va lue for a Silicon MN diode
is
VsRo (ON)
= 0.3 V
as indicated in Figure 8.lc.
8.2
SCHOTTKY-CLAMPED BJTs
A serious problem that severely limits th e switching
speed of a BJT inverter (and the TTL gates of the
previous chapter) is the amount of time required to
remove th e e normous stored charge from the base
of a saturated BJT. Thus, an obvious solution to this
problem is to use BJTs that do not, or cannot, saturate. Since the saturation mode of operation for a BJT
is characterized by a forward biased base - collector
voltage of
SCHOTTKY-BARRIER DIODES
A Schottky-ba rrier diode (SBD) is a metal -semiconductor (usually MN) rectifying junction . This device
is made up of adjoining metal and N - type semiconductor regions (usually aluminum with N-type silicon) as shown in Figure 8.1a . The MN SBD differs
from an ohmic contact in that a barrier to electron
flow exists at the MN junction. As in the case of a
PN diode this barrier is reduced on ly by applying a
forward voltage. For the MN diode, a fotward voltage
is positive on M relative to N. This polarity of voltage
reduces the barrier to electron flow from N to M and
depending upon the magnitude of the voltage may
correspond to a large current from M to N. Hence, a
simple way to view this device is that the metal M
region rep laces the P-type region of a PN-junction
V1ic(SAT) = V8 F.(SAT) - VcE(SAT)
= 0.8 - 0.2 = 0.6 V
the saturation region can be avoided by limiting the
forward-biased base-collector voltage to values less
than 0.6 V. This is accomp lished by placing a SBD
across the base and collector terminals of a B)T as in
Figure 8.2a. Note the defined positive currents in this
diagram . Now, as the input current is increased, the
98
8.2
ISBD
Schottky-Clamped BJTs
99
(mA)
t
(a)
cutoff
. __ _
_ _ __,__ _ _ _ _ _ _----J>-
Vseo(V)
VsaoCON) = 0.3
(b)
(c)
FIGURE 8.1
characteristic
Schottky Barrier Si MN Diode: (a) MN representation, (b) Circuit symbol, (c) Current-voltage I-V
SBD will begin to conduct at VsBo(ON) = 0.3 V.
Hence, the base-collector junction reaches the forward-bias of VBc = 0.3 V. Any further increase in
current 1[1 entering this configuration will be diverted
from the base of the BJT, through the SBD, and in
turn into the collector of the BJT. Thus, V8 c is limited
to V51 m(ON) = V8 c(HARD) = 0.3 V. This BJT-SBD
combination is called a Schottky-clamped BJT (SBJT)
or Schottky transistor and the BJT cannot operate in
saturation. Hence, the time consuming saturation
stored-charge removal (and insertion) for the base is
eliminated.
The circuit symbol for an SBJT is shown in Figure
8.2b, where the positive terminal currents are also
indicated (compare this with Figure 8.2a). The advantage of the decreased switching time of the SBJT
!
!
I'c
I'
J:_~1,
r:-)
I'c
?
I'B
...............
0-
0
l'·
t·
(a)
FIGURE 8.2
Schottky-clamped BJT: (a) Equivalent circuit, (b) Circuit symbol
r
(b)
100
Chapter 8/Schottky Transistor-Transistor Logic (STTL)
is essentially accomplished with no additional fabrication. The only difference between the SBJT and
the regular BJT is that the base region metal contact
is extended to overlap part of the collector N- region.
Hence, the MN-junction appearing between the
base and collector terminals is simply the base metal
in contact with the collector N-region.
of Vnc:(RA) = 0.7 V which is necessary to enter the
reverse-active mode of operation. However, with the
base-collector junction forward biased to 0.3 V, a
current can still flow through the SBD, even with the
BJT cutoff. In this textbook, this situation shall be
referred to as the reverse Schottky mode:
VBE
< Vm,(FA), V8 c(RS)
The mode of operation where the BJT is forward active and the Schottky diode is conducting is referred
to as the "on-hard" mode. This mode is similar to
saturation with V llE increased to 0.8 V, except Vile is
only forward biased to 0.3 V. The terminal voltages
and currents of an SBJT in the on-hard mode of operation are thus labeled in Figure 8.3a. Note that the
collector current of the BJT is still given by (see Figure
8.2a)
= IE
= f3Fla - Is1io
Note that the BJT does not saturate and u
Example 8.1 Schottky-Clamped BJT Inverter
Logic Swing
Determine the logic swing of the SBJT inverter of
Figure 8.4a.
Solution (Output High Voltage) The output high
voltage occurs when the input is low and insufficient
to turn on the Q 51m, With the SBJT cutoff, IRe
Ic(OFF) = 0 and
VouT = Vee - IcRc = Vee= 5 V
and the total collector terminal current is
= 1.
Reverse Schottky Mode
With the base-collector junction of a SBJT limited to
a forward-bias of Vllc(HARD) = Vs1m(ON) = 0.3 V,
an SBJT cannot operate in the reverse-active mode of operation. This is clear since VBc: cannot reach the value
(a)
= Von
Solution (Output Low Voltage) As the input
voltage increases, the output voltage decreases to the
minimum value. This is the on-hard collector-emitter voltage, where
VouT(min)
= Vu(HARD) =
0.5 V
= VOL
Solution (Logic Swing) The VTC is indicated in
Figure 8.46 and the logic swing is therefore
LS = V 011
-
VoL = (5) - (0.5)
=
I'8
FIGURE 8.3
= le
= 0, I~ = - I~ = IsoD
On-Hard Mode
[~(HARD)
= 0.3 V, Ifl
(b)
Schottky Barrier Bf[ Modes of Operation: (a) "On hard" mode, (b) Reverse Schottky mode
4.5 V
8.3
YourCV)
VOH = Vcc
Schottky-Clamped TTL (STTL)
101
edge of conduction
Q(OFF)
=5V
Vts=4.5 V
Your
Schottky clamped BIT
enters on hard mode
Q(HARD)
VoL = VciHARD)
= o.sv
(a)
FIGURE 8.4
f
Example 8.1: (a) Schottky clamped BJT inverter, (b) Voltage transfer characteristic
Tips, Tricks, and Gimmicks
Schottky-Clamped BJTs
Similar to bipolar logic gates of previous chapters, knowing the state of Schottky-barrier diodes and associated Schottky-clamped BJTs,
the circuit is easily analyzed. The equations
governing the operation of Schottky-barrier diodes and Schottky-clamped BJTs will be
needed in this chapter and are listed as follows:
Schottky barrier diode conducting: VsBD(ON)
= 0.3 V
F01ward active: VriE(FA) = 0.7 V and Ic(FA)
= f3FIB
On Hard: VBE(HARD) = 0.8 V, VridHARD)
= 0.3 V, Vc1:(HARD) = 0.5 V, and
Ic(HARD) = f3Fill
Reverse Schottky mode: V8 c(RS) = 0.3 V,
I[i = - Ic(RS) = IssD, IE = 0
The output low voltage is higher than VcE(SAT) and
results in a slightly reduced logic swing. This disadvantage is quite minor in comparison with the speed
improvement achieved using Schottky-clamped BJTs
in bipolar logic circuits.
8.3 SCHOTTKY-CLAMPED
TTL (STTL)
The basic 54S00/74S00 STTL gate is displayed in Figure 8.5. Note that all of the BJTs (with the exception
of Qp 2) have been replaced with SBJTs and the input
clamp diodes have been replaced with SBDs. In addition, DL has been replaced with Qp 2 which, along
with Qp, make up a Darlington pair operating as an
emitter-follower. This arrangement provides more
source current to charge the load capacitance when
the driver output is switched low-to-high, thus reducing the transition time. Note also that the 1.4 V
voltage drop between the collector of Q5 and the
output terminal has been preserved. When Qp and
Qp 2 are on, the collector-emitter voltage of Qp 2 has
a minimum value of
VC£,p 2 (FA) = V 8 E.P2(FA) + VcE.P(HARD)
> VcE(SAT)
and Qp 2 therefore cannot saturate. Hence the use of
a non-Schottky-clamped BJT for QP2·
The inclusion of QD and biasing resistors R8D
and Rrn contributes several advantages. First, for a
low input voltage, no current flows through R8 D and
Rrn. Then, as the input voltage is increased, QD and
Q0 must turn on at the same time. As a result, Q 5
102
Chapter 8/Schottky Transistor-Transistor Logic (STfL)
son
VINA'~~~
Q
---2-'----- --------- ---2---
VINB
0-
l
I
!
I
DcA
~
l..
FIGURE 8.5
Schottky TTL 54S00/74S00 Series NAND Gate
does not have the alternate conduction path it had
in TTL through the pull-down resistor R 0 when Q 0
is off. This eliminates the additional breakpoint between V0 H and V0 L present in TTL. Consequently,
Q 0 is sometimes referred to as a squaring transistor.
Additionally, a narrower transition width and improved noise margins are achieved using Q0 . The
values of R1m and R0 J are chosen to ensure that most
of lc,s goes to 113,0 and provides ample base driving
current to Q0 .
The current to just turn off Q0 is given by
- IH,o
=
ln,c
+
Ic,o
= (1 + f3r)IH,D
(the negative 18 , 0 indicates the current is out of the
base). Therefore, QD also provides active pull-down
of Q0 during the output low-to-high transition. This
amounts to an additional improvement in speed for
STfL. Indeed, the STTL gate has a propagation delay
time of approximately 2 ns, as compared to the 10 ns
propagation delay time of non-Schottky-clamped
TfL logic gates.
A final comment should be made on the values
of Rio and Re. They are about half of the corresponding values in TTL and therefore carry twice the current. This results in increased fan-out but also in-
creases the power requirement necessary to operate
STTL.
The purpose of each element in a series 54S00/
74S00 standard STTL gate of Figure 8.5 is sum.marized in Table 8,1, The states of each BJT for the output high and low logic levels arc tabulated in Table
8.2.
Example 8.2 STTL Voltage
Transfer Characteristic
Determine the VIC of the STTL gate in Figure 8.5
with V 1:--.:A = ViNll and verify that Qp is on for both
the output high and low states.
Solution (Output High Voltage) For V1N low, Q 0 ,
Q 0 and Qs are off, while Qp and Qp 2 are both on.
The output high voltage is then found by following
dashed path 1 in Figure 8.5 yielding
Vo11 = Vcc - VBE,/'(FA) - Vin:,r2(FA)
(5) - 2(0. 7) = 3.6 V
where V1w is zero because IRc(OH)
gible,
= IB,P is negli-
8.3
TABLE 8.1 Purpose of Each Element for a
Series 54S00/74S00 Standard STTL Gate
Element
Q,
RB
Qs
Re
Qp & Qp 2
Ru,
Ru,
QD
R,m & Rrn
Q0
Dc 1 & De
Purpose
Multi-emitter input SBJT, base-collector
level shifting of transition width, pulldown of Qs
Limits In.
Drive splitter, provides base driving current
to Q0 , base-emitter level shifting for
shift of transition width, pull-down
of Q"
Along with Qs provides logic inversion to
output-high driver
Active Darlington configuration currentsourcing pull-up, base-emitter levelshifting between Vee and output
Part of active pull-up and limits current
spikes during output high-to-low
transition
Provides discharge path for the base of Qp 2
Active pull-down of Q 0 , removes
breakpoint between V011 and Vol
Values ensure that most of Ic,s is provided
as base driving current to Q0
Output inverting BJT, output low driver for
current sourcing pull-down
Input clamping diodes to limit the negative
swing of the inputs to one SBD diode
drop below ground
Schottky-Clamped Tl'L (STfL)
103
Solution (Output Low Voltage) Since Qu is a
Schottky-clamped BJT, it does not reach saturation
and V0 1. is higher for STTL than TfL. The limiting
low value is
VOL = VcE,o(HARD) = 0.5 V
Solution (Input High Voltage) Following dashed
path 2 in Figure 8.5, considering the output low state,
the input high voltage is
vi//
= VBE,o(HARD) +
VaE,s(HARD) - Vee/HARD)
(0.5) = 1.1 V
= 2(0,8) -
The resulting VTC is displayed in Figure 8,6 and verifies the logical NOT function.
To verify that Qp is in active operation for the
output low state, solve for VB,r following dashed path
3 in Figure 8.5 yielding
VB,P
= VBE,o(HARD) + VcE,s(HARD)
(0.8) + (0.5) = 1.3 V
This will turn on Qr because its emitter is connected
to ground through REP· Qp is also on for the output
high state because with Qs cutoff, Vcc is applied to
the base of Qp through Re. Thus, Qp is on for both
states,
Solution (Input Low Voltage) Following dashed
path 2 in Figure 8.5, for the output high state, the
input voltage necessary to just turn on the output
inverting transistor Q0 is
V11 = ViiE,o(FA) + Viic,s(FA) ~ VcE,1(HARD)
3 .
= 2(0.7) - (0.5) = 0.9 V
2
TABLE 8.2 BJT States for Output High and
Low Logic Levels for a Series 54S00/74S00
Standard STTL Gate
Transistor
VoH
Vol
Q,
Qs
Qp
On hard
Cutoff
Edge of conduction
Edge of conduction
Cutoff
Cutoff
Reverse
On hard
Forward active
Cutoff
On hard
On hard
Qp2
QD
Qo
V0 L=0,5·------- _.,__- - - - - - - - - 2
3
4
5 Ym(V)
VIL=0.91
Vrn=l.1
FIGURE 8.6 STTL 54S00/74S00 Inverter Voltage
Transfer Characteristic (Example 8,2)
104
8.4
Chapter 8/Schottky Transistor-Transistor Logic (STTL)
Follmving dashed path 2 in Figure 8.7, the current
through Rll is
STTL FAN-OUT
The fan-out analysis of the STTL gate shown in Figure 8.5 is analogous to that of the non-Schottky TTL
of the previous chapter. Two cascaded STTL gates
connected as inverters are shown in Figure 8.7 with
the load gate components labeled with primes, as
usual. The driver gate is in the output low state and
the load gates are in the output high state. The fanout is dependent on how much current the driver
gate can sink from the load during the low output
state of the driving gate or
N = Im
I,L
Fan-out is not dependent upon the driving gate's
output high state because each Q1for the load gates
is in the reverse Schottky mode and 1111 = I~(IH) =
0 for each.
Input Low Current
As discussed in the previous chapter, the input
low current is l 1L = I~, 1(IL) = I~, 1 since Ic, 1(IL) =
-I 13, 5 (0FF). The input low current is found by following dashed path 1 in Figure 8. 7 yielding
_ Vee - VHc,,(RS) - VaE.s(HARD) - Viir,o(HARD)
Ru
Neglecting IB,I' and following dashed path 3 in Figure
8. 7, the current through Re is
I
These expressions yield the magnitudes of currents
for STTL and, as with DTL and TTL, are best indicated by example.
Example 8.3 STTL Fun-Out
Calculate the maximum fan-out for the STTL gate of
Figure 8.5 considering the circuit of Figure 8.7. Let
f3c = 49 for the BJTs.
Solution Substituting these values directly into the
derived equations yields
In =
V~e - V~u(HARD) - VeE,o(HARD)
l11 =
_ Vee - VcE,s(HARD) - V8 u1(HARD)
Re
RC -
J,_-_
R~
0
I
Output Low Current
(5) - (0.8) - (0.5)
(2_8k)
= 1.32 111A
= (0. 8) - (0.5) - 1 20 mA
(250)
-
.
_ (5) - (0.3) - 2(0.8) _
(2.8k)
- 1.11
R/l -
The output low current
I RC
_ (5) - (0.5) - (0.8) _
(
)
- 4.11
900
-
111A
A
111
1£.s = 1.llm + 4.11111 = 5.22 mA
18 ,0 = (5.22111) - (1.20111) = 4.02 nzA
Io, = 49(4.02111) = 197 mA
is found by analyzing the driving gate circuit in Figure 8.7. Note that the collector current of Q0 is
f3Flll,o, neglecting lsllD· Further, the base current of
Q0 , 113,o, is found by writing KCL at the base of Q0
and ignoring IA,D to obtain
N
= (l 97m) = 149.2
(1.32m)
Hence, the maximum fan-out is 149.
la,o = h,s - lc,o
The collector current of Q0 is given by
lc,o
= IRc,o =
VaE,o(HARD) - VeE,o(HARD)
R
8.5
STTL POWER DISSIPATION
e,D
The emitter current of Q5 , IE,s is given by
lcs
= Ia.s + lc,s =
IRB
+ IRe
To determine the average power dissipation of an
STTL inverter, we again average the sum of all current being supplied by Vcc for both the output high
V'ee =5 V
.
f
,1
.- ,---- Vee= 5 V
? ' C)
-2--____
R
.8 ill
/ ',\
r Q \ ___
VIN=VoH
i--
0
.
I
-· ·- _F'/ ~
.!
]~
•~
2 _
--
.--1111!=.::..:z-,
-~-ti---~~--,
,
f 2sop
I
i
~
I
~~
(bz
~-
ill
J......
1
e
I,,L
Qoj
,,
I
kQ
'
RJ 900"
_,
Rao
500 Q
j
/
-
'. [
R',,
<soon
~y·
V'oH
2son
I' ll.2
: :
:
/
T ~-
R~
~Q'o
I
''
~
, Sjso"
;/
rt-R~~,tn r:··
ir/ [Q',
Rco
De
3 ,
.
.
.
, · 4
2,,
'
I
I
I
I'!Lo
1
,I
\..___
driving gate (output low state)
FIGURE 8.7
(Q·>
I
l v~:v·•
--
-=- --------.
··---4---
i
~//
· , "".f'
: r·:_
(.JI
J,....
,.-4--
f
• 2.8
I'n,,-- 1 ~
·--- ---~!son
it""' ____
Re
p
2
R'
.s_]
-'
r
Cascaded SITL Gates for Fan-out and Power Dissipation Analyses
y/
load gates (output high state)
______ .,/;'
106
Chapter 8/Schottky Transistor-Transistor Logic (STTL)
and low logic states. This analysis is slightly more
complicated than that for TfL because Qp is on for
both cases. Notice that most of the current expressions were obtained in the fan-out analysis of the
previous section.
ligible and from Figure 8. 7, we have
I 1,c(OH)
Vee - V8 E,P(FA)
REP
Average Power Dissipation= Pcdavg)
Output Low Current
Supplied = IcdOL)
Finally, the average power dissipation is given by
p
For the output low state, we have already found
lpc(OL)
=
Vee - VeE(HARD) - V8 E(HARD)
Re
Furthermore, IRcP(OL) is equal to the collector current of Qp, since Qr 2 is cutoff. Assuming the base
current of Qp negligible, IRcP = Iu. Then realizing
that
I 8y(OL) + Im,(OL)
=
lr,P
and following dashed path 4 in Figure 8.7 yields
Vlll:, 0 (HARD
+ Vu, 5 (HARD) - V8 E,P(FA)
REI'
Example 8.4
Output High Current
Supplied = IcdOH)
For the output high state, we found in the previous
section
IccCOL) + lcc(OH)
Vee
2
STTL Power Dissipation
Calculate the average power dissipation of the STTL
inverter corresponding to Figure 8.5. Let f3F = 49 for
the BJT as in Example 8.3.
Solution Substituting the values into the expressions derived in section 8.5 yields
I
u
(OL) _ (0.8)
-
I,vi(OL) =
Vee - V1ic,,(RS) - VaE,s(HARD) - V1ll.o(HARD)
Not that as discussed in section 8.2, Q, is in the reverse Schottky state where a current flows only
through the SBD and the BJT portion of the SBJT is
cutoff.
)
and
=
R/l
(
cc avg =
where
Finally, I1dOL) is. found by following dashed path 2
of Figure 8.7:
I1rn(OL)
+ I,u(OH) = IE,P(OH)
+ (0.5) - (0. 7) _ 182
(3.3k)
µ.A
(5) - (0.3) - 2(0.8)
( _ k)
= 1.11 mA
28
and
lpc(OH)
+ IRCl'(OH) = h:.,,(OH)
=
(5) - (0. 7)
(3.3k)
=
l. 3 111 /\
From Example 8.3, we have IRc(OL) = 4.11 mA and
IRti(OH) = 1.32 mA. This gives
lec(OL) = (1.11111)
+ (4.llm) + (182µ,)
= 5.40 111A
and
Iec(OH) = (1.32111) + (1.3111) = 2.62 mA
Thus, the average power dissipated for STTL is
In determining the remaining current supplied, note
that IRc(OH) = I8 y and IRcr(OH) = Icy- Since I8 ,I' is
small and Q5 is cutoff, the voltage across Re is neg-
Pee (avg)
=
(5.40111)
+ (2.62111) ( )
2
= 20.05 mW
5
8.6
Note this is almost twice the power required for the
TTL gate of Example 7.4.
8.6
LOW-POWER STTL (LSTTL)
As mentioned in the previous sections, the increased
fan-out and superior transient response for STTL is
accompanied by a larger power requirement. Example 8.4 showed the STTL average power dissipation to be almost twice that of TTL. This prompted
the development of a low power Schottky-clamped
TTL (LSTTL) circuit. Figure 8.8 displays the 54LS00/
74LS00 series LSTTL gate in its two-input NAND
form.
Larger Resistors
The LSTTL resistor values are approximately ten
times the STTL values. Hence only one tenth the
current flows through these and approximately one
tenth the power is dissipated. However, fan-out is
also reduced and the propagation delay time is increased for this reduction in power dissipation.
Low-Power STTL (LSTTL)
Diode Input Section
In addition to the change in resistor values, other
improvements are included in the LSTTL circuit. The
original intention of the multi-emitter input transistor Q 1 was to aid in stored charge removal from the
base of Q5 . Since the SBJTs being utilized do not
saturate, this is no longer necessary. Thus a return to
a diode (Schottky) input. The Schottky input diodes
require about one third of the silicon surface area of
a multi-emitter transistor. Therefore, using diodes in
place of the input SBJT has the advantage of reduced
parasitic (input) capacitance. The connecting of REP
to the output terminal (instead of ground as in the
STTL circuit) allows Qp to begin charging the load
capacitance before Qp 2 is on and therefore speeds up
the low-to-high transition switching.
Pull-Down Enhancements
Diodes DDl and DD 2 are included to further enhance
the transient properties. DD 1 allows Qp 2 to discharge
through the collector of Qs when the output goes
Yee= 5 V
Re.
R.
120n
20 kn
DIA
VINA
Q,
C
VINB
Dm
----0 Your
Ra,
3 kn
1.5 kn
Q,,
FIGURE 8.8
107
Low-power Schottky LSTTL 54LS00/74LS00 Series NAND Gate
108
Chapter 8/Schottky Transistor-Transistor Logic (SITL)
TABLE 8.3 Purpose of Each Element
for 54LS00/74LS00 Series LSTTL Gate
Element
low. DD 2 provides for additional pull-down of the
output.
Purpose
Diode input ANDing and level shifting
Limits I,L
Drive splitter, provides base driving current
to Q0 , base-emitter level shifting for
shift of transition width, pull-down of
Q" and Q,, 2
Along with Q5 provides logic inversion to
output-high driver
Active Darlington configuration providing
current-sourcing pull-up and baseemitter level-shifting between Vee and
output
Part of active pull-up and limits current
spikes during output high-to-low
transition
Gives emitter of Qp a direct path to output
and allows charging of load capacitance
before Q,, 2 turns on
Allows Q,, 2 to discharge through collector
of Q 5
Provides additional pull-down of output
Provides active pull-down of Q0 , removes
breakpoint between V011 and Vm
Values arc chosen to ensure most of Ic; is
provided as base driving current to Q,,
Output inverting BJT, output low driver for
current sourcing pull-down
Input clamping diodes to limit the negative
swing of the inputs to one SBD drop
below ground
Changes in VTC
The improvements from STTL to LSTTL cause input
and output shifts in the voltage transfer characteristic. The emitter resistor Rm which was connected
to ground for STTL, is now connected to the output.
This raises the output high voltage to
The input high and low voltages for STTL were
dependent on -Vci:.,(HARD) = -0.5 V. With Q1 replaced by a Schottky-barrier diode, this term is replaced by -VD., = -0.3 V. This reduces V,L and V,, 1
for LSTTL by approximately 0.2 V.
The purpose of each element in the series
54LS00/74LS00 LSTTL gate of Figure 8.8 is summarized in Table 8.3. The states of each BJT for the
output high and low logic levels are tabulated in
Table 8.4.
LSTTL Power Dissipation
Compare the average power dissipation for the lowpower LSTTL inverter circuit corresponding to Figure
8.8 with the "high-powd' STTL gate of Example 8.4.
Example 8.5
Solution (Output High Supply Currents)
For
the output high state, following dashed path 1 in
Figure 8.9, I,u/OH) is given by
(5) - (0.3) - (0.5) = 210 µA
(20k)
TABLE 8.4 States of Diodes and BJTs
in Output High and Low Logic Levels
for 54LS00/74LS00 Series LSTTL Gate
Element
Du\
Qs
QI)
Qo
Qp
Q,,2
Doi
DD2
& DIil
and I,dOH) and IR 0 ,(OH) are both 0.
VoH
VoL
On
Cutoff
Cutoff
Cutoff
Edge of conduction
Cutoff
Cutoff
Cutoff
Cutoff
On hard
On hard
On hard
Forward active
Cutoff
Cutoff
Cutoff
Solution (Output Low Supply Currents) For the
output low state, IR 8 (OL) is found by following
dashed path 2 in Figure 8.9, yielding
_ Vee - VaLs(HARD) - Vnco(HARD)
I"/l (OL) -
R
/l
(5)
2(0.8)
(20k)
= 170 µA
V'cc= 5 V
0
Vcc=5V
I:
RB
,--2---------
i20w
~
,~
'f
------,
d---------1-
:
--1--,--,:i
R'CP
.J'r['..""
R'Bif 20kQ
Rc.!120<>
I'II.I
I
,
DI
1'
:
Q'n
$
Vrn=VoH
~
On
D'!'EP
I
0
i:c
'a
3--
De~
_,--.-------1,
IoL
D'c
i
;_____o V'oH
3kQ
RBD
~~-~Q'o
R'BD
2,
1.5 kQ
R'
'>
CD<__
3kQ
Q'o
t. .
_..,._
-=-
I'IL2
-=I'Il.o
~·-
driving gate (output low state)
FIGURE 8.9
~ 4kQ
VOL• V'rn
'
1--"
--f<I
4kQ
,I''
~12on
Cascaded LSTTL Gates for Power Dissipation Analysis
load gates (output high state)
110
Chapter 8/Schottky Transistor-Transistor Logic (STTL)
Following dashed path 3 in Figure 8.9, IRc(OL) is
IRc(OL) = Vee - VeE,s(HARD) - VBE,o(HARD)
Re
_ (5) - (0.5) - (0.8) _
µA
(8k)
- 4 63
and IRCI,(OL) is negligible.
Solution (Average Power Dissipation) The average power dissipation of the LSTTL gate is obtained by substitution as
(210µ,) + (170µ,) + (463µ,) ( )
~~=-~~--~---~s
( )
2
= 2.11 mW
This is slightly over a tenth of the power dissipation
for the STTL gate calculated in Example 8.4. Hence,
increasing the resistor values decreases the power
dissipation by about the same factor.
The m.aximum fan-out analysis for the low
power STTL circuit of Figure 8.9 is left as a homework problem.
8. 7 STTL SPICE SIMULATION
Figure 8.10 shows an STTL inverter with appropriate
SPICE labelings. Note that the Schottky-clamping
diodes for each of the SBJTs are shown in separate
devices. This is to exemplify that SPICE does not provide explicit models for SBJTs and they must be specified in the input CIRcuit file as two separate devices:
I
n+ 14
VCC '.f DC 5V
!
I
()
0
FIGURE 8.10
STTL Inverter with Appropriate SPICE Labelings
n--=-!a
8. 7
one BJT and one (Schottky-barrier) diode. The input
CIRcuit file that corresponds to this circuit is as follows:
Schottky TTL 54S00/74SOO
*Series (STTL) Inverter
VCC 4 0 DC 5V
VIN 1 D PULSE<DV 5V OS 2NS 2NS
+ 50NS 1D □ NS)
RB 4 2 2,8KOHM
RC 4 5 9000HM
RCP 4 10 500HM
REP 11 D 3-5KOHM
RBD 6 7 50DOHM
RCD 6 8 2500HM
QI 3 2 1 QNPN
DQI 2 3 SBD
QS 5 3 6 QNPN
111
STTL SPICE Simulation
DQS 3 5 SBD
QP 10 5 11 QNPN
DQP 5 10 SBD
QP2 10 11 9 QNPN
QD 8 7 D QNPN
DQD 7 8 SBD
QO 9 6 D QNPN
DQO 6 9 SBD
DC D 1 SBD
,MODEL SBD D(IS=7,3E-11
+ VJ=0,5V CJ0= □.□ 5PF EG= □
-69
+ XTI=2- □)
-MODEL QNPN NPN(IS=1E-14 BF=49
VA=80 TF=0,45NS TR=5NS
CCS=3PFD CJE=2,6PFD
CJC=2PFD R8=130HM
RC=6,20HM)
+
+
+
+
VIN(V)
51
VOlIT
4-
(V)
3- -
2- -
54
0
t(ns)
I
0
25
50
75
100
125
25
50
75
100
125
3
V 0 1rr(V)
2
5
4
f-----~+--~-+--~-+------ll>
0
0
2
3
4
V IN(V)
5
3
2
1
t(ns)
0
0
(a)
FIGURE 8.11 Results of Section 8.7 STTL Inverter
SPICE Simulation: (a) Voltage transfer characteristic
(b)
obtained .DC sweep, (6) Transient response obtained
.TRAN sweep
112
Chapter 8/Schottky Transistor-Transistor Logic (STTL)
-DC VIN DV 5V □ -1V
-PLOT DC V(9)
-TRAN 1NS 125NS
-PLOT TRAN V(1) V(9)
Plots of the VTC and transient response obtained from this simulation are shown in Figures
8.lla and b, respectively.
-END
CHAPTER 8 PROBLEMS
8.1
= 100.
= 10 kfl.
(a) Analyze the SBJT circuit of Figure P8.1. Specif-
8.4
Repeat Problem 8.3 for /3 1
ically, determine IB, le, ls 1\D, and Vc 1 - Use /3 1 =
100, V1ff(FA) = 0.7 V, V111 (HARD) = 0.8 V, and
Vu(HARD) = 0.5 V for the BJT and V, 1\D(ON)
= 0.3 V for the SBD.
(b) What is the operating state of the BJT?
(c) Repeat parts (a) and (b) with the SBD removed
from the circuit. Use VmJSAT) = 0.8 V and
Vc 1 (SAT) = 0.2 V.
8.5
Repeat Problem 8.3 for R8
8.6
Sketch the VTC for the STTL NAND gate of Figure
P8.n with V1N 1 = V1:-i 2 = V1N. Also, calculate the
noise margins. Let /3r = 100, VB 1 (FA) = 0.7 V,
V111 (HARD) = 0.8 V, and Vc 1 (HARD) = 0.5 V for
the BJTs and V, 1m = 0.3 V for the SBDs.
Ycc=5V
0
··7
~~3ill
Re
i
)
----{ ~
I I
Ycc~5V
I
I
Rc.~5011
1 kn
VINA~~
Vma~ :
i, Q
i
DJ1-
1
~
J_
~
FIGURE P8.1
= 10.7 V.
8.2
Repeat Problem 8.1 for V,m
8.3
Sketch the VTC for the SBJT inverter shown in Figure P8.3. Also, calculate the noise margins. Let /3 1. =
70, Vm,(FA) = 0.7 V, V81 (HARD) = 0.8 V, and
Vcr(HARD) = 0.5 V for the BJT.
Vee= 5 V
f
FIGURE P8.3
De,
'.A
Qo
~Do
Ro
75011
i
I
FIGURE PB.6
8.7
Determine the state of each BJT and diode in the
circuit of Figure PS.6 for the output high and low
states.
8.8
For the Schottky gate of Problem S.n, calculate the
following:
(a) the input low current 111
(b) the output low current 101
(c) the maximum fan-out"" N = 101 /In.
8.9
Calculate the average power dissipation for the
Schottky gate of Figure P8.6.
Chapter 8 Problems
8.10
Sketch the VfC for the STfL gate of Figure P8.10.
Use V1w(FA) = 0.7 V, V1dHARD) = 0.8 V, ,md
Vu (HARD) = 0.5 V for the BJTs
113
8.17
Determine the state of each BJT for the STTL NANO
gate of Figure PS.10 for the output high and low
states.
8.18
Show that the circuit of Figure P8.10 performs the
logical NAND function by determining VouT for all
possible combinations of V1N I and V1:-.J2, where each
of these are either low (O V) or high (5 V).
8.19
Sketch the VTC for the LSTTL circuit of Figure
P8.19. Also, calculate the noise margins. Use {3 1 =
50, VBIJFA) = 0.7 V, Vlll,(HARD) = 0.8 V, and
Vu,(HARD) = 0.5 V for the BJTs.
8.20
For the LSTTL gate of Figure P8.19, calculate the
following:
(a) the input low current I1L
(b) the output low current IoL
(c) the maximum fan-out= N = Im/1 11
Use f3F = 50, Vm,(FA) = 0.7 V, V8E(HARD) = 0.8 V,
and VcdHARD) = 0.5 V for the BJTs. See Figure 8.9.
8.21
Calculate the average power dissipation for the
LSTTL inverter corresponding to Figure P8.19.
8.22
Repeat Problem 8.20 and 8.21 for RB = 40 kfl, Re =
20 k.O, Rel' = 1 kn, and RE[' = 14 kft For fan-out
sec Figure 8. 9.
8.23
Repeat Problem 8.20 and 8.21 for RH = 4 kn, Re
FIGURE PB.10
8.11
For the STfL NAND gate of Figure P8.10, calculate
the following with f3 = 100 for all BJTs:
(a) the input low current 111 .
(b) the output low current IuL
(c) the maximum fan-out = N = Irn_/I 1L
8.12
Calculate the average power dissipation for the
STTL inverter corresponding to Figure P8.10.
8.13
Repeat Problems 8.11 and 8.12 for RB
1.6 kD., and Ref' = 120 n.
= 4 kfl, Re =
8.14
Repeat Problems 8.11 and 8.12 for RH
20 kD., and Re = 1 kfl.
= 40 kfl, Re =
8.15
For the STTL NAND gate of Figure P8.10, list the
clements that make up
(a) the input stage
(b) the drive splitter
(c) the output high driver
(d) the output low driver
Refer to the TTL super-circuitry block diagram in
Figure 4.9 of section 4.3.
8.16
For the STTL NAND gate of Figure P8.10, list the
purpose of all BJTs, diodes, and resistors.
=
114
Chapter 8/Schottky Transistor-Transistor Logic (STTL)
Q,
Q,,
V !NB o-------
FIGURE P8.19
1.6 kD, Rel' = 130
see Figure 8.9.
8.24
n,
and REI' = 1 kD. For fan-out
For the LSTIL NANO gate of Figure PS.19, list the
elements that make up
(a) the input stage
(b) the drive splitter
(c) the output high driver
(d) the output low driver
Refer to the TTL super-circuitry block diagram in
Figure 4.9 of section 4.3.
8.25
For the LSTTL NANO gate of Figure PS.19, list the
purpose of all BJTs, diodes, and resistors.
8.26
Determine the state of each BJT for the LSTTL
NAND gate of Figure PS.19 for the output high and
low states.
ADV
SCHOTTKY
TRANSISTORTRA SISTOR
GIC [ASTTL]
In 1985 Texas Instruments introduced improvements
to the two TTL sub-families of the previous chapter.
These improved subfamilies are
1.
Advanced Schottky TTL (ASTTL), an advanced
version of STTL, and
2.
Advanced Low-Power Schottky TTL (ALSTTL),
an advanced version of LSTTL (not a lower
power version of the ASTTL)
At about the same time Fairchild introduced its own
improved TTL sub-family, which is
3.
Fairchild Advanced Schottky TTL (FAST), which
is intermediate (between ASTTL and ALSTTL)
in performance and power dissipation
while maintam1ng the typical power dissipation
at 20 mW/gate calculated in the previous chapter for
the STTL logic family. It should be noted that the
smaller internal dimensions of the advanced
Schottky TTL BJTs increases susceptibility to damage
from electrostatic discharge due to shallower diffusions and thinner oxides.
The three advanced Schottky TfL subfamilies
(which were commercially introduced at roughly the
same time) are introduced in this chapter in order of
complexity.
9.1
These TTL sub-families were made possible in
part by improvements in BJT fobrication techniques.
IC BJTs with 3 f.Lm mininwm out size (as compared
with 5 f.Ll11 in the TTL sub-families presented previously) were made possible through inclusion of
walled bases and emitters. Ion implantation is used
to give well-controlled shallow junctions for the active devices. Use of oxide isolation (as discussed in
section 3.2) instead of PN junction isolation eliminates parasitic capacitance associated with the PN
junction isolation regions. This reduced frequency
limitations and allows internal nodes to charge
faster. Hence, reduced junction capacitance results,
with reduced propagation delays, on the order of
1.5 ns. ASTTL and ALSTfL logic families include a
PNP BJT input section which reduces the input low
current by 75%. The reduced input current allows
ASTTL gates to reduce the propagation delay
ADVANCED LSTTL (ALSTTL)
Figure 9.1a shows the 54ALS00/74ALS00 series advanced low-power Schottky TTL (ALSTTL) gate.
This gate is a design improvement of the low-power
STTL (LSTfL) gate of the previous ch£Jpter, not a
low-power version of the advanced STTL (ASTTL)
discussed later in this chapter.
Speed Improvements
The ALSTTL circuit improves the high-to-low transition speed over the LSTTL gate (Figure 8.8) of the
previous chapter by inclusion of Q513 and its collector
resistor Res• Inclusion of the non-inverting BJT Q 58
increases the internal current drive by providing base
driving current to Q5 . The diodes DsA and DsB provide low impedance paths for removal of storedcharge from the base of Q5 . This enhances the output
low-to-high transition time.
115
116
Chapter 9/Advanced Schottky Transistor-Transistor Logic (ASTTL)
,,.-· .. 2 · .............. · ....... ···----2'
.................................
.;.
(a)
Vour(V)
Vcc=5
V 0 H=4.3
4
3
2t
1
VOL= 0.5
-----------
1
VIL= 1.4
2
3
4
5
VINA =V INB(V)
Vrn =1.7
(b)
FIGURE 9.1 Advanced Low-power Schottky
Transistor-transistor Logic (ALSTTL) 54ALS00/74ALS00
Two-input NAND Gate: (a) Circuit, (b) Voltage transfer
characteristic
cJ 1 Adv;:rnced LSTIL (ALSTIL)
Input Section
The input diodes of the LSTTL circuit are replaced
with emitter follower PNP BJTs, Q 1F;\ and Q 1Pll· The
emitter-base PN junction of the Qw BJTs compensates for the additional base-emitter drop of Q 511 between the inputs and the output. The emitterfollower configuration also reduces h by a factor of
approximately ¼, and thus increases the fan-out.
Additional inputs can be added by duplication of the
basic input circuit configuration (shown shaded for
input A in Figure 9.1).
Discharge of Pull-Up Section
and Output Load Capacitance
The diode DI' allows the base of Qp 2 to discharge
through Q 5 when the output switches high-to-low
and provides more rapid discharging of the load capacitance.
Output Clamping Diode
Finally, the output clamping diode Dco has been
added to the output and provides the same function
as the input clamping diode Q 1c, That is, Dco prevents the output from overshooting ground (during
an output high-to-low transition) by more than a
Schottky diode turn-on voltage VsllD(ON) = 0.3 V.
TABLE 9.1
Element
QS!l
Res
DsJ\ & Dss
Qp & Qp2
117
The purpose of each circuit element is tabulated
in Table 9.1. The state of each BJT and diode for the
output high and low states is listed in Table 9.2.
Example 9.1 ASTTL Voltage Transfer
Characteristic
Determine the critical voltages for the ALSTTL circuit
of Figure 9.la and draw the voltage transfer characteristic. Use VBE,Nl'N(FA) = VEB.rrs:p(FA) = 0.7 V,
VBE(HARD) = 0.8 V, and VcE(HARD) = 0.5 V.
Solution (Output High Voltage) For low input
voltages Q 0 will be cutoff (as will be seen mom en tarily) and Qp will be forward active. The output high
voltage therefore can be obtained by writing KVL for
dashed path 1 of Figure 9.la as follows:
V 0 11 = Vee - Vmy(FA) = (5) - (0.7) = 4.3 V
=
Solution (Input Low Voltage
V1J Following
dashed path 2 of Figure 9.la, it is seen that PNP
input BJT Qil'J\ is forward active for VINA < Vcc V EB,IPJ\(FA). Thus, the base voltage of QsB is equal to
the emitter voltage of QII';\ and as long as Q 1rA is
forward active
Purpose of Each Element for a Series 54ALS00/74ALS00 ALSTTL Gate
Purpose
Emitter-follower configuration reduces I11
by¼, Vrn.w compensates for V1w.sB
Limits I1L
Drive splitter, provides base driving
current to Q0 , base-emitter level
shifting for shift of transition width,
pull-down of Qr and Qp2
Along with Q 5 provides logic inversion to
output-high driver
Provides base driving current to Q5
Collector resistor for QsB
Provides discharge path for base of Q 5
Active Darlington configuration currentsourcing pull-up, base-emitter levelshiftings between Vee and output
Part of active pull-up and limits current
spikes during output high-to-low
transition
Element
Dco
Purpose
Gives emitter of Q,, a direct path to
output and allows charging of load
capacitance before Qp 2 is fully on
Allows Qp 2 and load capacitance to
discharge through collector of Q 5
Allows active pull-down of Q0 , removes
breakpoint between V01 1 and VoL
Values are chosen to ensure most of Ic.R
is provided as base driving current
to Q0
Output inverting BJT, output low driver
for current-sourcing pull-down
Input clamping diode to limit the
negative swing of the inputs to one
SBD drop below ground
Output clamping diode, serves same
purpose as Dc 1 at the input
118
Chapter 9/Advanced Schottky Transistor-Transistor Logic (ASTTL)
TABLE 9.2 States of Diodes and BJTs
in Output High and Low Logic Levels
for 54ALS00/74ALS00 Series ASTTL Gate
Element
Vol-!
YoL
QIP
Os
OsB
DsA & Dsn
QD
Oo
Qp
Qp2
DP
On
Cutoff
Cutoff
Cutoff
Cutoff
Cutoff
EOC
Cutoff
Cutoff
Cutoff
On hard
On hard
Cutoff
On hard
On hard
Fotward active
Cutoff
Cutoff
f
Tips, Tricks, and Gimmicks
Varactor Diode
From section 2.4, a PN junction has capacitance given by
where
= zero-bias (i.e. V = 0) junction
capacitance [Fl
cp = junction potential (typically
0.9 to 1 V)
m = grading coefficient (m = 1/2 or
C 00
0
0
Examining Figure 9.1a, it is seen that Q 0 , Q 5 , and
Q 5 n turn on simultaneously, when the base voltage
of Q58 reaches
= VBE,o(FA) + VBE,s(FA) + VaE,sa(FA)
V8 sa
Thus, the turn on voltage for Q 0 , Q 5 , and Q 58 can
be found by writing KVL along dashed path 3:
1/i,_ =
VBE,o(FA)
+
vllE,s(FA)
+
VaE,sB(FA)
- VEB,IP;\(FA)
= 2V8 £(FA) = 2(0.7) = 1.4 V
Solution (Output Low Voltage
=
V0 J
As the
input voltage is increased beyond V,L the output begins to drop. The output continues to drop until Q0
is on hard and the output low voltage is
VOL = VCE,o(HARD) = 0.5 V
Solution (Input High Voltage = VIH) The input
voltage at which the output drops to Vm is the input
voltage sufficient to bring Q 0 , Q 5 , and Q 58 on hard.
Thus following dashed path 3 yields
TT
1/3 for digital IC diodes)
= minority carrier transit time
Section 2.4 also discussed varactor diodes,
which are reverse-biased diodes used as voltage-controlled capacitors characterized by the
above capacitance expression. Since the diode
is reverse biased, the first term is negligible and
the expression reduces to the approximation
C0 (V0 )
r
~
(
Coo
l _ Vo
(ceuc,scd b;,scd)
<Po
Figure 9.2 shows the circuit symbol for a varactor diode. The remaining two advanced
STTL circuits employ varactors to improve dynamic response.
-1>11~
.
Viu = V13w(HARD) + VBE,s(HARD)
+
V8 csH(HARD) - VmtPA(FA)
= 3 Vlll-:(HARD) - VEBl,(FA)
=
FIGURE 9.2
Varactor Diode Circuit Symbol
3(0.8) - (0.7) = 1.7 V
If the input voltage is increased further, Q,rA will enter the cutoff mode of operation.
Solution
(Voltage
Transfer
Characteristic)
The voltage transfer characteristic for the ALSTTL
gate of Figure 9. la is shown in Figure 9.16 with the
critical voltages labeled.
9.2 FAIRCHILD ADVANCED
SCHOTTKY TTL (FAST)
Figure 9.3a displays a two-input NAND gate of the
Fairchild Advanced Schottky TTL (FAST) logic
lJ.2
lOkn
Fairchild Advanced Schottky TfL (FAST)
R:,
R:
Q
4.1 kn
D,
(a)
VOH= 4.3------.
4
3
2
~--+----+-++--~+----+----+-----
3
4
VINA = V INB(V)
5
(b)
FIGURE 9.3 Fairchild Advanced Schottky TfL (FAST)
54F00/74F00 Two-input NAND Gate: (a) Circuit with
"Miller killd', (b) Voltage transfer characteristic
119
120
Chapter 9/Advanced Schottky Transistor-Transistor Lob>ic (ASTTL)
family. This gate is intermediate in power-dissipation, fan-out, and speed between the ALSTTL circuit
of the previous section and the ASTTL circuit in the
following section. The most notable addition to the
FAST logic circuitry is the presence of the Miller killer
sub-circuit explained in the following sub-section.
sub-circuit commonly referred to as a Miller killer.
The Miller killer sub-circuit compensates for the
Miller effect present in Q 0 in the following fashion:
•
Miller Killer
Miller's theorem states that the equivalent baseemitter capacitance is approximately the base-collector capacitance of a BJT inuliiplie<l by f3r of the BJT.
Thus, the BJTs in a TTL circuit are subject to an additional speed limitation since the base-collector capacitance increases with frequency of switching. This
limitation is referred to as the Miller effect. The output BJT Q0 is particularly susceptible to this. Additional sub-circuitry has been added to the FAST gate
of Figure 9.3a (and the ASTTL logic family presented
in the following section) to compensate for the Miller
effect.
In Figure 9.3a, BJT Q1v Schottky diodes DB1v
Dc1v and DP, and the varactor diode Dv make up a
TABLE 9.3
Element
QsB
Res
RBS
Ds
Qp & Qp2
Re"
As the output rises during the output low-tohigh transition, the voltage at the emitter of
Qp rises
• This in turn induces a current in the varactor
diode Dv
• The varactor current then turns on QK momentarily
• QK in the forward active mode pulls-down
the base of Q 0
• This absorbs the current through the basecollector transition capacitance
• This improves the output rise time and decreases the dynamic power dissipation that
would have occurred from the output high
and low drivers being on simulatneously
When Q5 enters forward active operation, the varactor diode discharges through the Schottky diodes
Purpose of Each Element for a Series 54F00/74F00 FAST Gate
Purpose
Input diodes
Limits I1L
Drive splitter, provides base driving current
to Q0 , base-emitter level shifting for
shift of transition width, pull-down of
Qp and Qp2
Along with Q 5 provides logic inversion to
output-high driver
Provides base driving current to Q5
Collector resistor for QsB
Provides discharge path for base of Q 5
Provides discharge path for base of Q5
Active Darlington configuration currentsourcing pull-up, base-emitter levelshiftings between Vee and output
Part of active pull-up and limits current
spikes during output high-to-low
transition
Gives emitter of Qp a direct path to output
and allows charging of load capacitance
before Qp 2 is fully on
Allows load capacitance to discharge
through collector of Qs
Element
Deo
Purpose
Allows Qp 2 to discharge through collector
of Q5 and discharges Dv when Q5 is
forward active
Active pull-down of Q0 , removes
breakpoint between Vm1 and VoL
Values are chosen to ensure most of Ic-,R is
provided as base driving current to Q 0
Output inverting BJT, output low driver for
current sourcing pull-down
Input clamping diodes to limit the negative
swing of the inputs to one diode drop
below ground
Output clamping diode, serves same
purpose as De 1at the input
During output low-to-high transition
induces a current which turns on QK
momentarily
Along with DP provides a discharge path
for Dv
Pulls down base of Q 0 during rapid
switching
Limits pull-down of QK to an adequate
level without overkill
9.3
Advanced Schottky Transistor-Transistor Logic (AS1TL)
9.3 ADVANCED SCHOTTKY
TRANSISTORm TRANSISTOR
LOGIC (ASTTL)
D 13 K and Dp. Finally, the Schottky diode DcK limits
the pull-down of the base of Q0 to a satisfactory
amount without reducing the speed enhancing effects.
The final and most complex TTL logic family is the
advanced Schottky transistor-transistor logic
(ASTIL) family shown in its two-input NAND configuration in Figure 9.4.
Input Diode Configuration
Examining the FAST logic circuit in Figure 9.3a it
should be noticed that Schottky diode input circuitry
of the LSTIL gate presented in the previous chapter
is employed (as opposed to multi-emitter or PNP
input configurations).
The voltage transfer characteristic for the FAST
circuit is shown in Figure 9.3b. Calculation of the
critical voltages is left as a homework exercise. Table
9.3 indicates the purpose of each element in the
FAST gate.
Modified PNP Input Section
The ASTIL input section is a PNP BJT input section
similar to that of the ALSTIL gate presented earlier
in this chapter. The input clamping Schottky diode
has been replaced with a base-emitter shorted SBD
diode configuration. The input configuration has the
w
Re
R.
lOkW
_,.,,r········ .. ···················
vm" c
.
Ql'A
p;Q., • "·
i
.>
>
Rco <: 2kW
<
-[~.
Ran< 1 k\V
:kl
,
<
Dss
FIGURE 9.4
121
Advanced Schottky Transistor-transistor Logic (ASTTL) 54AS00/74AS00 Two-input NAl'\JD Gate
122
Chapter 9/J\dvanced Schottky Transistor-Transistor Logic (J\STTL)
reduced input high current of the ALS"ITL gate and
thus increased fon-out, lower power dissipation, and
faster dynamic response is associated with it.
Miller Killer Sub-Circuit
The Miller killer sub-circuit presented in the previous
section on the FAST sub-family is included in ASTTL
logic gates. The operation is identical to that explained in the preceding section.
Improved Output High Driver
The output high driver has been improved by adding
a third BJT Qp 3 . The diodes DR, and DR 2 and resistor
R,w, maintain a constant reference voltage to the
base of Qp 3 through the resistor Rlll, 2 · This provides
additional drive current to the base of Qp 2, while increasing the available current to the varactor diode
Dv during the low-to-high transition.
TABLE 9.4
Element
QI!'/\
& Qll'B
QIC1\ & Q1rn
RB
Qs & Qsz
QSB
R,s
RBS
Ds,
Q1,& Ql'2
Other Changes
The diode DD present in the FAST gate of Figure 9.3
has been replaced with a BJT Qcm providing an active
contribution to the discharge of the load capacitance.
Also, the collector of the BJT Q 52 is fed by the output
high driver through the Schottky diode D 52 . This allows capacitances of the output high to discharge
through the collector of Q 52 when Q 52 is forward
active.
The purpose of each element in the ASTTL logic
E;ite of Fii11nc• 9.4 is tc1bulated in Table 9.4.
This and the previous four chapters trace the design development of TTL logic and history of its subfamilies. The intrinsic complexity of TTL logic gates
presents a limiting factor on scale of integration for
integr;:ited circuits. Very large scale integration (integr;:ited circuits with 10,000 or more logic gates)
would be extremely difficult to fabricate with TTL
Purpose of Each Element for a Series 54AS00/74AS0O FAST Gate
Purpose
Input diodes
Input clamping diodes
Limits I1L
Drive splitter, provides base driving current
to Q 0 , base-emitter level shifting for
shift of transition width, pull-down of
Q,. and Q1,e
Along with Os provides logic inversion to
output-high driver
Provides base driving current to Os
Collector resistor for Osn
Provides discharge path for base of Os
Provides discharge path for base of Os
Active Darlington configuration currentsourcing pull-up, base-emitter levelshiftings between Vee and output
Aids in discharge of base of Qp
Part of active pull-up and limits current
spikes during output high-to-low
transition
Gives emitter of Qp a direct path to output
and allows charging of load capacitance
before Q 1, 2 is fully on
Active discharge of output load
capacitance through collector of Os
Limits base current of Q01,
Active pull-down of Q 0 , removes
breakpoint between V, ll I and Vm
Element
DP
R1m & Rm
Q0
Du
Dcu
Dv
D 1lK
QK
DcK
Qp1
0 1, 1 & DRz
RB 2
RBI
Purpose
Allows Qp 2 to discharge through collector
of Qs and discharges Dv when Os is
forward active
Values are chosen to ensure most of lc,R is
provided as base driving current to Q 0
Output inverting BJT, output low driver for
current sourcing pull-down
Input clamping diode to limit the negative
swing of the inputs to one diode drop
below ground
Output clamping diode, serves same
purpose as Du at the input
During output low-to-high transition
induces a current which turns on QK
momentarily
Along with Dp provides a discharge path
for Dv
Pulls down base of Q 0 during rapid
switching
Limits pull-down of QK to an adequate
level without overkill
Decreases rise time at initiation of low-tohigh transition
Provides a reference voltage to the base
of Q1'3
Limits current of base of Qp3
Further limits current to and aids in
reference voltage to base of QI'.,
Chc1pte1· 9 Problems
technology because of the number of transistors per
gate. Later chapters present logic fon,ilies con-
123
structed from MOSFETs which require only a few
transistors per gate and overcome the VLSI barrier.
CHAPTER 9 PROBLEMS
9.1
By inspection of the ALSTIL NANO circuit of Figure
9.la, determine the critical voltages. Docs a "knee"
region exist in the voltage transfer characteristic of
the corresponding inverter? Use VRE(FA) = 0. 7 V,
VBl,(HARD) = 0.8 V, Vu,(HARD) = 0.5 V, and
VsBu(ON) = 0.3 V.
9.2
For the ALSTIL NANO circuit of Figure 9. la, reduce
the resistor values by a factor of 10 and discuss the
effects of this modification on the following:
(a) the circuit voltages
(b) the average power dissipation
(c) the switching speed
9.8
Indicate the type of operation for each transistor in
Figure 9.3a for the output high and low states.
9.9
By inspection of the FAST NANO circuit of Figure
9.4, determine the critical voltages. Does a "knee"
region exist in the voltage transfer characteristic of
the corresponding inverter? Use V1,io(FA) = 0.7 V,
VrnJHARD) = 0.8 V, VcE(HARD) = 0.5 V, and
Vsim(ON) = 0.3 V.
9.10
For the FAST NAND circuit of Figure 9.4, reduce the
resistor values by a factor of 10 and discuss the effects of this modification on the following:
(a) the circuit voltages
(b) the average power dissipation
(c) the switching speed
9.3
Explain the purpose of each element in the ALSTIL
circuit of Figure 9.la.
9.4
Indicate the type of operation for each transistor in
Figure 9.1a for the output high and low states.
9.11
Explain the purpose of each element in the FAST
circuit of Figure 9.4.
9.5
By inspection of the FAST NANO circuit of Figure
9.3a, determine the critical voltages. Docs a "knee"
region exist in the voltage transfer characteristic of
the corresponding inverter? Use VBE(FA) = 0.7 V,
VBJJHARD) = 0.8 V, Vc 1 (HARD) = 0.5 V, and
Vs1m(ON) = 0.3 V.
9.12
Indicate the type of operation for each transistor in
Figure 9.4 for the output high and low states.
9.13
Calculate the average power dissipated for the
ALSTIL circuit of Figure 9.1a. Use V111 :(FA) = 0.7 V,
VBE(HARD) = 0.8 V, Vn(HARD) = 0.5 V, and
Vs 1m(ON) = 0.3 V.
9.14
Calculate the average power dissipated for the FAST
circuit of Figure 9.3a. Use V,dFA) = 0.7 V,
VB! (HARD) = 0.8 V, VCJ (HARD) = 0.5 V, and
VsBu(ON) = 0.3 V.
9.15
Calculate the average power dissipated for the
ASTIL circuit of Figure 9.4. Use VB 1,(FA) = 0.7 V,
VB 1,(HARD) = 0.8 V, VcE(HARD) = 0.5 V, and
V 5 ,m(ON) = 0.3 V.
9.6
9.7
For the FAST NANO circuit of Figure 9.3a, reduce
the resistor values by a factor of 10 and discuss the
effects of this modification on the following:
(a) the circuit voltages
(b) the average power dissipation
(c) the switching speed
Explain the purpose of each element in the FAST
circuit of Figure 9.3a.
10
OTHER TTL
GATES
consisting of Q 1 and RB and the output section con-
Preceding chapters contain descriptions of the various TIL logic families, indicating improvements
made over the years from the earliest RTL and DTL
subfamilies to the advanced STTL and ASTTL subfamilies. Throughout the TTL chapters, the inverter
and multi-input NAND gates are used to demonstrate the design and analysis of TTL gates. In fact,
TIL logic families can also realize the other basic
logic functions AND, NOR, and OR, as well as ANDOR-invert. The present chapter indicates the modifications to the standard NAND circuitiy of the 5400/
7400 standard TTL logic family to provide these other
functions. Schematics for gates of additional TTL
sub-families are presented in the homework problems at the end of the chapter. The schematics for
each logic function of the TTL sub-families are tabulated in Table 10.1 for easy reference.
sistini of Q 0 , DL, Qp, c1nd Rcr are identical to the
previous TTL NAND gate of Figure 7.3 presented in
section 7.4 with Q0 providing one level of inversion
between the input and output. Also note the branch
containing Qs, Re, and RD is left unchanged from the
previous NAND gate.
The drive splitter section, however, contains
some additional circuit components which are Qs 2,
QsD, D5, RsD, and Res• These are enclosed in the
shaded block and provide a second level of inversion
between the input and output. Thus, with two inversions the circuit realizes the logical AND function
as predicted in the previous sub-section. It will be
shown in the following sub-sections that the additional circuitry also removes the "knee" found in the
TTL NAND gate VfC.
Output Low Voltage
= VoL
10.1 TTL AND GATES
With either or both inputs low, a large current flows
TTL AND Super-Circuitry
into the base of Q 1• By following dashed path 1 of
Figure 10.lb, this current is given by
Figure 4. 7 of section 4.3 is a block diagram for a TTL
NAND gate. This block diagram indicates an output
low driver being enabled for ANDing of the input
voltages and an output high driver being enabled for
NOT ANDing of the inputs. If the output drivers
were enabled in the inverse fashion, the gate would
become an AND gate. This is accomplished by using
a inverting drive splitter as shown in the block diagram of Figure 10.la. In this circuit the output high
driver is enabled for ANDing of the inputs and the
output low driver is enabled for NOT ANDing of the
inputs.
I
_ Vee - VBE,1 - ViN(low)
RB
B,/ -
Furthermore, for either input low, the collector current of Q 1 is essentially zero, while Q 1 is in saturation,
since
Ic, 1 = - 18 ,s2 (/eakage) << {3Fliu
The voltage at the base of Q52 is then
Hence, Q 52 and therefore Q 5 D are cutoff for V1N low.
With Q 52 and Q 5 n cutoff, Q 0 and Q 5 are easily seen
to be saturated along with D 5 conducting by following dashed path 2 of Figure 10.16. The output low
voltage (for any input voltage low) is therefore
TTL AND Gate Circuit
Figure 10.lb shows the 5408/7408 standard TTL
AND gate circuit and the circuit symbol for this gate
is shown in Figure 10.lc. Note that the input section
VoL
124
=
VeE,o(SAT)
TABLE 10.1
Figure Numbers of TTL Sub-Family Logic Gates
Sub-Family
Inverter
NAND
DTL
TTL
LTTL
HTTL
STTL
LSTTL
6.4
7.5
6.5
7.3
7.8
7.9
8.5
8.8
AND
NOR
OR
AOI
XOR
Schmitt
Tri-State
10.1b
10.3a
Pl0.24
10.4a
10.5a
10.8a
10.10a
10.12a
Pl0.12
Pl0.15
Pl0.20
Pl0.22
Pl0.30
Pl0.31
Pl0.25
P10.5
P10.8
I
-
Output
High
Pull-up
Driver
-
Output
Low
Pull-down
Driver
Yies
VINA
VINB
..
.
Diode or
Multi-emitter
AND gate
VAND
Inverting
Drive
Splitter
f,---.
I?
I
N
0
I
(a)
(b)
:=o--F=AB
(c)
FIGURE 10.1
Standard 5408/7408 TTL AND Gate: (a) Block diagram, (b) Circuit schematic, (c) Circuit symbol
125
126
Chapter 10/0ther TTL Gates
As the input voltage is further increased and Q5 D
begins to conduct, the base current of Qs is reduced
still further and Qs as well as Q 0 come out of saturation. Hence, VocT begins to increase and Vc,s 2 begins to decrease.
4VOH
= 3.6 - - - - - - - - - - - . - - - - - - - - - -
Input High Voltage= Vrn
3
When VH.s drops below VBE.o(FA) + VBE,s(FA), Q0
becomes cutoff and the output begins to go high.
When Q 50 enters saturation, the voltage V,3, 5 =
Vcc.;;D(SAT) is rlefinitely lmv enough to cutoff both
Q0 and Q5 . The input voltage (with all inputs tied
together) necessary to saturate Q 52 and Q 50 is then
the input high voltage, given by
2
1
I
2
3
4
VIll = 1.4
Va= 1.2
vi.\'
= ViiE,So(SAT) + VBE,s2(SAT)
=
(d)
Output High Voltage
FIGURE 10.1 (continued)
transfer characteristic
(d) TTL AND gate voltage
Input Low Voltage = V1L
To determine the input low voltage, note that QI, RH,
Q 52, Q 50, Res, and R50 collectively resemble the portion of the TTL NAND gate (in Figure 7.3) containing
Q,, RB, Q 5, Q 0 , Re, and R0 . Hence, the collector voltage of Q 50 will be high for any input low in a NANDlike fashion and the output will be low with Q5 and
Q 0 in saturation. As the input voltage increases, the
collector current of Q 52 increases, the base voltage of
Q 52 increases, and Q 52 becomes forward active. Also,
as the input voltage is increased further, the current
through the diode D 5 decreases. However, the mag-nitude of the diverted current through Q 52 is insufficient to take Q 5 and Q 0 out of saturation. Thus, the
voltage at the collector of Q52 remains approximately
fixed at
The input voltage necessary to turn on Q 50 can
be found by writing KVL for dashed path 3 of Figure
10.lb yielding
ViN = VBE,so(FA) + VBE,dFA) - Veu(SAT)
= 2VBE(FA) - VcE(SAT) = ViL
= VoH
With all inputs high, QI becomes reverse active. Q 52
and QsD are in saturation, which can be verified by
following dashed path 3 of Figure 10. lb yielding
ViN(high) > VHcso(SAT) + Vii£,s 2 (SAT) - Vc£. 1(RA)
With Q5 D in saturation, VH,s = VcE,so(SAT) and thus
Q5 and QO are cutoff. The output voltage is then
found by following dashed path 4 of Figure 10.lb
yielding
Vmrr = Vee - VH[.J'(FA) - V0 (0N) = V011
Voltage Transfer Characteristic
The voltage transfer characteristic for the standard
TfL AND gate is shown in Figure 10.ld for Vee =
TABLE 10.2 States of Each BJT and Diode
for Output Low and High Logic Levels
for 5408/7408 Standard TTL AND Gate
Element
Vc.s2 = VBE,o(SAT) + VBE,s(SAT) + Vo,s(ON)
VeE.l(SAT)
2VBr(SAT) - VeE(SAT) = V 111
0,
Os
Os2
OsD
Ds
op
DL
Ou
VoL
VoH
Saturation
Saturation
Cutoff
Cutoff
On
Cutoff
Cutoff
Saturation
Reverse active
Cutoff
Saturation
Saturation
Cutoff
Forward active
On (EOC)
Cutoff
10.1
TrL Jnd CJtes
BJTs for a two input Q1• The SPlCE input C!Rcuit file
for this circuit is as follows:
5 V. As mentioned earlier, the "knee" in the TfL
NAND gate of Chapter 7 is not present in the VTC
of the AND gate, and the transition region is more
abrupt. The states of each BJT and diode for the output low and high states of the TTL AND gate are
tabulated in Table 10.2.
Standard 5408/7408 TTL AND Gate
VCC 3 0 DC 5V
VINA 1 0 PULSE(OV 5V OS 1NS 1NS
+ SONS 100NS)
VINB 13 0 DC 5V PULSE(OV 5V OS
+ 1NS 1NS 100NS 20DNS)
QIA 11 2 1 QNPN
QIB 11 2 13 QNPN
QS2 10 11 12 QNPN
QS 4 9 5 QNPN
QSD 9 12 0 QNPN
QP 6 4 7 QNPN
QO 8 5 0 QNPN
-MODEL QNPN NPN(8F=100 IS=1E-1
+ 14A VA=80 RB=100HM RC=20HM
+ CJC=2PF CJE=4Pf)
DS 10 9 DIODE
DL 7 8 DIODE
DCA O 1 DIODE
DCB O 13 DIODE
-MODEL DIODE D(CJO=.SPF)
RB 3 2 4KOHM
Additional Inputs
As with the TTL NAND gate, more inputs can be
added by increasing the number of emitters in Q1•
Example 10.1 TTL AND
Gate SPICE Simulation
Using SPICE, perform a DC sweep to find the voltage transfer characteristic for the "TTL AND gate of
Figure 10.lb and Vc,sD as a function of the input voltage. Also, verify realization of the logical AND function by using two SPICE BJTs in parallel to simubte
the multi-emitter BJT Q1•
Solution Figure 10.2a shows a 5408/7408 standard
TTL AND gate with SPICE labelings and parallel
2KOHM
DS
~1-0-l>fg~
1Q
n+ 1
VINA@
A
11
11
QS2
2
2
n- O
*
~
13
QIB 11
12
VINB "~
1
_ DCA
0
~--~91
9
4
QS
5
DL
QP
f
12
DCB
RSD
5
0
RD
8000HM
0
(a)
FIGURE 10.2 TIL AND Cate: (a) With appropriate SPICE labelings
V
'r.~o;,=
QSD
13
0
127
0
1KOHM
128
Chapter 10/0thcr TTL Gates
5
5
4 --
34
2
1
3
0
0
25
I
I
I
I
I
I
'
50 75 100 125 150 175 200
► t(ns)
VIN,B(V)
t
5---.,1_ _ _ _ ___,
0-1---+...
0
-+ - +-·-+----+ -► VIN(V)
2
3
4
5
4
3
r
2
r
Ye.so (V)
1 -
'
0-+----+:--+:---;-....,-....:--+-,--*~ t(ns)
0
25
50
75 100 125 150 175 200
V AND(V)
•
I
5-'
I
4T _ _..,,
3 .. '
2:I
1~
0-1----+-:__.,,,,_*,--'i"'""""',-=~,-~,-~~ V IN(V)
0
1
2
3
4
5
(b)
0-+----+---+-------...-~ t(ns)
0
25
50
75 100 125 150 175 200
(c)
FIGURE 10.2 (continued) (b) Voltage transfer
characteristic and collector voltage of Qs 0 from .DC sweep,
(c) Transient response showing realization of logical
AND function from .TRAN sweep
RCS 3 10 2K◊HM
RC 3 4 1-bK◊HM
RCP 3 6 12D◊HM
RSD 12 D 8DO◊HM
RD 5 D 1KOHM
-DC VINA DV 5V □ - □ 1V
-PRINT DC VC(QSD) VC(QO)
-TRAN 10PS 200NS
-PRINT TRAN V(VINA) V(VINB)
+ VC(QO)
-END
The BJT and diode models are taken from the TrL
NAND simulation of Chapter 7.
rn.2
The VTC and Vc,su as a function of input obtained from the SPICE simulation are shown in Figure 10.2b. Note the output voltage rises simultaneously with the drop in the collector voltage of QsD·
Figure 10.2c shows the transient response obtained from the SPICE simulation. Note the output
is high for both inputs high and low for any input
low. Thus, the AND function for this gate is verified.
10.2 TTL NOR GATES
TTL NOR Gate Circuit
The NOR logic function can also be obtained from
TTL circuitry. Figure 10.3a shows the 5402/7402
standard TTL NOR gate. The logic symbol for this
gate is shown in Figure 10.3b. The NOR logic function is obtained by duplicating Q 1, Q 5 , and RB (shown
in the shaded region) with multiple Qs BJTs having
coupled collectors and coupled emitters. Both of the
Q 5 collectors are connected to Re and the base of Qp,
v!Nl! ~~21.
::l. . '.:_
n····•·.
·,'.-.'
...'"'.··.•,2··.·.,_•. •...
',QI)
•
Output High State
With both inputs low, both Q 1J\ and Q 1B are in saturation and both QsJ\ and QsB are cutoff, as is the
case with the single Q 1 and single Qs in the TTL
NAND gate (and inverter) as explained in section
7.5. With both QsA and Qsn cutoff, Q0 is cutoff and
QI' is at the edge of conduction. Hence, this gate is
in the output high state with
VouT = Vee - VB1,l'(FA) - Vn(ON) = V0 11
for both inputs low.
Output Low State
With either or both inputs high, the corresopnding
Q 1 is reverse active and the corresponding Q 5 is in
<il('~
--~-2<,"-•,.c.,
VNOK
-·-'---'----.:.....i
DCALS: 2s:Drn
J
·································:···-;·_
:
(a)
FIGURE 10.3
129
while both of the Qs emitters are connected to RL 1
and the base of Q( 1, as is the case with the single
drive splitter Q, in the TTL NAND and inverter
gates. Therefore, either Qs;\ or Qsn can activate Q 0
and force the output to the low state.
. ..•. ·.·...
. ,
TrL NOR Cc1tcs
5402/7402 Standard TTL NOR Gate: (a) Circuit schematic, (b) Circuit symbol
(b)
130
Chapter 10/0ther TTL Gates
saturation. Q, 1 is then in saturation giving an output
low voltage of
Input Low, Breakpoint, and Input High
Voltages = V 1L, Vm, and Vm
The input low and high voltages for the standard TTL
NOR gate are the same for either input and are the
same as that for the TTL NAND gate and inverter as
can be seen by writing KVL for either dashed path 1
or 2 in Figure 10.3a yielding
put high and low states as was done for the TTL
inverter.
Solution Both Inputs Low For both inputs low,
both input BJTs are saturated, both Qsi\ and QsB are
cutoff, Q 0 is cutoff, while Qp and D1, are at the edge
of conduction. There is current flow through both R13
resistors given by
I
(II) _ Vcc RHA
,
(5) - (0.8) - (0.2)
( k)
= 1.0 mA
4
=
_ Vee - VHE,lll (SAT) - VIN(low)
I /!BB (IL) R1w
The breakpoint corner found in the standard
TfL NAND gate is also present in the standard TTL
NOR gate. It has the same value as in the NAND
gate and is the same for either input:
ViB =
Vee - VHi:(SAT) - Vu(SAT)
Rirn
=
VBl_o(FA) + Viics(FA) - Vcu(SAT)
The breakpoint output voltage is also the same as
that found for the NAND gate and following dashed
path 3
Voll = Vee - Il<cRc - v/lE,P(FA)
(5) - (0,8) - (0.2)
(4k)
= 1.0 mA
The total current supplied by Vcc for both inputs low
is
Icc(LL)
Vr),L(ON)
= Vee - : : ViiE,o - VHc,r(FA) - Vn,L(ON)
R
Vee - Vn(SAT) - VcdSAT)
and
2VaE(SAT) - VcE(SAT)
(SAT) - VIN(low)
Ill\
ViL = VBl(FA) - VcE(SAT)
Viu =
Vi,1-,1J1
-
= IRBI\ (IL) +
= (1.0111)
11,m/IL)
+ (1.0111)
= 2.0
mA
Solution (ViNA == high, VINn == low) With V 1r-m
low, the current through R,m remains unchanged as
Additional Inputs
To increase the number of inputs to a TTL NOR gate,
additional combinations of Q 1, RB, and Qs are duplicated for each new input.
With V 1;s:A high, Q 1A is reverse active, Q 5 A saturated,
Q 0 saturated, and Qp and Dr. cutoff. The current
through R8 A is given by
I1,w1UH)
Example 10.2 TTL NOR Gate
Power Dissipation
Find the average power dissipated in the TTL NOR
gate of Figure 10.3a. Reviewing section 7.7 before
proceeding is recommended. Use VBE(FA) =
V8 c(RA) = V0 (0N) = 0.7 V, VBE(SAT) = 0.8 V, and
VcE(SAT) = 0.2 V.
Since the two-input TTL NOR gate has
four output states, the power dissipation must be
found as the average of the four separate combinations of inputs as opposed to the average of the out-
Solution
_ Vee - Vsc,1(RA) - VBE,sA(SAT) - VBi:,o(SAT)
RBI\
(5) - (0. 7) - 2(0,8)
= ---'-----'-------'----- =
(4k)
6 75 µA
With QsA and Q 0 saturated, the current through Re
is
Ii,c(OL) = Vee - Vo-,s/\(S~:) - Vm:, 0 (SAT)
=
(5) - (0.2) - (0.8)
(1. 6k)
= 2.5 mA
10.3
The total current supplied by Vee for V1:-.:A high and
V,:-.:H low is then
lccUIL)
= IR/J/\(IH) + I1wnUL) + IRc(OL)
(675µ,) + (1.0m) + (2.5m) = 4.175
=
Solution (ViNA == Low,
low the current through
/RB/\ (IL)
VINIJ
RBA
== High) With
mA
With V,"'B high, Qrn is reverse active and Qs 8 saturated, and therefore Q0 saturated. The current
through R1m is then
IRH/l(IH)
Vee - Viic,/RA) - VBE,S1\(SAT) - vllE,O(SAT)
(5) - (0.7) - 2(0.8)
(4k)
Comparing with Example 7.4, the average power dissipated in a TTL NOR gate is more than 70% higher
than that for the TTL inverter.
10.3
TTL OR GATES
TTL OR Gate Circuitry
= 675 µ,A
= l1w11 (IL) + l1wB(IH) + 11,c(OL)
(1.0m) + (675µ,) + (2.5111) = 4.175 111A
=
Solution (Both Inputs High) With both inputs
high, the currents through the two R8 resistors are
obtained as previously
and
= 675 µ,A
With both the Qs BJTs saturated and Q 0 saturated,
the current through Re is still
IRc(OL)
= 17.75 mW
Section 10.1 indicates that a TTL AND gate is obtained by including an extra level of inverting circuitry in the drive splitter section of the gate. The
previous section shows that a TTL NOR gate requires
duplication of the input section and a drive splitting
BJT, Q 1, R13, and Q 5 • Combining both of these modifications produces a TTL OR gate. Figure 10.4a
shows the circuit diagram for the 5432/7432 standard
TTL OR gate. The circuit symbol for this logic gate is
shown in Figure 10.4b. The circuitry contained in the
lightly shaded region is the duplicated input section
and the circuitry in the darker shaded region provides the additional drive splitter inversion.
The total current supplied by V cc for this state is
given by
I1wB(IH)
= (2.0111) + (4.175111) + (4.175111) + (3.85111) (5)
R1rn
The current through Re with either of the Q5 BJTs
saturated and Q0 saturated is the previously calculated value
Icc(LH)
lc-c(LL) + Icc(HL) + Icc(LH) + lcc(HH)
4
Vee
4
ViNA
is again
= 1.0
131
Pcc(nvg)
=
mA
TTL OR Cates
= 2.5
mA
Output Low State
To show that the OR gate of Figure 10.4a is in the
output low state for both inputs low, we must determine that Q0 is in saturation for this situation.
With an input low, the corresponding Q 1 is in saturation and the corresponding Q 5 (either QsA or Q 513)
is cutoff along with Qsu- With Q 5 u cutoff, the operation of Q 0 in saturation can easily be verified by
writing KVL along dashed path 1 in Figure 10.4a.
Thus, the output low voltage is
v()L
= VcE,o(SAT)
The total current supplied for both inputs high is thus
Icc(HH)
= IRB11(IH) + IRBB(IH) + JRc(OL)
= (675µ,) + (675µ,) + (2.5m) = 3.85
Output High State
mA
Solution (Average Power Dissipated) The average power dissipated by the TTL NOR gate is then
The output high state for either input high is now
verified. If an input is high, the corresponding Q1 is
reverse active and the corresponding Qs (either Q 5 /\
or Q5 R) is in saturation and Q5 u is also in saturation.
132
Chapter 10/0thcr TTL Gates
,l
Ra.3'120Q
l
"T'"'\
v.lNA
c-~~· Qu.
--- 2 -
\'----+--
------------------------l!----
DL
,
l;
f ~4- ..,.....
_ J-✓_)Q-~(l,_, VOR
I
"'l -
___±w_
1
~
~
1
(a)
INA~INB --L_/--F=A+B
(b)
FIGURE 10.4
5432/7432 Standard TTL OR Gate: (a) Circuit schematic, (b) Circuit symbol
This can be verified by writing KVL for either dashed
path 2 or 3 in Figure 10.4a. With QsD in saturation,
the base voltage of Qs[VB,s = Vc,so(SAT)] is insufficient to turn on Q 5 or Q 0 . With Q 5 and Q 0 cutoff,
Q 1, and DL operate at the edge of conduction. Hence,
the output high state is verified and the output high
voltage following dashed path 4 of Figure 10.4a is
given by
follows:
and
Vi11 =
2ViidSAT) - VcE(SAT)
Additional Inputs
As with the TTL NOR gate of the previous section,
additional input sections can be duplicated to increase the number of inputs.
Input Low and High Voltages
= V1L & Vm
·
The input low and high voltages for the TfL OR gate
of Figure 10.4a are the same as those for the TTL
AND gate presented in section 10.1. These are as
Example 10.3 TTL OR Gate Noise Margins
Calculate the noise margins for the TTL OR gate of
Figure 10.4a. Use VBE(FA) = V1ic(RA) = VD(ON) =
0.7 V, VBE(SAT) = 0.8 V, and VcE(SAT) = 0.2 V.
10.4
Solution (Critical Voltages) The critical voltages
for the TTL OR gate are found by direct substitution
into the equations derived in this section yielding
VOL = 0.2 V
V01 1 = (5) - (0.7) - (0.7)
mode of operation and the gate enters the output
low state.
=
With either VA AND V 8 bringing the output low or
Ve AND V 0 bringing the output low, the output pro-
3.6 V
vides a logical NORing of the input ANDings or
V0 U7
Solution (Noise Margins) The noise margins are
then calculated to be
= Vc)H -
VNML
=
133
Output is NO Ring of the ANDings
Vn = 2(0.7) - (0.2) = 1.2 V
Vin = 2(0.8) - (0.2) = 1.4 V
V."Jtvr1I
TTL Al'\JD-OR-lnvert (AO!) Gates
= (3.6) - (1.4) = 2.2
Vn - Vm = (1.2) - (0.2) = 1 V
V 111
V
= (VA AND V8 ) NOR (Ve AND Vo)
This is expected since single emitter input transistors
in TfL as in Figure 10.3 provide a NOR function output.
AND-OR-Invert (AOI) Terminology
TTL AND-OR-INVERT
(AOI) GATES
10.4
Referring back to the TTL NOR gate of Figure 10.3a,
single emitter BJTs are used for the input BJTs. The
opportunity to construct more complex logic functions using TTL circuitry exists if multi-emitter input
BJTs are used in place of the single emitter BJTs for
the input sections. Such a gate is the 5471/7471 standard TTL AND-OR-invert gate of Figure 10.5a. The
output of this gate is the logic function
Vmrr =AB+ CD
= NOT[(VA AND Va) OR (Ve AND V0 )]
The circuit symbol for this logic gate is shown in Figure 10.Sb.
This NORing of the ANDings is referred to as an
AND-OR-Invert (AOI) gate. That is AND the inputs,
OR the ANDings, and invert the ORing. Hence, the
TTL gate of Figure 10.5a performs the logical function
Vour = NOT[VA AND Vil) OR (Ve AND V0 )]
Recipe for Other Complex Logic Gates
From the logic techniques developed in this and the
preceding sections, other complex logic gates can be
constructed using the following general TTL circuit
design realizations:
1.
ANDing of signals is performed by multi-emitter
input BJT sections.
2.
ORing of signals is performed by multiple input
sections (Q 1 and R8 ) and multiple drive splitting
BJTs (Qs).
3.
If inverting of the ORing is not desired, include
the additional logic inversion circuitry.
4.
Always include the totem-pole output branch.
Input ANDing Sections
Recall from section 7.3 that input multi-emitter BJTs
are used in TfL circuits to provide ANDing of the
emitter voltages at the collector. The circuit of Figure
10.Sa has two multi-emitter BJTs for the input sections. Examining the input BJT labeled Q,i\ 13, the collector voltage is the logical realization VA AND VB.
Likewise the collector voltage of Q 1co is the logical
realization Ve AND V 0 .
Drive Splitter Section
The ANDing of the inputs provided by the collectors
of QrAB and Q 1co are then fed to the bases of the
drive splitters Qsi\B and Qsco• A high voltage at either the base of QsAB or Qsco will saturate that particular BJT. This in turn forces Q 0 into the saturation
Example 10.4 Non-Inverting Complex Logic
TTL Gates
Design a complex logic TTL gate that performs the
logic function
Vow = (VA AND Vil) OR Ve
OR (VD AND VE AND VF)
Solution (Input Sections) This gate will require
three input sections to accommodate the OR logic.
The first section consists of a double emitter BJT to
134
Chapter 10/0ther TTL Gates
1.6 kn
VINA'~-~
V !NB
~
)-----t----,
I
I
-:-
R,rnf .-:·
1 kn
-:-
j_
(a)
INA
INB
- -F=AB+CD
INCIND-
(b)
FIGURE 10.5
Four-input 5471/7471 Standard TTL AND-OR-invert Gate: (a) Circuit schematic, (b) Circuit symbol
perform VA AND V13, the second section is only a
single emitter BJT to accommodi.lte V c, and the third
section employs a triple emitter BJT to realize VD
AND VE AND V r-• The three input sections are shown
in separate shaded blocks in Figure 10.6a.
Solution (Multi Q 52 Inversion Section) As with
the TTL OR gate of Figure 10.4a, a second inverting
section with coupled additional drive splitter BJTs,
QszAB, Q 52 c, and Qs2DEF (one for each input section),
is fed by the input sections. These allow for a noninverted AND-OR logical output. These additional
drive splitter BJTs are shown in the middle of Figure
10.6a.
Solution (Drive Splitter Section) The standard
drive splitter section including Re, (the single) Q5 ,
and RD is now added directly after the middle splitter
section in Figure 10.6a.
Solution (Totem-Pole Output Section) Finally,
i.lt the output of the circuit in Figure 10.6a, the standnrd TTL totem pole branch containing Rel', QI', DL,
and Q0 is included ns in all other "TTL gates.
10.4
1TL AND-OR-Invert (AO!) Gates
135
r~c.'T/Qro
Du:_i
input section 2
inverting drive
splitter
(a)
INA=D
~~o
F=AB+C+DEF
INEINF(b)
FIGURE 10.6 Complex TTL (Non-inverting) AND-OR Gate rvour = VAo = (VA Af-JD Vs) OR Ve OR (VD AND VE
AND Vp)] of Example 10.4: (a) Circuit schematic (b) Circuit symbol
136
Chapter 10/Othcr TTL Gates
I
R~i
4·
.
...... .
···••··4w
Dec
input section 2
FIGURE 10.7 Six-input Complex 1TL AND-OR-invert
Gate of Example 10.5: V, ,ur = VAUi = NOT[ (VA AND
V11 ) OR Ve OR (Vil AND VE AND VF)]; Circuit of Figure
Example 10.5
Inverting Complex Logic Gate
Modify the gate of Example 10.4 in Figure 10.6a so
that the output is inverted and the gate realizes the
function
VoUT = NOT[ (V1, AND
ViJ
OR Ve OR (Vn AND Vr AND Vr)l
10.6a (Example 10.4) Modified by Removal of Second
Inversion Stage
Solution To invert the output of the circuit in Figure 10.6a the second inverting section between the
input sections and the drive splitter section in Figure
10.6 is removed. As a result, coupled drive splitter
BJTs must be used in the drive splitter section in the
same fashion as the TTL NOR gate of Figure 10.3a.
Figure 10.7 shows the modified gate with an inverted
105
TTL XOR Gates
137
7486 standard TTL XOR gate. The circuit symbol for
this logic gate is shown in Figure 10.86.
output. Careful study of this circuit leads to a good
understanding of TTL design principles.
XOR Input Section
10.5
TTL XOR GATES
Each input has an input section consisting of a single
emitter BJT Q1 and input base resistor R13 as in all
TTL input sections. In addition, each input section
also includes an inversion section similar to the sec-
An exclusive OR (XOR) gate is also provided with
modified TTL circuitry. Figure 10.8a shows a 5486/
(a)
:jD-F=AXORB=AEBB
(b)
FIGURE 10.8
5486/7486 Standard TTL XOR Gate: (a) Circuit schematic, (b) Circuit symbol
138
Chapter 10/0thcr 1TL Gates
ond inversion section of the TTL AND gate of Figure
10.lb. This is the circuitry in Figure 10.8a containing
Res,\, Qs 2!V Ds1v Rsoiv and QsDA for the first input
and RcsB, Q 5 :m, Ds 8 , RsDB, and Q 508 for the second
input. Note that the values for the Res and R50 resistors are smaller for the XOR gate than for the AND
gate. The net effect of the input section is to invert
the input voltage, which should be obvious since
each input section resembles an open collector inverter.
XORing Logic Pair
The XOR logic function is realized by the pair of BJTs
Qx 1 and Qx 2 in the middle section of Figure 10.Sa.
To show this, we consider each combination of input
logic states.
Both Inputs Low
With both inputs low, the nodes labeled VrN,\ and
VrNR are both high, since the input section acts as an
inverter. Examining the XO Ring logic pair, it is seen
that both the base and emitter of Qx 1 are high (and
should be at the same voltage) and Qx 1 is therefore
cutoff. The same is easily observed for Qx 2 .
With Qx 1 and Qx 2 both cutoff, Q 5 and Q 0 are
both in the saturation region of operation, as can be
seen by writing KVL for dashed path 1 of Figure
10.8a. Hence, the output voltage is in the low state.
Both Inputs High
When both inputs are high, the nodes labeled V 1NA
and V 1r--:B are both low and a similar situation arises
to the previous case. Since the base and emitter voltages of Qx 1 and Qx 2 are all at the same voltage
VcF.(SAT), Qx 1 and Qx 2 are again cutoff. Hence, Q 5
1'
Trip Voltages
Figure 10.9a shows a pair of input and inverting
output waveforms that demonstrate hysteresis.
Examining these waveforms, it is seen that the
output experiences a high-to-low transition
only when a rising input voltage initially
exceeds
V1N = Vw
Examples are shown at times t 2 and t8 in Figure
10.9a.
Furthermore, the output experiences a
low-to-high transition when a falling input initially drops below
such as at time t 5 •
The voltages Vm and V,u are referred to as
trip voltages and in order for hysteresis to occur, the condition
Vio > Viu
is required.
Good for Cleaning up Noisy Signals
Considering Figure 10.9a again, note that at
times t 1, t1,, and t 7, the input rises above Vn_; but
not above V1u and the output does not change
state. Likewise, at times t 3 and t 4 , the input falls
below V1u but not below V1u and the output
does not change. Therefore observing that V 1N
is extremely noisy, whereas VouT is not, we observe that a circuit exhibiting hysteresis is excellent for cleaning up noisy signals. Even the
spikes that occur at times t 1, t0 , and t 7 are not
sufficient to change the output.
Voltage Transfer Characteristic of Inverter
with Hysteresis
Tips, Tricks, and Gimmicks
Hysteresis and Schmitt Triggers
In the following section, a type of logic circuit
is described that has a different voltage transfer
characteristic for the output lzigh-to-low and
low-to-high transitions. Unlike the logic circuits
described previously, the output high-to-low
and low--to-high transitions occur at different
input voltages. This phenomenon is known as
hysteresis and the voltage transfer characteristic exhibits a "hysteresis loop."
Figure 10.9b displays the voltage transfer characteristic for a digital logic inverter circuit exhibiting hysteresis. This VfC indicates a highto-low output transition at an input voltage
higher than that at which the output low-tohigh transition occurs. Note the familiar hysteresis "loop."
Schmitt Triggers
Circuits that exhibit hysteresis are referred to
as Schmitt Triggers.
105
TTL XOR Gates
139
input rises above VID
- -input low-to-high trip point --
- --;-----input h/gh-to-low trip point- ------ \__ - ---- -, -
----- -,------
1\\
-+-~-+----~ --- -t~-i---j---~--•t
,
1
I
½
t,
t,
t.
I
t,,
t,
t,
input drops below V w
y OH - 1 - - - - -...
Your (Y)
Output low-to-high transition
YOH-
t
t
~Output high-to-low transition
/
t
VOL
Yru
(b)
FIGURE 10.9 (a) Input and inverting output voltage
waveforms for a circuit exhibiting hysteresis, (b) Voltage
transfer characteristic of a circuit exhibiting hysteresis; in
both (a) and (b) the output high-to-low and low-to-high
transitions occur at a different input voltage
140
Chapter 10/0thcr TTL Gates
and Q 0 are again saturated and the gate is in the
output low state.
VA '= Low and Vn '= High
With VJ\ low and VB high, the inverted nods V1NJ\ and
ViNH are high and low, respectively. The base-emitter
voltage of Qx1 is therefore low-high and Qx 1 is cutoff.
The base-emitter voltage of Qx 2, however, is highlow and Qx 2 is in saturation. The collector voltage of
Qx2, which is the base voltage of Q 5 , is found by
following dashed path 2 of Figure 10.Sa yielding
VB,S = VC,X2
= Ve[,SoB(SAT) + Vu,x2(SAT) < Viic,s(FA)
Hence, Q 5 and Q 0 are both cutoff and this gate is
seen to be in the output high state. Writing KVL for
dashed path 3 of Figure 10.Sa yields
VoUT
=
Vee - Viiu(FA) - V0 (0N)
=
Rcs 2, and RE. The block is reproduced in Figure
10.lla for analysis and resembles cascaded RTL inverters with a common emitter resistor. This block is
a noninverter.
Schmitt Trigger Output Low Voltage
Assuming V1Ns in Figure 10.lla is low, Q 51 is cutoff
and all current through Rcs 1 is diverted to the base
of Q 52 . Thus, Q 52 is in saturation and analysis of this
circuit in this state requires summing the terminal
currents of Qs 2 :
Substituting expressions for each of these terminal
currents in terms of VE yields
Vee - Vr: - Viir:(SAT)
Res1
+ Vee - V, - Ve1-(SAT)
Vo11
VA '= High and V8 '= Low
With VA high and V8 low, the inverted V,NA and
V,NB are low and high respectively. Hence, the baseemitter voltage of Qx, is high-low and Qx 1 is saturated. The base emitter voltage of Qx 2 is low-high
and Qx 2 is cutoff. Because of the circuit symmetry,
the gate is in the output high state as explained in
the previous sub-section.
With both inputs high or both inputs low, this
gate is in the output low state. If either input is high
and the other low, this gate is in the output high
state. Hence, the XOR function is indeed realized by
this circuit.
Res2
Collecting terms and rewriting yields
Vee - VHl:(SAT) + Vee - VeE(SAT)
Re~1
Rc.,2
Figure 10.10a displays a TTL Schmitt trigger NAND
gate. The circuit symbol for this element is shown in
Figure 10.106. The voltage transfer characteristic for
this circuit when connected as an inverter (V,NA =
V,Nll) exhibits hysteresis as shown in Figure 10.10c.
As explained in the previous Tips, Tricks, and Gimmicks box, circuits exhibiting hysteresis are useful for
cleaning up noisy signals.
Emitter-Coupled Schmitt Trigger
The sub-circuitry in Figure 10.10a that provides hysteresis is the shaded block containing Qsv Qs2, Res 1,
(-1- + _1_ + ~)v1-
=
Res1
Res2
Rr
Solving for VE yields
Vee - Va1-(SAT) + Vee - Vcr(SAT)
.
Res1
Res2
Vr = _____1_ _ _
1 ___
1 _ _ __
--+--+Res1
10.6 TTL SCHMITT TRIGGER
INVERTERS AND NAND GATES
Ve
R;
Rc,2
Rr
The output low voltage at You-rs, is one V 0 ,(SAT)
above the common emitter voltage and therefore
or
Vee - VM(SAT)
.
VuLs
+Vee
- -- -Ve,(SAT)
--~
Res2 __
= ---="--1_ _ _1 ___1_:_c_,:.__
Rc;1
--+--+Res1
Res2
Rr
+ Vu(SAT)
Schmitt Trigger Output Low-to-High
Transition Trip Point
If the input V,:-..:s in Figure 10.lla rises high enough,
Q 51 will enter the forward active region of operation
and current will be diverted from the base of Qs 2 to
lll.6
TTL Schmitt Trigger Inverters and NAND Gates
141
V ,x =5V
Rei,,>~
Ra
YouTS
DIA
VINA
V!NB
Dm
Du
Da
~___/
diode input section
BIT emitter coupled
Schmitt trigger
level
shifter
5400/7400 TIL totem pole
output and drive splitter
(a)
Yatrr(V)
4
YOH=
3
2
(b)
FIGURE 10.10 Standard TTL 5424/7424 Positive
NANO Schmitt Trigger: (a) Circuit schematic, (b) Circuit
...---------- Output high-to-low transition
3.6------------------
t
t
Output low-to-high transition
(c)
symbol indicating hysteresis in center of symbol,
(c) Voltage transfer characteristic showing hysteresis
142
Chapter 10/0ther TTL Gates
Yee= 5 V
V,ouiV)
, Output high-to-low transition
i
/
! t //
! t~
i-r
3-
Output low-to-high transition
VOLS= 1_9_2-- - - - - - - - - I-
(a)
(b)
FIGURE 10.11 Base Emitter-coupled Schmitt Trigger: (a) Non-inverting circuit, (b) Non-inverting voltage transfer
characteristic showing hysteresis
the collector of Qs 1 . Since Qs 1 is initially cutoff, the
input at which Q51 operates at the edge of conduction is V1Ns =VF+ VRF,s1(FA), where the value of VE
is that in the calculation of VoL• Thus, the input voltage V1Ns that causes the output voltage VouTs to go
up is
The voltage at the base of Q52 is then the output high
state value given by
'v\There the collector current Ic,s 1 is given by
lc,s1
=
VE
v/NS - VBE,s/SAT)
h:,s1 = -R
RE
E
Thus, substituting for Ic,s 1 yields
+ VBE,s1(FA)
Schmitt Trigger Output High Voltage
vVith V1Ns high, Qs 1 enters saturation and Q 52 is cut
off. With no current through Rcs 2, the output is
VO/rs= Vee
Schmitt Output High-to-Low Transition
Trip Point
Hence, referring to Figure 10.lOa with both ViNA and
V1Ns high, Q51 is in saturation, and Q52 is cutoff. The
emitter voltage of Q52 is thus
VE = ViNs - VBE,s1(SAT)
Va,s2 = Vee -
Rcs1
Rr: [VJNs - Vm/SAT)]
Subtracting VE, the base-emitter voltage of Q 52 is
Vee -
Rcs1
R
WrNs - Vm (SAT)]
0
E
- VJNs + Viii:(SA T)
Rearranging yields
(R;; + 1
+ (R;; + 1
1
VBE,s2 = Vee -
1
)VrNs
)vaE(SAT)
Hl.6
Finally, substituting VB1.s:2 = VtdFA) and solving for
V1Ns yields the input voltage necessary for Q52 to just
turn on as follows:
Vee
VINs
+
(R;;' + 1
)vBE(SAT) - VB1:(fA)
= --------------Res1
RE
Schmitt Trigger Inverters and NAJ'\JD Gates
put high and low voltages are those found in section
7.5. Also, the logic state at V~lur is inverted through
the drive splitter. Finally, note that the emitter-coupled Schmitt trigger input V,Ns of Figure 10.l0a is
one diode voltage above the inputs. This shifts both
trip points down by V0 (ON):
+1
= Vios
This is the input voltage Vms for which the output
high-to-low transition (the output goes down) occurs as shown in Figure 10.llb.
Emitter-Coupled Schmitt Trigger
Voltage Transfer Characteristic
The non-inverting voltage transfer characteristic
with hysteresis for the emitter-coupled Schmitt trigger of Figure 10.1 la is shown in Figure 10.llb.
5424/7424 Schmitt NAND Output Stage
Examining the circuit of Figure 10.l0a, it is seen that
the drive splitter and output branches are the same
as those for a standard TfL 5408/7408 inverter or
5400/7400 NAND gate.
5424/7424 Schmitt NAND Level
Shifter Stage
The branch in Figure 10.lOa consisting of Qu DL,
RLE, and RLc between the emitter-coupled Schmitt
trigger and the drive splitter is a 2VBE level shifter.
This is necessary so that the output of the emittercoupled schmitt trigger is appropriate for switching
the drive splitter between the output high and low
pull-up drivers.
Diode Input Section
Finally, it should be noted that the gate of Figure
10.l0a includes a multi-diode input section. This
provides ANDing.
Vm
= Vws
The voltage transfer characteristic of the 5424/7424
Schmitt trigger NAND gate of Figure 10. lOa exhibits
hysteresis in the same fashion as the simpler e1T1ittercoupled Schmitt trigger of Figure 10.lla with a few
exceptions. Since the output stage is that of the
Chapter 7 5400/7400 TfL logic family series, the out-
- VD(ON)
and
Vw = Vws - Vo(ON)
Note that V10 is shifted from Vrus and V1u from V105,
since this is an inverting Schmitt circuit. Figure
10. lOc shows the voltage transfer characteristic for
the Schmitt trigger of Figure 10.lOa.
TTL Schmitt Trigger
Example 10.6
Trip Points
Find the trip points Vrus and V 105 for the emittercoupled Schmitt trigger of Figure 10.1 la. Use resistor
magnitudes of Rc 51 = 4 kfl, Re52 = 2.5 kfl, and
REs = 1 kfl. Also, find the trip points for the NAND
Schmitt trigger of Figure 10.lOa for the same resistor
values. Use V8 E(FA) = 0.7 V, V8 E(SAT) = 0.8 V, and
VcdSAT) = 0.2 V for both cases.
Solution (Emitter-Coupled Schmitt Trigger
Trip Points) The trip points for the Schmitt trigger
of Figure 10.lla arc found by direct substitution as
follows:
Vius =
(5) - (0.8) + (5) - (0.2)
(4k)
(2.5k)
--------1
1
1
-+--+(4k)
(2.5k)
(lk)
+ (0. 7) =
2.5 V
and
(5) + [
~~~~
Vms =
+ 1] (0.8) - (0. 7)
(4k)
lk
5424/7244 Schmitt Trigger
Voltage Transfer Characteristic
143
= 1.66 V
+1
Solution (5424/7424 NAND Schmitt Trigger
Trip Points) The trip points for the corresponding
Schmitt trigger of Figure 10. lOa are therefore
Vio =
(2.5) - (0.7)
= 1.8 V
and
V1u
= (1.66) - (0.7) = 0.96
V
144
Chapter 10/0ther TTL Gates
10.7
TTL TRI-STATE BUFFERS
Output Driving Mode
When the input VEN in Figure 10.12a is high, the
right portion of the logic gate (labeled TTL AND
gate) operates as a non-inverting buffer between the
input V,~ and output VoL'l·
Circuit
In digital logic circuit applications, it is often necessary to connect the outputs of several logic blocks
together with the ability to select the logic signal that
will actually drive a common output. To achieve this,
it is necessary to have each logic block possess one
state in which both the output high pull-up driver
and output low pull-down driver are disabled. Such
a TTL circuit is shovvn in Figure 10.12a. This is a
54125/74125 TTL tri-state buffer. The circuit symbol
for such a gate is a modified inverter symbol as
shown in Figure 10.126.
Output High Impedance Z-state
When the enable input VE~ is low, both the output
pull-up and pull-down drivers are disabled and the
output is in a high impedance output state. This is generally denoted in truth tables as a Z-state.
High Impedance Z-Nodes Are Floating
A circuit node in a high-impedance Z-state is floating relative to all other voltages in the circuit. The
V,:;,:=5
V
,.. ~:
TILANDGate
Enable TIL Inverter
(a)
IN~OUT
EN
(b)
Figure 10.12 TTL 54125/74125 Tri-state (Non-inverting) Buffer: (a) Circuit schematic, (b) Circuit symbol
showing enabling input at bottom
10.7
TTL Tri-State Buffers
145
following conditions of high impedance Z-state
nodes cannot be under-emphasized:
Outputs of Several Tri-State Buffers
Can Be Connected Together
1.
Figure 10.13a shows a simple illustration of several
1TL tri-state buffer outputs connected to a single
node. The enabling inputs of all four tri-state buffers
are controlled by a 2: 4 decoder so that only one of
the enable signals will be high with the remaining
three enable signals low.
Figure 10.13b displays the case in which the enable line O is high and enable lines 1, 2, and 3 are
low. This situation equivalently represents the single
buffer TA driving the output node with the logic signal A T8, Tc, and TO are all in high impedance output
2.
3.
High impedance Z-state nodes are NOT at
ground
High impedance Z-state nodes are NOT at Vcc
High impedance Z-state nodes have NO driving
ability
The statement that best describes a node in a high
impedance Z-state is
A gate input cannot be driven by a node
in a high impedance Z-state
output of multiple
tri-state
buffers
connected to a
single node -------_ __
----- ---------( --'~\-~•<.
______
_,
A
C
1--------- -
-
-
I
TA
''
''
''
''
'
D
.
B
-r-T~m
'
'
----+I
~,, '- - - -
0
control
signals
1
2
3
2:4 decoder
only one tri-state buffer at a
time is enabled - thus, the
multi-driven node is never in
contention
(a)
FIGURE 10.13
(a) Outputs of several tri-state buffers connected to a single node
146
Chapter 10/0ther TTL Gates
driven by A
--z--~~~~-c
~.-
IC.,, low
AHN high:
TD
-~
-,'
g}
-~--~---
BHNlow
D
; DHNlow
Te
B-
1z-,-
'
·--
i
i.
t1
~
0
~
~
.Q
:E
.Q
.Q
1
2
3
__J_
control
signals
~ -0-
2:4 decoder
Te, Tc, and T0 are all in high
impedance output Z-states
(essentially
dis connected
from the output node) - TA is
operating as a buffer
(b)
FIGURE 10.13 (continued)
(b) Tri-state buffer TA is enabled; TB, Tc, and Tn arc all disabled
Z-states and act as open circuits between the common output node and B, C and D, respectively.
Circuit BUSes Utilizing
Tri-State Buffers
Tri-state buffers are often used to drive multi-bit circuit busses. A BUS is a set of wires that is used to
carry several sets of signals, one set at a time. Figure
10.14 shows an 8-bit bus BUS[7: 0] connected to four
sets of eight signals A[7:0L B[7:0L C[7:0L and
0[7:0]. The eight signals A[7:0] are connected to
eight individual tri-state buffers that are all connected to a single enable signal AEN· Each tri-state
buffer in turn is connected to a single line of
BUS[7:0]. Likewise, B[7:0L C[7:0L and 0[7:0] are
all connected to BUS[7: OJ through sets of eight tristate buffers, each set of eight buffers driven by a
single enabling signal. The advantage of using a bus
is the alleviation of huge multiplexors and corresponding wiring.
10. 7
TTL Tri-State Buffers
--- --·- ------·-<1~-·-
-
-
l
1
~-~~-•---"---
o_ -·
14 7
·---
-------~-
2
C[7:0]
A[7:0]
l
D[7:0]
B[7:0]
0
1
2
3
4
5
6
7
BUS[7:0]
FIGURE 10.14 8-bit Data Bus Driven By Four Register
Outputs; each bit of each register output has a single tristate buffer driving a corresponding bus line; ENA, ENB,
ENC, and END arc the enabling signals of register A, B,
C, and D drivers, respectively-one enable signal; at
most is high at any given time
148
Chapter 10/Othcr TTL Gates
CHAPTER10PROBLEMS
. 10.1
How is a TTL NANO gate modified to realize the
logical AND function?
10.2
What is the purpose of each clement in the standard TTL AND gate of Figure 10.2?
10.3
Determine the state of each BJT and diode for the
output low and high states for the standard TTL
AND gate of Figure 10.2 (in section 10.1) and draw
the voltage transfer characteristic for V,, == Vu. Use
V11 F(FA) == 0.7 V, V1dSAT) == 0.8 V, Vo(SAT) ==
0.2 V, and Vuc(RA) == 0. 7 V.
10.4
Find the average power dissipated in the standard
TTL AND gate of Figure 10.2 (in section 10.1). Use
V131,(FA) == 0.7 V, Vu 1,(SAT) == 0.8 V, Vc1(SAT) =
0.2 V, and V1ic(RA) = 0. 7 V.
10.5
Figure P10.5 shows a STTL 54S08/74S08 AND
gate. The second inversion section consisting of
Res, Q s1 , and Ds is simpler than that of the standard TTL AND gate. Determine the state of each
BJT and diode for this gate in the output high and
low states and sketch the VTC for V" = Vu.
10.6
What is the purpose of each element in the STTL
AND gate of Figure P10.5?
10.7
(a) Find th e ave rage power dissipated in the STTL
V, Vlll,(HARD) = 0.8 V, V0 ,(HARD) == 0.2 V,
V11 c(RS) = 0.3 V, V0 (ON) = 0.7 V, and
Vs1m(ON) = 0.3 V.
(b) Compare with the average power dissipated in
the STTL NANO gate obtained in Example 8.4 .
10.8
An LSTTL 54LS08/74LS08 AND gate is shown in
Figure P10.8. The second inversion section is sim ilar to th a t in the STTL AND gate with a higher
Res resistance. Determine the state of each BJT
and diode for this gate and sketch the VTC for
V,\ = Vu,
10.9
What is the purpose of each element in the LSTTL
AND gate of Figure P1Q.8?
10.10
(a) Find
AND gate of Figure P10.5. Use V1w(FA) = 0.7
the average power dissipated in the
LSTTL AND gate of Figure P10.8. Use Vm,(FA)
= 0. 7 V, Vu 1,(HARD) = 0.8 V, Vc1/HARD) =
0.5 V, Vuc(RS) = 0.3 V, V1iON) = 0. 7 V, and
Vsnr:,(ON) = 0.3 V.
(b) Compare with the average power dissipated for
the STTL AND gate found in Problem 10.7.
(c) Compare with the average power dissipated in
the LSTTL NANO gate obtained in Example
8.5.
Vcc=5V
0-
Rs~ 2.8W
nl
.
VINA
0--
I
FIGURE Pl0.5
Q
'
54S08/74S08 STTL AND Gates
Chapter 1ll Problems
149
DIA
.... I<I .,. . . ,. . . . . . . . . . . . . . . . . ,c,
D"'
FIGURE P10.8
54LS08/74LS08 LSTTL AND Gate
10.11
How is a TTL NAND gate modified to provide the
logical NOR gate?
10.12
Figure Pl0.12 shows a STTL 54S02/74S02 NOR
gate. Determine the state of each BJT and diode for
the output high and low states for this gate and
sketch the VTC for V" = V11 •
What is the purpose of each element in the STTL
NOR gate of Figure P10.12?
10.13
10.14
(a) Find the average power dissipated in the STTL
NOR gate of Figure Pl0.12. Use Vm/FA) = 0.7
V, VBI (HARD) = 0.8 V, Vc,(HARD) = 0.5 V,
V11 c(RS) = 0.3 V, V/)(ON) = 0.7 V, and
Vs1m(ON) = 0.3 V.
(b) Compare with the average power dissipated in
the STTL NAND gate found in Example 8.4.
(c) Compare with the average power dissipated in
the standard TTL NOR gate obtained in Example 10.2.
10.15
A 54LS02/74LS02 LSTTL NOR gate is shown in
Figure Pl0.15. Determine the state of each BJT and
diode for the output high and low states for this
gate and sketch the VTC for V" = VB.
10.16
What is the purpose of each element in the LSTTL
NOR gate of Figure Pl0.15?
10.17
(a) Find the average power dissipated in the
LSTTL NOR gate of Figure P10.15. Use
Vlll(FA) = 0.7 V, V8 dHARD) = 0.8 V,
VcE(HARD) = 0.5 V, VBC:(RS) = 0.3 V, VD(ON)
= 0.7 V, and V5 w(ON) = 0.3 V.
(b) Compare with the average power dissipated in
the LSTTL NAND gate of Example 8.5.
(c) Compare with the average power dissipated for
the STTL NOR gate obtained in Problem 10.4.
10.18
How is a TTL NOR gate modified to provide the
logical OR function? How is a TTL NAND gate
modified to provide the logical OR function?
10.19
Figure Pl0.19 shows the 54S32/74S32 STTL OR
gate. What is the state of each BJT and diode for
the output high and low states for this gate. Sketch
the VTC Use V8 E(FA) = 0.7 V, VB 1 (SAT) = 0.8 V,
VcE(SAT) = 0.2 V, and V8 c(RA) = 0.7 V.
10.20
Find the average power dissipated in the 5432/7432
standard TTL OR gate shown in Figure 10.4 (in
section 10.3). UseVB1 (FA) = 0.7V, VlllJSAT) = 0.8
V, Vc,(SAT) = 0.2 V, and V8 c(RA) = 0.7 V.
10.21
(a) Find the average power dissipated in the STTL
OR gate of Figure Pl0.19. Use V1ll:(FA) = 0.7
V, Vm(HARD) = 0.8 V, VcdHARD) = 0.5 V,
Vcc=5V
,---~-~- T
~
~
~133il ~
50
~
Re ff--9-00-n~----1/ Q,
v_T~\
r~
J
""
l
"
r·-()
VNO!t
"--~,-,--.'---~:-- -f/oo
5000
Ren ~ 2so n ·
,
·:✓/)
'1!
i
Q,
·,
L ,,,
· · · · · · · · · · · · · · · · · · · J ····-···1-..
FIGURE P10.12
54S02/74S02 SITL NOR Gate
RJ:::,-~r=
I
.
J
.
/n
R,,f20n
-
DIA
L.. _ _ __,
-·J<l
~-~
>--)
FIGURE Pt0.15
54LS02/74LS02 LSITL NOR Gate
150
o VN<lll
Chapter 10 Problems
151
V,x=5 V
900[2
FIGURE Pl0.19
54S32/74S32 STTL OR Gate
Vnc(RS) = 0.3 V, VD(ON) = 0.7 V, and
Vs1m(ON) = 0.3 V.
(b) Compare with the average power dissipated for
the STTL NANO gate found in Example 8.4.
(c) Compare with the average power dissipated in
the TTL OR gate obtained in Problem 10.20.
10.22
10.23
10.24
The 54LS32/74LS32 LSTTL OR gate is shown in
Figure Pl0.22. Note that this gate does not have
the pull-down diode between the base and emitter
of Qp that is found in the LS1TL NANO gate of
Figure 8.8.
(a) Find the average power dissipated in this gate.
Use V1i1o(FA) = 0.7 V, V1,io(HARD) = 0.8 V,
Vc 1(HARD) = 0.5 V, Vw(RS) = 0.3 V, Vl)(ON)
= 0.7 V, and V51 m(ON) = 0.3 V.
(b) Compare with the average power dissipated for
the LSTTL NANO gate obtained in Example
8.5.
(c) Compare with the average power dissipated in
the TTL OR gate obtained in Problem 10.21.
Sketch the VfC for the LSTTL OR gate of Figure
P10.22. Use Vn 1JFA) = 0.7 V, Vn 1JSAT) = 0.8 V,
Vc: 1JSAT) = 0.2 V, and V1w(RA) = 0.7 V.
The low power TTL (LTTL) 54L02/74L02 NOR gate
is shown in Figure Pl0.24. Note that the totem-
pole output deviates from the LTTL NANO gate
presented in Figure 7.8 in that the output high
driver has a Darlington pair and pull-down resistor
(as opposed to the standard TTL output high driver
made up of a single BJT and diode).
(a) Find the critical voltages and sketch the voltage
transfer characteristic.
(b) Find the average power dissipated in this gate
for two inputs.
(c) Compare with the average power dissipated in
the TTL NOR gate obtained in Example 10.2.
Use VidFA) = 0.7 V, VBE(SAT) = 0.8 V, Vc 1(SAT)
= 0.2 V, and VllC:(RA) = 0.7 V.
10.25
Figure Pl0.25 shows the high-speed TTL (HTTL)
54H11/74H11 three input AND gate.
(a) Find the critical voltages and sketch the voltage
transfer characteristic.
(b) Find the average power dissipated in this gate.
(c) Compare with the average power dissipated in
the TTL AND gate obtained in Problem 10.4.
Use Vn 1 (FA) = 0.7 V, VmJSAT) = 0.8 V, Vu(SAT)
= 0.2 V, and Vnc(RA) = 0.7 V.
10.26
The 5427/7427 is a three input standard TTL NOR
gate. Referring to the two input TTL NOR gate of
Figure 10.3, draw the three input gate. Include resistor values.
152
Chapter 1()/0thcr TI'L Gates
Vru,.
C>········,·····························k,l··············'································ •··i··································
FIGURE P10.22
54LS 2/74LS32 LSTTL OR Gate
20k-'l
VmA' ,.......... ,..............,
i
Ro~12W
<
FIGURE P10.24
54L02/74L02 LTTL NOR Gate
Chapter 10 Problems
Vcc":_,5V
\.,/
FIGURE Pl0.25
54H11/74H11 HTIL Three-input AND Gate
R,:,,
Vmc'~~
VIND
f"\
'llco
)---t-----1
-:-
-:-
FIGURE P10.30
54S51/74S51 STIL AND-OR-invert Gate
500
153
154
Chapter 10/Other TTL Gates
10.27
The 54LS27/74LS27 is a three input LSTTL NOR
gate. Referring to the two input LSTTL NOR gate
of Figure Pl0.15, draw the three input gate. Include
resistor values.
10.28
How arc TTL NOR gates modified to realize complex AND-OR-invert logic functions?
10.29
How are TTL OR gates modified to realize complex
AND-OR logic functions 7
10.30
The 54S51/74S51 STTL AND-OR-invert gate is
shown in Figure Pl0.30. Verify that this gate performs the logical function
10.32
The 5454/7454 standard TTL AND-OR-invert gate
is an eight input gate that performs the logical
function
VouT = AB
Referring to the four input TTL AOI circuit of Figure 10.5, draw the eight input gate. Include resistor
values.
10.33
The 54LS54/74LS54 LSTTL AND-OR-invert gate
is a ten input gate that performs the logical function
Vmrr = AB
Vin1T
10.31
+ COE + FGJ-l + If
= AB + CD
The 54LS51/74LS51 LSTTL AND-OR-invert gate
is shown in Figure Pl0.31. Verify that this gate performs the logical function
Referring to the four input LSTTL AOI circuit of
Figure Pl0.31, draw the ten input gate. Include resistor values.
Vour =AB+ CD
-:-
FIGURE 10.31
+ CD+ EF + GI-!
54LS51/74LS51 LSITL AND-OR-invert Gate
LOGIC
Another bipolar logic family is E111itter-Co11pled Logic
(ECL), which gets its name from a multi-transistor
emitter-coupled configuration. The emitter-coupled
configuration that is the basis of ECL is a current
switch analogous to an analog difference amplifier.
Output inverting BJTs are not used in ECL digital
circuits. The BJTs in ECL circuits therefore avoid the
saturation region of operation, operating only in the
forward-active and cutoff regions. However, unlike
Schottky TTL sub-families, ECL transistors are nonSchottky-clamped BJTs. Since ECL transistors are
non-saturating, additional circuitry for internal pullup (base-driving) and pull-down (discharge paths) is
not needed, thus reducing circuit design requirements.
The design improvements in ECL over TTL subfamilies result in an improved fan-out and the fastest
switching time of commercially available digital circuits. Typical propagation delay times are on the order of 1 ns, allowing for clock frequencies up to
1 GHz. 11,is improved performance is achieved at the
expense of the highest power dissipation of all logic
families, typically 25 mW per gate.
As will be seen, ECL has a smaller logic swing
than TTL sub-families. The smaller logic swing along
with the use of the emitter-coupled pair, which results in a constant current source and the avoidance
of a totem-pole output, eliminate current spikes inherent in TTL and results in a lower susceptibility to
noise.
This chapter introduces the ECL current switch,
a general ECL super-circuitry block diagram, and the
first commercially available ECL circuit, the MECL I,
developed by Motorola and commercially introduced
in 1962. The MECL I circuit has a 8 ns propagation
155
delay and flip flops constructed from MECL I circuits
toggle at a rate of 30 MHz.
11.1
BJT CURRENT SWITCH
Figure 11.1 shows the ideal BJT current switch. The
input is at the base of Q 1, with the base of QR held
at a constant reference voltage VBll· The coupledemitters are ideally connected to a constant current
source IEE· An early ECL implementation is shown
in Figure 11.2a, where a resistor RE is connected between the coupled-emitters and -VEE· The current
IRE is then given by
I RE
_ VE - (-VEE)
RE
-
where VE is the voltage at the coupled-emitters. Outputs are taken at the collectors of QI and Qiv giving
both an inverting and non-inverting output:
VINv
= Ve,1 = Vee - lc,1Re1
and
The states of the inverting and non-inverting
outputs are determined by whether the input voltage
VIN is less than or greater than the reference voltage
VIm• If VIN is less than V 88 (input low state), the inverting output VNOT is in the output high state and
the non-inverting output VNINV is in the output low
state. If VIN is greater than V BB (input high state) then
VNOT is low and VNINv is high. The states of the input
and outputs are tabulated in Table 11.1.
156
Chapter 11/Basic Emitter-Coupled Logic (ECL)
TABLE 11.1 States of Input and Outputs
for ECL Current Switch
f
Input
Input
State
Inverting
Output State
Non-Inverting
Output State
V1~ < Vim
V1~ > Vim
Low
High
High
Low
Low
High
11.2 ECL CURRENT SWITCH
VOLTAGE TRANSFER
CHARACTERISTIC
The logical NOT function for the inverting output
will now be justified. The basic ECL inverter of Figure
11.2a is considered throughout this section.
Output High Voltage
FIGURE 11.1
Basic ECL Current Switch
= Vott
With V1~ < V1m, Q 1 is off and QR is in the forwardactive region of operation. The current IRE therefore
flows entirely through QR· This can be verified by
solving for VHE,I· With QR forward active, the voltage
of the coupled-emitters is
Vr = VaB - VBu,(ECL)
VNINV
Q(SAT)
Yaa
(a)
FIGURE 11.2
Resistor ECL Current Switch: (a) Circuit, (b) Voltage transfer characteristic
(b)
11.2
Tips, Tricks, and Gimmicks
Special mention should be made of the VBE(FA)
magnitude used for ECL circuits. ECL BJTs are
physically smaller than the BJTs used in the
TTL sub-families. This leads to a larger baseemitter turn-on voltage. Experimental observation suggests using
= 0.75 V
VLllJECL)
Since ECL circuits are designed to avoid operation of the BJTs in the saturation region, this
value ofV13 E = V8 E(ECL) will be used throughout ECL circuit analyses in this and the following chapters for all active ECL BJTs.
ECL Current Switch Voltage Transfer Characteristic
157
Input Low and High Voltages = V1L
and Vrn
For V1r-.: slightly less than V,rn, Q, is forward active,
but not conducting as heavily as QR· For V,N slightly
greater than V,m, QR is still on but not conducting as
heavily as Q,. Furthermore, the transition width between V11 . and V,H is very narrow. Experimentally, the
transition width is found to be approximately Vnv =
0.1 V and centered about V1N = Vm,· Therefore, the
input low voltage, where Q1 turns on, and the input
high voltage, where QR becomes cutoff, are defined
as
ViL = Viw -
0.05 V
Vi11 = VBB +
0.05 V
and
Output Low Voltage = VoL
and
VBE,l
= VIN - VE = VIN - Viw + Vm(ECL)
Since V,N < V88, we have
VBE,l
=
VIN - Vaa
Thus, for V11':
Ic, 1 = 0 and
= low,
VINv
+ VBc(ECL) < ViiE(ECL)
As V1N is increased beyond V1L, Q1begins to conduct
and V1Nv = Vee - Ic, 1Rc 1 begins to decrease. When
V1N is increased beyond V1m, the coupled-emitter
voltage is
Q1 is cutoff. With Q, cutoff,
= Vee= Vo11
Threshold Voltage
=V
TH
When V1N = V138, Q, and QR are both active. The
current IRE is therefore shared by both Q1 and QR.
Assuming the base currents are negligible (i.e.
f3F >> 1),
Thus, raising V,N, raises Ve accordingly. However,
the base of QR is fixed at V8 ,R = V86 . Thus, raising
V1N by 0.05 V beyond Vsll decreases VBE,R sufficiently
to cutoff QR· The input at which QR enters cutoff is
defined as V1N = V111 and the output corresponding
to V111 is Vm. Since QR no longer conducts collector
current at this point, the input transistor collector
current Iu is given by
lc,1
= IRr =
VE - (-VFF)
R
··
E
VIN - Vi1E,1(ECL)
and the inverting output is
VINv = V cc -
IRE
2
RCI = V n 1 = V1w
As will be seen, with proper choice of RCJ, Rm, and
v,lB, the output voltage at the inverting
output is
That is, the output is also equal to V1m.
Va
Re
Substituting the expression for Ic, 1 into the inverting
output expression given by
RE, for v,N =
ViNvW1N = Vaa) = Vea
+
yields
158
Chapter 11/Basic Emitter-Coupled Logic (ECL)
where V1N = V 111 was substituted. Thus, the output
low voltage is dependent on the ratio Rei/RE as well
as Yee and VEE·
Solution The critical points are found by substituting directly into the expressions derived in this
section to obtain
V0/1 = 5 V
VIL = (2.6) - 0.05 = 2.55 V
Voltage Transfer Characteristic
Beyond Vm
V111 = 2.6
When V1N is increased beyond V1H, the collector current Ic, 1 is still given by
Ic 1
,
+ 0.05 = 2.65 V
(lk)
Vex = (5) - (lk) [(2.65) - (0.75) + (0)]
VIN - ViidECL) + Vi:£
= ---.:..:..:____.c.c::....c_---'------'=
= 3.10 V
Rr
tili
/'1 1;\
(5)
+ (0.6) +
and the output decreases linearly with V,N as follows:
1
VINv = Vee
[(0.8) - (0)]
(lk)
+ (lk)
= 3.2 V
Q, will eventually saturate with further increasing of
Vi,w(V1N = Vs) = (3.2) - (0.6) = 2.6 V
v,N- Beyond this point
VINv = VIN - VHc(SA T)
and the output increases with further increases of the
input. Simultaneously solving the two preceding
output voltage expressions [and replacing V1dECL)
with VfdSAT)] yields the input voltage at which Q,
saturates, V1N = V5 as
The corresponding output can be found by substituting V1N = Vs into either of the above output expressions. Note, however, that the region of operation where QR saturates is generally avoided.
Figure 11.2b shows the voltage transfer characteristics of the ECL current switch in Figure 11.2a.
The following example calculates the critical voltages.
The non-inverting output voltage transfer characteristic is also included in Figure 11.2b. Note that
Y:--: 1:--:v does not drop below VO1., since QR does not
operate in saturation. The more ideal output ofVN,NV
results because the base of QR is limited to (held at)
V,m, and QR is not driven hard enough for Y:--:,Nv to
drop below Vm. The determination of the VN,NV
voltage transfer characteristic critical points is left to
the reader (see Problem 11.8).
11.3
ECL SUPER-CIRCUITRY
Now that the operation of the current switch has
been explained, the ECL super-circuitry required for
optimum operation will be discussed. Figure 11.3
shows a block diagram of the ECL super-circuitry.
The individual portions are explained in the following sub-sections.
Current Switch
Example 11.1 EGL Current Switch
Voltage Transfer Curve
Hie operation of the basic current switch is identical
to that explained in the previous section.
Determine the critical points for the VTC of V1Nv for
the ECL current switch of Figure 11.2a. Let Vcc = 5
V, -VEE= GND = 0, Y88 = 2.6 V, and Rc 1 =Ro:=
RE = 1 kD. Also, use VBE(ECL) = 0.75 V and
V 1ic(SAT) = 0.6 V.
Multiple Inputs
Multiple inputs are accommodated by the use of additional input transistors with coupled collectors and
coupled-emitters. Additional inputs will realize a
1H
f
I
VINA
VIND
v!Nk
..
I
Current
Switch
Reference
Voltage
Network
v••
.
159
NonInverting
Output
Buffer
Inverting
Output
Buffer
VNOR
Basic ECL NOR/OR Gate
)
FIGURE 11.3
ECL Super Circuitry Block Diagram
NOR function at the inverting output and an OR
function at the non-inverting output. This is the topic
of the following section.
Reference Voltage Network
In the earlier (now obsolete) versions of ECL, the
reference voltage Vrm was simply supplied by an additional voltage source. However, these gates were
quite temperature-dependent, and exhibited extremely poor performance with temperature variations. A temperature-compensating voltage reference network was designed to eliminate this
problem. As will be seen in section 11.5, the temperature compensating reference voltage V,m is a
function of temperature and varies with the same
temperature dependence of the current switch,
providing an exceptionally stable temperature response.
isolates the connected gates at the output from the
driving gates and provides very high fan-out.
11.4
BASIC ECL NOR/OR GATE
By adding additional input transistors with coupled
collectors and coupled emitters to the ECL current
switch, as in Figure 11.4, the inverting output becomes a NOR output and the non-inverting output
V NOR
'
>-~---------<
Output Buffers
The outputs of the ECL current switch cannot efficiently drive even a few load gates. This is because
the current IoH available in the output high state cannot meet the ln 1 needed by any load gates. This problem is overcome by using emitter follower buffers as
output stages for the ECL current switch. The emitter
followers provide current amplification and have the
additional advantage of low output impedance. This
FIGURE 11.4
Basic ECL NOR/OR Gate
160
Chapter 11/Basic Emitter-Coupled Logic (ECL)
becomes an OR output. This is easily verified. Because RCJ is connected to the coupled collectors of all
input transistors, if any input transistor is active, the
corresponding collector current flows through Rei,
and VNoR is low. Hence, VNoR is high only if all in-
puts are low, cutting off all input transistors, which
satisfies the NOR logic table. For the OR output, if
any input is high, IRE will be supplied from the input
side of the current switch, cutting off QR· with Ic,R =
0, VoR is high.
Ra
3000
-1.175V
+IRE
·a----- ---3
RBJ 1.24ill
3
2
3
-VFJ',=-5.2 V
(a)
VNOR. VoR(V)
v•• = -1.175
-1.5
-1.0
Vs= -0.29
-0.5
•
---+'------+•--------- ► VIN (V)
-0.5
INA
INB
V
NOR
VNOR
-------vOH = -0,76
,~r-,
OR
1
: f-
--1.0
-----------j------v•• = -1.175
-1.5
-.0.1
(b)
vi
(c)
FIGURE 11.5 MECL I with Output Buffers: (a) Circuit, (b) Circuit symbol showing complementaiy outputs, (c) Voltage
transfer characteristic
11.5
Thus, this gate realizes both the logical NOR and
OR functions and
The ECL logic family provides the logical
NOR and OR operations
MECL l NOR/OR Gate with Output Buffers
161
TABLE 11.2 Purpose of Each Element
for MECL I Gate
Element
Qin
11.5 MECL I NOR/OR GATE
WITH OUTPUT BUFFERS
QR
As mentioned previously, output buffers are connected to the current switch to improve fan-out and
provide isolation from load gates. Figure 11.5a shows
the first ECL gate (in its NOR/OR form) to use output buffers, called MECL I, for Motorola ECL I. The
resistors RDN (NOR side) and R00 (OR side) are included to provide resistive loads for the emitter followers and passive pull down of the outputs. The
circuit symbol for this ECL gate with dual outputs is
shown in Figure 11.Sb. Since the outputs are the logical inverse of each other, they are referred to as complementary outputs.
The emitter followers (Q 8N and QBO) are used
for the output buffers and provide several advantages. First, the emitter follower configuration naturally provides a large sourcing current to a load with
a low output impedance. This gives ECL gates their
large driving capabilities and superior fan-out relative to other logic families. More importantly, the
large driving currents contribute exceptional switching capabilities. Also, the emitter follower provides a
voltage level shift between the BJT current switch
outputs and the NOR/OR gate outputs in the fashion
discussed in section 4.4 by introducing one baseemitter drop V8 E(ECL). This places the output voltage swing in a range compatible with the input voltage swing.
Unfortunately, the emitter followers also contribute a few disadvantages. The decreased switching
times are accompanied by large current spikes in the
emitter followers, causing voltage spikes at the corresponding collectors. As will be seen in the following chapters, this problem is compensated for by isolating the Vcc and VEE voltage supplies of the emitter
followers from the rest of the circuit.
The MECL I circuit configuration also shows unbalanced collector resistors Rei and Rm. This is because if more than one input transistor is on, the
current through Rc: 1 is greater in magnitude than the
current through Rm if QR is on. Hence, using a
smaller resistor for Rc 1 results in a VNOR for output
low approximately the same as that for Yew•
Rm
RCI
RE
QRN
QBO
RD:--:
Rno
Purpose
h
Input BJT for n' input, input side of emittercoupled pair
Reference voltage BJT, reference side of
emitter-coupled pair
Input side current switch collector resistor,
balances NOR side of circuit with OR side
Reference side current switch collector
resistor
IRE sourcing current resistance
NOR output BJT, buffered output
OR output BJT, buffer output
NOR output passive pull-down
OR output passive pull-down
Table 11.2 tabulates the purpose of each elen1ent
used in designing the MECL I circuit.
Vee= Ground and -VEE= -5.2 V
Most notable are the magnitudes of the voltage
sources. Vcc is at ground and -VEE has the peculiar
value -5.2 V, while V88 is -1.175 V. These values
are used in consideration of the design of the tern perature compensating network of the following
chapter. The reason the top of the circuit is at ground
is because the collector currents of the output buffers
vary widely, while the current-switch emitter current
IRE is fairly constant. Since ground voltage is more
stable then a power supply voltage, that is
d(GND)
d(Vn:)
dV
dV
--'----'- << - holding the top of the ECL circuit at ground and the
bottom of the circuit at a negative voltage less than
ground provides less ringing and less noise.
Table 11.3 lists the states of each BJT for the output high and low states.
TABLE 11.3 States of BJTs for Output High
and Low Logic Levels for a MECL I Gate
Element
VNoR(OH)
VNoR(OL)
Qin
QR
QBN
Quo
Cutoff
Forward active
Forward active
Forward active
Forward active
Cutoff
Forward active
Forward active
162
Chapter 11/Basic Emitter-Coupled Logic (ECL)
11.6 MECL I VOLTAGE TRANSFER
CHARACTERISTIC
lc, 1 is then found by following dashed path 3 (neglecting l1w:·J yielding
VrN - Vau(ECL) + VEE
The voltage transfer characteristic for the MECL I
NOR output is obtained in this section.
= VoH
Output High Voltage
With all inputs of the MECL I circuit of Figure 11.5a
low, all Q 1 are cutoff. The V NOR output voltage is
written by following dashed path 1 giving
VNOi,
= -Irl,lwRcr - VHE,l!N(ECL)
To obtain V0 L for the inverter, realizing that it is symmetrically located about Vmi, we use V1N = ViH• Substituting the expression for Ic, 1 into the expression for
V:-,.:oR with V1N = V11-l and V:-,.:oR = V01 _ yields
Vor_ -__ V111 - ViiE(ECL)
Re
+ Vff R _ V (ECL)
cr
BE
VNOR Saturation Region
Realizing that
The input voltage at which Q1 goes into saturation is
the same as found in section 11.2 with Vee= GND
the base current of Q11 N is written by following
dashed path 2 to obtain
l
1-r
=I
rr=--c,
.,
RE- - - - -
=
0,
Hence,
- Vi:c - ViiE,llN(ECL)
H,llN - Rcr + (f3r + l)RoN
Substituting IB,BN into the expression for VNoR yields
the output high voltage
VOii
= -
VEE - VBE:(ECL) Rcr - VaE(ECL)
Rcr + (f3r + l)RoN
Note that the first term in this equation is often negligible.
Input Low and High Voltages
=V
1L
In section 11.2, it was mentioned that the transition
width for the BJT current switch is very narrow, approximately 0.1 V. The input low and high voltages
were also indicated to be approximately symmetric
about the reference voltage V1313 • This is also the case
for the MECL I NOR/OR circuit. That is,
V11 _ = V 88
-
VnH
Output Low Voltage
+
Determine the logic swing, high and low noise margins, and noise immunities for the MECL I circuit of
Figure 11.Sa. Also, calculate V5 using V8 c(SAT) = 0.6
V. Use /3r = 49, VB1:(FA) = 0.75 V, V8 c(SAT) = 0.6V,
and Vm(SAT) = 0.8 V.
Solution (Critical Voltages) First, the critical
voltages are calculated from the expression derived
in this section:
(5.2) - (O. 75)
Vo11 = - (270) + [(49) + 1](2k) (270) - (0.75)
0.05 V
and
Vr11 =
Example 11.2 MECL I Critical Voltages
and Noise Margins
0.05 V
= VoL
If any input is high, the corresponding input BJT is
forward active. The collector current of this input BJT
then dominates the current through Rei, i.e. IB,BN
<< Ic, 1, The V NOR output voltage is obtained by again
following dashed path 1, where
V NOR = - lcrRcr - Viiuw(ECL)
-0.76 V
V11_
=
(-1.175) - (0.05) = -1.225
Vr11
=
-1.175 + 0.05 = -1.125
V
= _ (-0.76) - (0.75) + (5.2) (270) _ (0_ 75)
(1,24k)
OL
= -1.55 V
(~~;~i) [
(0.6) +
(0.8) - (5.2) l
Vs=---------l + (270)
(1.24k)
= -0.29 V
11.7
Note that the resistor values for Rc 1, R1., and RDN
position Vm 1 and V0 L approximately symmetric
about the reference voltage V1m = -1.175 V at each
output.
Solution (Logic Swing)
iv!ECL I
163
fan-l)Ut
The maximum fan-out of an ECL gate is therefore
dependent upon the output high state of the driving
gate. Hence,
TI.e logic swing is cal-
culated from
V1.s
=
Vc)H - Vc)L = (-0.76) - (-1.55)
= 0.79 V
Solution (Noise Margins) The high and low noise
margins are then calculated from
VNM/1
= Vo11 -
V111
= (-0.76) - (-1.125)
Your
= 0.365 V
VNML
=
Figure 11.6 shows a MECL I NOR emitterfollower output buffer connected to the inputs of
identical MECL I gates. All circuit elements and parameters for the load gates are distinguished with a
prime. Only the current switch portion of the load
gates are shown, since that is all that is needed for
fan-out analysis. For the determination of fan-out,
VIL - V01 = (-1.225) - (-1.55)
= 0.325 V
These noise margins appear to be relatively low compared to TTL logic circuits but arc acceptable for ECL
circuits. This is because of ECL's small logic swing.
Solution (Noise Immunities) Noting that Ytvt =
Yrm, the noise immunities for the MECL I circuit are
=
v;N
V
Yo!-1·
Input High Current
= Im
Examining Figure 11.6, the input high current is seen
to be
The current I{,i: in the load gate is
, _
1/ff -
(-0.76) - (-1.175)
(0.79)
= 0.53
=
v~ -
v;
(-Vi£)_
R'
-
v;E
+
R'
r:
[
and the voltage at the common emitters of the load
gate current switch is
and
(-1.175)
(-1.55)
(0. 79)
v;
=
v; ,\' -
VnE,/(ECL) =
VilE(ECL)
vll// -
Backward substitution yields the magnitude of
= 0.475 V
Output High Current
liH•
= Iott
The output high current is
Figure 11.5c shows the VfC of the MECL I circuit with Vcc at ground and -YEE at the negative
voltage -5.2 V. The VfC takes the same form as that
for the basic BJT current switch and appears entirely
in the third quadrant, since both input and output
voltages are negative. Verification of the Yem voltage
transfer characteristic, which is also shown, is left as
a homework exercise.
Io11
=
Ir:,nN(FA) - l1wN
The current through the resistor
I RON
RDN
is
_ Von - (-VEE)_ Vo11 + VEL
-
-
RoN
RnN
The forward active current through QBN is
h,1w(FA) = (/3F + 1)1/l,llN
11.7
Following dashed path 1 in Figure 11.6, the base current of QBN is
MECL I FAN-OUT
For ECL gates, no current flows at the inverter input
during the output high (input low) state. That is
In =
Ill,I(OJI)
= In,i(OFF)
= 0
I
_ I
ll,BN -
_ - Vou - V 8 c 1w(ECL)
RC/ -
R
Cl
Backward substitution then provides 1011 .
164
Chapter 11/Basic Emitter-Coupled Logic (ECL)
V'cc
Vee~
'~
Ra
2700
NOR
output
R'a
i
2700
-1.175 V
',,
V B
1
R'•
I
6
+r
RB
~ 1.24 kn
6
-V'88 =-5.2V
-V 88 =-5.2 V
output buffer of driving gate
current switches of N load gates
FIGURE 11.6 MECL I Gate Driving N Identical Gates for Fan-out Analysis of NOR Output (Note: the NOR
output is shown driving multiple loads)
VoH Is a Function of Fan-Out
The analysis for the maximum ECL fan-out calculation is not yet complete. When an ECL gate in the
output high state drives load gates, the output high
voltage decreases as more load gates are driven, that
is
and VoH decreases as additional gates are added.
Therefore, the expression for VoH derived in section
11.6 for a non-loaded gate cannot be used directly
here. This can be understood by examining Figure
11.6. Rather than the driving gate sinking current
from the input of the load gate, as is the case with
TTL gates, the input of the ECL load gate draws current from the output of the driving gate. When more
load gates are connected to the output of the driving
gate, more current is drawn from the collector of the
output BJT. If the collector current of Q 8 N is increased
by Alc, 8 :-.:, its base currf'nt is increased by 61 8 , 8 N =
6.lc, 8 :-.://h. This lowers the voltage at the base of QB!':
by 61 8, 8:-.:Rc 1 and therefore the emitter output voltage
also drops by 6.18 _8 NR 0 . Hence, the maximum fan-
11.8
out for ECL is calculated using a value of Vrn 1 slightly
lower than that found for the non-loaded gate. Quite
often this value is based upon the minimum tolerable
high noise margin= Vr--:MH·
Example 11.3 MECL I Fan-Out
Calculate the maximum fan-out for the MECL 1 gate
of Figure 11.Sa. Use the values of /3F = 49 and
VdECL) = 0.75 V specified in Example 11.2. Assume that the load gates have reduced Voll of the
driving gate from -0.76 V to -0.79 V.
MECL I hiwcr Dissipation
165
NOR Output High Current Supplied
= IEE (NOH) & Inn (NOH)
For the NOR output high state in Figure 11.5a, all
input BJTs are cutoff and QR is forward active. The
current through RE therefore comes from the emitter
of Q 1, and is given by
The currents through the output buffer pull-down
resistors are
Solution (Input High Current) Substituting into
the derived equations yields
Vi= (-0.79) - (0.75) = -1.54 V
(-1.54) + (5.2)
(l_ 24 k)
= 2.95 mA
If,t:
=
I'
= (2.95m) = 59 .. Ll
(49) + 1
Ill
,-,.,.,,
Solution (Output High Current)
l1wN
IB,BN
and
(-0. 79) + (5.2)
( k)
= 2.205 mA
2
-(-0.79) - (0.75)
=
270
= 148 µA
The total current sinked by -VEE for the NOR output
high state is then the sum
=
Iuw = [(49)
+ 1](148µ,)
=
7.4 mA
l0 u = (7.4m) - (2.2111) = 5.2 mA
Solution (Maximum Fan-Out)
N
?
(5.2111)
(59.4µ,)
NOR Output Low Current Supplied
= IEdNOL) & Inn(NOL)
For the NOR output low state, at least one of the
input BJTs is forward active (V1N = V01-1) and QR is
cutoff. The current through RE is therefore
= 87.5
Hence, the maximum fan-out for this gate is 87.
The currents through the output buffer pull-down
resistors are
11.8
MECL I POWER DISSIPATION
For the analysis of this section, the notation NOH and
NOL are used to denote the NOR output high and NOR
output low voltages, respectively.
To determine the average power dissipated in
the MECL I gate of Figure 11.5a, we determine the
sum of all currents sinked by -VEE for both the NOR
output high [IE1-:(NOH)] and low [IEE(NOL)] states.
However, the power supplied by V1m is negligible in
comparison. From these we determine the average
current supplied and multiply by -VEE·
and
The total current sinked by -VEE for the NOR output
low state is then the sum
166
Chapter 11/Basic Emitter-Coupled Logic (ECL)
Average Power Dissipated
= PEdavg)
Solution (NOR Output Low Currents) The NOR
output low currents are
The average power dissipated is then obtained by
substituting into
PEc(avg)
__ lr:E(NQH) + h;r:(NQL)
2
Example 11.4
Ve•[
,_
= 2.98 mA
MECL I Power Dissipation
IRno(NOL)
(-0.76) + (5.2) =
.A
222
( k)
· 111
2
IRm,(NOH) =
(-1.55) + (5.2)
( k)
= 1.825 mA
2
IEE(NOH)
(
2
+ (5.2)
k)
=
1.825 mA
(-0.76) + (5.2)
( k)
= 2.22 mA
2
=
frE(t-JOL) - (2.981/l)
+ (1.825111) + (2.2211l)
= 7.035 mA
Solution (Average Power Dissipated) The average power dissipated is then
PEE (avg) =
= 2.64 mA
=
(-1.55)
lm-JNOL) =
Find the average power dissipated in the MECL I
gate of Figure 11.Sa. Use VBE(ECL) = 0.75 V.
Solution (NOR Output High Currents) Direct
substitution of the element vaiues in Figure 11.5a
into the expressions derived in this section yields the
average power dissipated. The NOR output high currents are
(-1.175) - (0.75) + (5.2)
(1.24k)
l1mo(NOH)
+ (5.2)
(-0.76) - (0. 75)
(1.24k)
lRr(NOL) :::::
(6.685111) + (7.035111) ( )
.
5.2
2
= 35.6 mW
In the analysis of this section and in the previous
example, it was assumed that V01-1 and VoL were the
same for the NOR and OR outputs. This is not exactly the case, since Rc 1 is slightly less than Rm. A
= (2.64m) + (2.22111) + (1.825111)
= 6.685 mA
- -~n32
~ VCC"io DC OV
I
RCI t2700HM RCR ,300OHM
QBN
2
9
2
5
VNoR 0---
3
v2
QBO
I
n~
QIB
n+r:--~,QIA
10
:::Is
---0 VoR
7
7
RON ~INBn-To
3
VINA-
VBBtDC1~
RE ~ 1.24KOHM
l
·:1:~
-.--~;;,7------~}I ~·KOHM\
,a
2KOHMIL8 _ _ _ _ _ _-_ _
I
n+l a
VEEf DC5.2V
FIGURE 11.7
MECL I NOR/OR Gate with Appropriate SPICE Labelings
11.Y
more accurate calculation would require accounting
for the difference in output critical voltages.
11.9
MECL I SPICE SIMULATION
Figure 11.7 shows a MECL I NOR/OR gate with appropriate SPICE labelings. The SPICE input CIRcuit
file that represents this circuit is as follows:
MECL I SPICE Simulation
167
MECL I NOR/OR Gate
,OPTIONS NOMOD NOECHO NOPAGE
VCC 1 D DC DV
VEE D 8 DC 5-2V
VBB 6 D DC -1,175V
VINA 5 D DC -5,2V PULSE(-1,SV
+ - □ .7V OS OS OS 2SNS SONS)
VINB 4 0 DC -5,2V PULSE(-1,SV
+ - □ .7V OS OS OS SONS 1DDNS)
VJNA(V)
V NOR(V)
A.
-1.75
-LS -1._25 -L0-0._75 - 0 ~ - ~ - - ~
m
(V)
+-0.2
t:~:
· -0.8
-1.0
-1.2
-1.4
t-1.6
t-1.8
V0 .(V)
l
~-__,1.f--1s_-__,1_.s_-1_.2_s_-_,_1._o_-o-+--.1_s_-o_.s_-_o.+-2_s--1---------v!N (V)
-0.2
-0.4
0
f-----1-------'__J- ----+------+------1--1-------1-~ ► t(ns)
-0.25
10 20 30 40 50 60 70 80 90 100
-0.50
-0,75.,-.-.......
-1.00
-1.25
-1.50
VINB(V)
0 _,______,_____,_____,_
·--'--~---'---~---+------+---'---"-
t(ns)
-0.25- 10 20 30 40 50 60 70 80 90 100
-0.50
-0.75------1.00
-1.25
-1.50
0 --1------1-----1 ---+------'----+-----4-~'---_j________,________j_______.., t(ns)
-0.25
10 20 30 40 50 60 70 80 90 100
-0.50
-0.75 -1.00
-1.25 7\
-1.50 ___u,..__ _ _ _ _ _---1
-0.6
I
-0.8
-1.0
-1.2
-1.4
-1.6
-1.8
(a)
FIGURE 11.8 Results of Section 11.9 MECL I SPICE
Simulation: (a) Voltage transfer characteristics from .DC
V0 .(V)
0 --1-----+----+-~~--+-------'-'---+-----l----1--_________. t(ns)
-0.25
10 20 30 40 50 60 70 80 90 100
-0.50
-0.75-L,----------.
-1.00
-1.25- -1.50- (b)
sweep, (b) Transient response verifying NOR and OR
logical operations from .TRAN sweep
168
Chapter 11/Basic Emitter-Coupled Logic (ECL)
RCI 1 2 270◊HM
RCR 1 3 3000HM
RE 7 8 1-24KOHM
RDN 9 8 2KOHM
RD◊ 10 8 2KOHM
QIB 2 4 7 QNPN
QIA 2 5 7 QNPN
QR 3 6 7 QNPN
QBN 1 2 9 QNPN
QB◊ 1 3 10 QNPN
- MODEL QNPN NPN(IS=1E - 14 BF=49
+ BR=D-2 VA=80 TF=D-45NS
+ TR=SNS CCS=1PFD CJE=1-6PFD
CJC=O-SPFD RB=13 RC=b-2)
-DC VINA -1-75V OV 0-01V
-PLOT DC VE(QBN) VE(QBO)
-TRAN 1 □ PS 1DONS
-PLOT TRAN V(VINA) V(VINB)
+ VE(QBN) VE(QBO)
-END
+
Note that VI N A and V 1N 8 have DC default values of
-5.2 V to hold them low. This is because the default
DC value for a voltage source with no DC specificati on is ground (O V) . The VTC and transient response obtained from simulating this circuit are
shown in Figure 11 .8a and b.
CHAPTER11PROBLEMS
11.1
Determine the critical voltages for the non-inverting output of the ideal ECL current switch of Figure
P11.1 and sketch the corresponding VTC. Use Re,1
= Rc,R = 1 kD, and IEE = 3 mA.
11.5
Repeat Problem 11.3 for the ideal ECL current
switch of Problem 11.4.
11.6
Repeat Problem 11.2 for Vee = 0 V, V,m = -2.5 V,
Re, = 1.9 k.O, Rm = 2 kfl, and IEE = 1 .145 mA.
Use V~ 1,(ECL) = 0.75 V.
11.7
Repeat Problem 11 .3 for the ideal ECL current
switch of Problem 11.6.
11.8
Determine the critical voltages for the non-inverting output of the ECL current switch of Figure
Pll.8 and sketch the corresponding VTC.
Vcc=SV
1 ill
Ra
v!NV
VNINV
v••
·- - 0
V• o - ~
--,------,
2V
Rei
1 ill
Ra
VINV
VIN
o--~
-Vil!! =-5V
1 ill
VNINV
Q.
~l
V 88 =0
FIGURE Pll.1
11.2
Determine the critical voltages VcJH, Vrn , V,L, V,H,
and V5 for the inverting output of the ideal ECL
current switch of Figure P11.1. Use V81 (ECL) =
0. 75 V. Sketch the VTC.
11.3
For the ideal ECL current switch of Figure Pll .1, is
the output voltage swing centered about the reference voltage V81i?
11.4
Repeat Problem 11.2 for Re, = 500 n, Rm = 500
= 7.5 mA. Use VsE(ECL) = 0.75 V.
n, and IEE
FIGURE Pll.8
11.9
Determine the critical voltages VoH, V0 1_, V1L, V,H,
and V5 for the inverting output of the ECL current
169
Chapter 11 Problems
1-Ra
1
,__----~---
VNOR
290Q
------------<
O ·--
-VrIB = -5.2 V
FIGURE P11.13
switch of Figure P11.8. Use VnE (ECL) = 0.75 V.
Sketch the VTC.
11.10
What value of RE will center the output voltage
swing about the reference voltage for the ECL current switch of Figure P11.8 7
11.11
Repeat Problem 11.9 using Vee = 0 V, -VEE =
-5.2 V, Vsn = -2.3 V, Ru= Rm= 800 n, and RE
= 1.5 kfl. Use VBE(ECL) = 0. 75 V.
11.12
Repeat Problem 11.9 using Vee = 0 V, -VEt' =
-5.2 V, V,m = -1.175 V, Rn= Rm= 1.2 kD, and
RE= 3 kn. Use Vm(ECL) = 0.75 V.
11.13
Determine the voltage transfer characteristic VNoR
versus V,,\ for the ECL gate of Figure P11.13 and
treat all other inputs as low. Use VHdECL) = 0.75
V. Neglect the base current of the emitter follower.
11.14
the text. Draw the voltage transfer characteristic
using the solution of Problem 11.15.
11.17
Determine the fan-out for the ECL gate of Figure
P11.15 and assume that the high-level noise
margin is 0.2 V. For consistent answers, use Vu 1 =
-1.1 V.
For the ECL OR gate of Figure Pl 1.15, determine
the values Vrn 1 and Vm, Include the emitter follower base current and use V11 dECL) = 0.75 V and
/3, = 50.
11.16
For the gate of Problem 11.15, determine Vu, and
V,L using the approximate technique developed in
245
n
<Ji.a
For the ECL NOR/OR gate of Problem 11.13 with
RE = 2 kf!, determine the voltage transfer characteristic for VRti = -1.175 V. Use VB 1,(ECL) = 0.75
V. Additionally, include the base current of the
emitter followers for the high level of VNoR and
VoR• Use f3F = 50.
11.15
t
Rm
Q,
~
~
VaR
v,.
------0
-----0
-1.3 V
__J
Roo
RB
780Q
-VrIB=-5.2 V
FIGURE P11.15
21ill
170
Chapter 11/Basic Emitter-Coupled Logic (ECL)
11.18
For the circuit of Figure Pl 1.18, determine V, ,11 and
Vu 1, corresponding to V111 = -0. 7 V and V11 _ =
-2 V. Use VBE(ECL) = 0.75 V and f3F = 50.
11.19
Ycc=5V
,-~
II
Determine the fan-out of the ECL NOR/OR gate
of Problem 11.13. Assume that the load gates have
reduced V0 1-1 of the driving gate from -0.75 to
-0.79 V. Use f3r- = 50 and V11 dECL) = 0.75 V.
11.20
List the super-circuitiy elements that make up ECL
logic gates.
11.21
Determine the fan-out of the ECL NOR/OR gate
of Problem 11.14.
11.22
For the ECL gate of Figure Pll.13 determine the
average power dissipated.
11.23
For the ECL NOR/OR gate of Problem 11.14, determine the average power dissipated. Use the data
given in Problem 11.14.
11.24
For the ECL NOR/OR gate of Problem P11.15, determine the average power dissipated.
11.25
Repeat Problem 11.19 with V011 reducing to
-0.85 V.
Rei
i
220.Q
Ra.
II
I/
0---
3k.Q
-----·-
i
VINA
i
Q. ~VBB
--0
/
-1.3 V
~
"-,
-Vl!E = -5.2 V
FIGURE Pll.18
Qo
Votrr
--0
COMPENSATING
EMITTERCOUPLED
In 1964, Motorola introduced its second commercially available ECL sub-family called the MECL II.
Amongst its improvements over MECL I are propagation delays down to 4 ns with flip-flop toggling
frequencies up to 70 MHz. More importantly is the
inclusion of an internal bias network to replace the
need for the separate V88 bias voltage source. As will
be seen, this bias network was designed to compensate for temperature variations in the logic portion of
the circuit.
Modifications were made to some of the MECL
II circuitry to provide JK flip-flop toggle frequencies
of 120 MHz and D-type flip-flop toggle frequencies
of 180 MHz. These gates, while a part of the MECL
II sub-family, were often referred to as MECL II 1/2.
12.1 MECL II WITH TEMPERATURE
COMPENSATING BIAS NETWORK
example, the changes in these resistor values has the
effect of lowering both V011 and V01,.
Overall operation of this circuit is the same as
that for the MECL I and the purpose of each element
is tabulated in Table 12.1. In the following example,
the critical voltages and the voltage transfer characteristic are obtained by the methods of section 11.6.
Table 12.2 lists the state of each BJT for the output
high and low states.
Example 12.1 MECL II Voltage Transfer
Characteristic
Find the critical voltages (analyze the NOR output)
and logic swing for the MECL II gate of Figure 12.1.
Use f3F = 49, V8 E(ECL) = 0.75 V, and V8 c(SAT) =
0.6 V. Assume Vmi = -1.175 V.
Solution (Output High Voltage) In order to obtain the output high voltage, the current through Rei
for the output high state must first be found. Table
12.2 shows that all input BJTs are cutoff for the output high state, so the current through R0 is the base
current of QflN· Following dashed path 1 of Figure
12.1 yields
Figure 12.1 shows the MECL II NOR/OR gate, introduced by Motorola in 1966. This circuit contains a
major improvement to the MECL I circuit of the previous chapter in that a special bias network is used
to provide the V88 reference voltage so that a separate voltage source is not needed. As will be seen in
the next several sections, this bias network provides
a bias voltage that varies with temperature in a fashion that compensates for temperature variations in
output voltages.
In addition to the inclusion of the temperature
compensating bias network, resistor values have
been slightly modified. R0 has been raised to 290 fl,
RE lowered to 1.18 kfl, and RDN and RDo have been
lowered to 1.5 kfl. As will be seen in the following
I
- VEE - VBE,llN(ECL)
ll,BN - Ro + (f3F + l)RoN
(5.2) - (0. 75)
(290) + [(49) + 1](1.5k)
=
59
µA
Following dashed path 2 of Figure 12.1 then yields
Vou
= - In,1wRc1 - VBl,,BN(ECL)
(5.2) - (0. 75)
(290) + (49 + 1)(1.5/c) (290 ) - (0, 75 )
=
171
-0.77 V
172
Chapter 12/Ternperature Compensating Emitter-Coupled Logic
\ - - - - -..,,,,---.
temperature compensating bias network
-VEI!.::::-5.2 V
FIGURE 12.1
MECL II NOR/OR Gate with Temperature Compensating Bias Network
TABLE 12.1 Purpose of Each Element
for MECL II Gate
Purpose
Element
Input BJT for n input, input side of
emitter-coupled pair
Reference voltage BJT, reference side of
emitter-coupled pair
Input side current switch collector resistor,
balances NOR side of circuit with OR
side
Reference side current switch collector
resistor
IRE sourcing current resistance
NOR output BJT, buffered output
OR output BJT, buffered output
NOR output passive pull-down
OR output passive pull-down
Qin
QR
QB:S:
QBO
QB
Element
th
RE
QllN
QBR
Rl)N
Rno
Temperature Compensating Bias Network
QB
Rm 1
Du
DL 2
RBL
R111,
TABLE 12.2 States of BJTs for Output High
and Low Logic Levels for a MECL II Gate
Self-biasing BJT
Self biases Q8
Level-shifting diode 1
Level-shifting diode 2
Base bias resistor
Emitter bias resistor
VNOH
Cutoff
Forward
Forward
Forward
Forward
On
On
VNOL
Forward
Cutoff
Forward
Forward
Forward
On
On
active
active
active
Solution (Input Low and High Voltages)
As
D1.1
DL2
active
active
active
active
active
with the MECL I circuit of the previous chapter, the
input low and high voltages for the MECL II gate are
symmetric about the reference voltage V88 with a
very narrow output transition (V1H - V1L = 0.1).
Thus,
VIL = -1.175 - 0.05 = -1.225 V
V111
= -1.175 + 0.05 = -1.125 V
Solution (Output Low Voltage) The output low
voltage is found by assuming the input is driven by
12.2
another MECL II gate in the output high state (V1N =
V0 H)- First, the current through RCI for the output
low state must be obtained. Assuming the base current of Q 8 N is negligible compared to the collector
current of Q1, the Rc 1 current can be obtained by following dashed path 3 of Figure 12.l and using KVL
yielding
fc--,1(FA)
VBE,1(ECL) + VEE
V OH
= h,1(FA) = ------'-'--'-----RE
=
(-0.77) - (0.75) + (5.2) =
A
31
(1.18k)
. m
The output low voltage is then determined by following dashed path 1 with IRc = IciFA) and using
KVL yields
V0 1.
-lc,i(FA)Rc,1
VBE,BN(ECL)
= -(3.1111)(290) - (0.75) = -1.65 V
The input at which Q 1 enters saturation is obtained
using the following expression derived in section
11.2:
(0.6) +
(290)
(1.18k)
DC Analysis of the Bias Network
173
Solution (Logic Swing) The logic swing is therefore
VLs = VoH - VOL= (-0.77) - (-1.65)
= 0.88 V
The VIC for the MECL II gate with the critical voltages labeled is shown in Figure 12.2.
12.2 DC ANALYSIS OF THE BIAS
NETWORK
The DC analysis of the temperature compensating
bias network is quite simple. Figure 12.3 shows only
the bias network portion of the MECL II circuit. Following dashed path 1 of Figure 12.3 and neglecting
I8 ,B, the current down the branch containing Rm-i,
R8 L, and the two diodes is
lo= VEE - 2Vo(ON)
R1-u1
+
RaL
The voltage at the base of Q8 is therefore
Va.TB = -InRB11
(0.75 - 5.2)
-0.386 V
(290)
1
+ (1.18k)
VNOR, V 0 /V)
V00 = -1.175 Vs= -0.386
-1.5
-0.5
v•• 0-
VNOR
- - - - -----------i-VOH: -0,77
D1.2
-1.0
v•• = -1.175
:
R~i231 k1l
-1.5
VOL= -1.65
--0.1 V
~-
FIGURE 12.2 MECL II NOR/OR Gate Voltage
Transfer Characteristics
FIGURE 12.3
Bias Network
MECL II Temperature Compensating
174
Chapter 12/Temperature Compensating Emitter-Coupled Logic
Hence, the reference voltage Vfrn is one V11 E(ECL)
drop below the base voltage of QB or
V Bil
= - IDRB/1 -
Vil[,B (ECL)
VI:£ - 2V0 (0N)
-
- - - - - - RB11
RBI/+ RllL
VBr(ECL)
Calculate the DC voltage supplied by the bias network of the MECL II gate of Figure 12.1. Use VD =
, r
n----.rr \ __ n
V BE\C,'--L) -
r-"7r: ,
U. / J
r
V.
Solution Direct substitution of the resistor values
and BJT and diode junction voltages yields
VBB
Tips, Tricks, and Gimmicks
Temperature Independent
Expressions for V 0u and VaL
for EGL Gates with Output Buffers
Bias Supply DC Voltage
Example 12.2
1f
In the following section, the temperature-dependent expressions for Voi-1(T) and Vrn_(T) are
derived in terms of the temperature independent values (calculated at room temperature).
The temperature independent expressions for
V0 H(T 1J and Ym(T1J are the same as those for
MECL I obtained in section 11.6, and are repeated here for reference as follows:
V[E - Vm(ECL)
= - (5 -2) - 2 (0 ·75 ) (300) - (0.75)
(300)
+ (2.31k)
Ro
+
(f3r
+
l)RoN
R
°
- vllf(ECL)
-1.175 V
12.3 THE NEED FOR TEMPERATURE
COMPENSATION
Temperature Dependence of PN
Junction Forward Bias Voltage
Before showing that the bias network actually provides temperature compensation, it will first be
shown why temperature compensation is needed.
Figure 12.4 shows the equivalent circuit used to calculate the temperature-dependence of the NOR
logic half of the MECL II gate. This figure includes
voltage sources labeled l'.1VpN(T) in series with the
base-emitter PN junctions of the BJTs to represent
the temperature dependence of the PN junction forward voltages. The temperature dependence of a silicon PN junction forward voltage is measured as
L1 VPN(T)
=
(-2
1
:;)
X T
Note that for each °C rise in temperature,
duces by 2 mV.
~ VPN
re-
Temperature Dependent Output
High Voltage = VoH(T)
Considering Figure 12.4, for V1N =" low, Q1 is cutoff
and the output high voltage is found by following
dashed path 1 yielding
V,wm(T)
=
-Ii,.1w(T)Rc, - Vauw(ECL) - ~ VPN(T)
-VP£ =-5.2 V
FIGURE 12.4
Output Stage
Temperature Dependent MECL II
12.3
where the subscript NOH represents NOR output
high. The base current IB.BN(T) is found by KVL along
dashed path 2
(T) _ Vu: - VBr..BN(ECL)
6. vl'N(T)
1
B,BN
RC/ + (f3r + l)RoN
vEE -
Comparing this expression to the temperature-independent expression of VcJH(T,J given in the Tips,
Tricks, and Gimmicks box, it is seen that VNoH(T) can
be expressed in terms of Vor 1(T,J as follows:
VNo1-1(T) = Vo11(T1,)
-
1]
Thus, the change in VoH due to temperature variation is
= LiVrN(T)[
RC/
RC/ + (/3r + l)RoN
= - Li V1w(T)
+ l)RoN
+ (/3r + l)R1JN
(/3r
RCI
Since RDN is usually more than three time RCI, for
any reasonable ECL /3, this expression can be approximated by
Temperature Dependent Output
Low Voltage= V0 dT)
=
Again, considering Figure 12.4, for V,N
high, Q, is
forward active and VNoR = VNm is found by following dashed path 1 with the current through Re,, dominated by ICJ, Using KVL, we have
VNOL (T)
= - I c,/T) RC/
- VBE,BN (T) - Li VrN (T)
The collector current of Q, is obtained by following
dashed path 3 of Figure 12.4 yielding
I L,-1
= 11·., I =
VE - (-Vu:)
-=-RE- ' - - -
ViN(T) - VBr.,1(ECL) - Li VPN(T) + VE[
RE
VNoL(T)
=
_ V 1N(T) - V 8 E,1(ECL) - Li VrN(T)
+ VEER
ct
Assuming that this gate is driven by an identical
MECL II gate in the output high state and substituting v,N(T) = VNoH(T) = Vrn,(T,J + LiVNoH(T) =
Vm1(TR) - Li v,,N(T) yields
VN01(T)
- VBE,BN(ECL) - 6. VrN(T)
_c__c__ _ _
Backward substitution yields
- Vm:,1w(T) - Li Viw(T)
vBE.BN(ECL) - 6. vl'N(T) R
RC/ + (f3r + l)RoN
CI
+ Li Viw(T) _ _ _RC/
[ RC/ + (/3r + l)RoN
175
Re
Backwards substitution yields a temperature dependent expression for the output high voltage
_
The Need for Temperature Compensation
=
Vw1(TR) - LiViw(T) - VBr., 1(ECL) - LiVrN(T)
R[IRCI
+
- VBE,llN(T) - Li VpN(T)
As with the output high voltage, an expression for
VNm(T) in terms of VNm(T1J is obtained as
VNOL (T) = VNOL (T1,)
+ Li VPN(T) ( 2 RC/
Rr: - 1 )
This expression shows that a change in VNoL due to
temperature variation is given by
Li V NOL (T)
= Li VrN(T) (2 Rei
RE - 1 )
Problem Associated with Temperature
Variation of V0 ,!T) and V0 dT)
The problem that results because of the temperature
variation in VoH and Vm is that the output voltage
swing will no longer be centered about the reference
voltage VHB· The deviation of the average voltage
output due to temperature variation is
Li V
(T) ( ) _ Li VNot r(T)
NOR
avg -
+ Li VNOL (T)
2
and by substitution, we have
Li VNoR(T)(avg) = Li VPN(T)
(Re.
- 1)
RE
As was seen in the previous chapter, the magnitudes
of the emitter-coupled pair collector resistors and Rr.
arc specifically chosen so that VcJH and Vm are symmetric about V88 . Hence, if the output critical voltages vary with temperature, then the output voltage
swing will no longer exhibit the desired reference
voltage symmetry.
To accommodate for the output voltage temperature variance, a bias network that also changes with
Vff
176
Chapter 12/Temperature Compensating Emitter-Coupled Logic
temperature is necessary. The next section demonstrates that the ten,perature compensating bias network introduced with the MECL II circuit provides
the exact temperature compensation needed.
by following dashed path 1 in Figure 12.5 neglecting
the base current of Q 13 to obtain
ID(T) =
Vii: -
2V D(ON) - 2t:. Vl'N(T)
Rw1
12.4 BIAS NETWORK
COMPENSATION FOR
TEMPERATURE VARIATION
In section 12.2 we determined the DC voltage Vm1
supplied by the bias network of Figure 12.3. In this
section we determine the temperature dependence
of V13 B(T).
Figure 12.5 shows the equivalent circuit for calculating the temperature-dependence of the bias
network in Figure 12.3. The circuit of Figure 12.5 includes a t:. VPN(T) voltage source in series with the
base-emitter PN junction of Q 13 and a 2t:. VFN(T) voltage source in series with the two level shifting PN
junction diodes.
The temperature-dependent current IriT) in the
diode-resistor branch of the bias network is obtained
+
R1n
The temperature-dependent reference voltage is
then
Vim(T)
= - Io(T)RB11 - ViiuJN(ECL) - t:. Vi'N(T)
Vn: - 2V (0N) - 2t:.VPN(T)
- - - - - -0- - - - - - - ' - - Ru11
Ru11 + Ru1
- vlll,llN(ECL) - t:. VrN(T)
Recall that in section 12.2 the temperature independent expression for Vm/T,J was obtained as
VBu(Tg) = -
Vi:i - 2V0 (0N)
R
R
Ll/1 +
RL
RH// -
Vur(ECL)
CmTtparing these two expressions and expressing
V138 (T) in terms of V,m(T,J yields
Vu1/T) = V/l/1(TR)
Ru11
+ t:. vl'N(T) [ 2 - - - - 1]
RB11 + RuL
Hence, the temperature variation of V,m is
uV1w(T) = t:.Vl'N(T) [ 2 - Rau
- - - 1]
Rll/1 + Rill
Note that the temperature variation in Vlll3 has the
identical form of the average temperature variation
of the NOR output. The following example shows
that the resistor values of the logic and bias network
portions of the MECL II gate provide a compensating
temperature variance.
Example 12.3 Verification of Bias Network's
Temperature Compensation
Verify that the resistor magnitudes of the MECL II
gate of Figure 12.1 provide equivalent temperature
variations in the average output voltage and reference bias voltage.
Solution By direct substitution, the variation in average output voltage is
-VFE = -5.2 V
t:.VNOJ,(T)
(290)
= t:.Vl'N(T) [ (1.18k)
- 1
]
= -0.754t:. VPN(T)
FIGURE 12.5
Network
Temperature Dependent MECL II Bias
Also by direct substitution, the temperature variation
of the reference voltage is
12.6
Li V (T) = Li V (T)
B/3
PN
=
[2
(3
00)
(300) + (2.31k)
1]
12.5
177
Solution (Maximum Fan-Out)
(5.69111)
N:::; (
)
6 l.9f.L
-0.77M vl'N(T)
As can be seen, the temperature variation of the bias
network is only a few percent different than the temperature variation of the average output. Therefore,
as the average output of the MECL II gate varies with
temperature, the reference voltage due to the bias
network varies in almost direct proportion maintaining approximately temperature independent noise
margins.
Power Dissipation of MECL II
= 91.9
Hence, the maximum fan-out for this gate is 91.
Comparing with the fan-out for the MECL I gate
calculated in Example 11.3 it is seen that the fan-out
is improved slightly for the lower resistor values of
the MECL II gate.
12.6 POWER DISSIPATION
OF MECL II
FAN-OUT OF MECL II
The procedure for finding the maximum fan-out of
the MECL II circuit is identical to that for MECL I
presented in the previous chapter. The following example shows that the lower resistor values of the
MECL II (over the MECL I) provide a slight improvement in fan-out.
Example 12.4 MECL II Fan-Out
Calculate the maximum fan-out for the MECL II gate
of Figure 12.1. Use the values of f3F = 49 and
V8 E(ECL) = 0.75 V specified in Example 12.1 (and
Example 11.3). Assume that the load gates have
reduced Vm 1 of the driving gate from -0.77 V to
-0.8 V. Compare with the fan-out calculated for the
MECL I gate in Example 11.3.
Solution (Input High Current) Substituting into
the derived equations yields
Determining the power dissipation for the MECL II
circuit follows a procedure similar to that for the
MECL I circuit presented in the previous chapter.
The only difference is that the power dissipated in
the bias network is appreciable and must be included. As can be seen by examining the MECL II
circuit, the power dissipated in the bias network is
the same for both the output high and low states.
Temperature Compensated Bias
Network Power Dissipation= PTc
Neglecting the base current of Q 8 in Figure 12.3, the
current through R8 L and R8 H is found by writing KVL
along dashed path 1 yielding
IRBL
(3.09m)
IIIJ = (49) + l = 61.9 µA
+
RBL
The current through R8 E is obtained by writing KVL
along dashed path 2 of Figure 12.3. This current is
I
. _ Vu: - IRBHRBu - VBr:, 8 (ECL)
RllE -
,
I
2V0 (0N)
VEE RBI/
V~ = (-0.8) - (0.75) = -1.55 V
(-1.55) + (5.2)
In =
(l.l 8 k)
= 3.09 mA
_
-
R
BE
The total current delivered to the -VEE voltage
source through the bias network is the sum
Solution (Output High Currents)
IRoN =
IBBN
'
+(0.8) - (0.75)
=
= 172 µA
270
h.aN =
IoH
(-0.8) + (5.2)
(l. k)
= 2.93 mA
5
[(49) + 1](172/.L) = 8.62 mA
= (8.62m) - (2.93111) = 5.69 mA
NOR Output High Current Supplied
IEE(NOH)
=
The NOR output high currents IRE(NOH),
IrmN(NOH), and I1m 0 (NOH) were found in the previous chapter for the MECL I gate and are identical
for the MECL II circuit. Repeating these, we have
178
Chapter 12/Ternpcraturc Compensating Emitter-Coupled Logic
[, (NOH)
Solution (Bias Network Currents) First, the
power dissipated in the bias network is obtained
substituting into the derived expressions yielding
= ViJB - Viiu,(ECL) + ViL
R[
k[.
l1wN(NOH) = VOf~+ VEE
(5.2) - 2(0. 75)
(300) + (2.31k)
DN
I1wo(NOH) =
VoL
+
R
l1wL =
VEE
DO
I1m
The total NOR output high current to -VEE is then
the sum of these and the current through the bias
network:
=
=
1.42 111A
(5.2) - (1.42m)(300) - (0.75)
(2k)
= 2.01
111A
Summing, yields the total power dissipated in the
bias network:
!Tc
=
(1.42111) + (2.01m)
= 3.43 mA
Solution (NOR Output High Currents)
The
NOR output high currents are
NOR Output Low Current Supplied
IEiNOL)
=
NOH) _ (-1.175) - (0.75) + (5.2) _
I RE (
(1.18k)
- 2.78 111A
The NOR output low currents IRE(NOL), 11w1':(NOL),
and IR 1)0(NOL) were also found in the previous
chapter for the MECL I gate and are identical for the
MECL II circuit. These are
I,w,\•(NOH)
=
I1w 0 (NOH)
=
(-0.77) + (5.2)
(l. k)
5
(-1.65) + (5.2)
(l. k)
5
=
2.95 mA
= 2.37 mA
The total output high current is then
IIE(NOH) = (2.78111)
+ (2.95111) + (2.37111)
+ (3.43m)
= 11.5 mA
Solution (NOR Output Low Currents) The outThe total NOR output low current to -VEE is then
the sum of these and the current through the bias
network. Thus
IEE(NOL)
= IRr:(NOL) + 11wN(NOL)
+ IRoo(NOL) +
ITc
Average Power Dissipated= PEE(avg)
The average power dissipated is then found by substituting into
put low currents are calculated to be
IR[(NOL) =
I1m,-(NOL) =
I1w 0 (NOL)
=
(-0.77) - (0.75) + (5.2)
(l.l k)
= 3.12 mA
8
(-1.65111) + (5.2)
(l. k)
= 2.37 111A
5
(-0. 77) + (5.2)
(l.Sk)
= 2.95 mA
The total output low current is then
+ (2.37m) + (2.95111)
+ (3.43111)
b(NOL) = (3.12111)
= 11.9 mA
Solution (Average Power Dissipated) The avMECL II Power Dissipation
Find the average power dissipated for the MECL II
gate of Figure 12.1. Use V8 E(ECL) = V0 (ON) =
0.75 V.
Example 12.5
erage power dissipated is then found by
Pu: (nvg)
=
(11.5111) + (11.9111) ( )
5.2
2
=
60.8 mW
12. 7
179
MECL II Spice Simulation
~ J~vcC$ocov
2
11
3
2
QBN
3
9
QBO
10
2
4
VNOR
QIB
n+ 4
~INB"±
RDN
2KOHM
7
±
2
5
QR
n+ 5
11
QB
3
_6
11
6
VaR
DL1
7
VINA
DL2
6
_
RBE
•
RE
8
1.24KOHM
2KOHM
RBL
10
RDO
2KOHM
2.31KOHM o
n+ 8
VEE
-r. DC 5.2V
n-1
O
_L
FIGURE 12.6
12.7
MECL II NOR/OR Gate with Appropriate SPICE Labelings
MECL II SPICE SIMULATION
Figure 12.6 shows a MECL II circuit with appropriate
SPICE labelings. The SPICE input CIRcuit file that
represents and simulates this circuit is as follows:
MECL II NOR/OR Gate
.OPTIONS NOMOD NOECHO N◊PAGE
VCC 1 D DC DV
VEE D 8 DC 5-2V
VINA 5 D DC -5-2V PULSE<-5-2V
+ DV OS 2NS 2NS SONS 10DNS)
VINB 4 D DC -5-2V PULSE<-5-2V
+ DV OS 2NS 2NS 1DONS 2DONS)
RCI 1 2 270◊HM
RCR 1 3 3000HM
RE 7 8 1-24KOHM
RDN 9 8 2KOHM
RD◊ 10 8 2KOHM
QIB 2 4 7 QNPN
QIA 2 5 7 QNPN
QR 3 6 7 QNPN
QBN 1 2 9 QNPN
QB◊ 1 3 10 QNPN
RBH 1 11 2900HM
RBL 13 8 2-31K◊HM
RBE 6 8 2KOHM
DL1 11 12 DIODE
DL2 12 13 DIODE
QB 1 11 6 QNPN
-MODEL QNPN NPN<IS=1E-14 BF=49
+ BR= □ -2 VA=80 TF=0-4SNS
+ TR=5NS CCS=3PfD CJE=7-6PFD
+ CJC=3PFD RB=13 RC=b-2)
-MODEL DIODE D(VJ=D-75)
,DC VINA -5-2V DV □ -1V
,PLOT DC V(9) V(10)
-TRAN 2NS 250NS
-PLOT TRAN V<VINA) V<VINB)
+ VC(QBN) VC(QBO)
-END
As with the MECL I simulation of the previous chapter, VINA and V1NB have DC default values of -5.2 V
to hold them low. The VIC and transient response
obtained from simulating this circuit are shown in
Figure 12.7a and b.
180
Chapter 12/Temperature Compensating Emitter-Coupled Logic
.
YmiY)
-1.75-1.5-1.25 -1.0-0.75-0.5-0.25
-- --+ ----l---r--+-----t----1---+--
-- ---
Vm (V)
-- ►
-0.2
- -0.4
-0.6
7
-'--0.8
0-----t-+---+---+---,--~----¼ t(ns)
-0.25- 10 20 30 40 50 60 70 80 90 100
-0.50-0.75-:---1.00--i--1.25 _j__
-1.50--'-VINB(V)
...
t-1.0
-1.2
0 -+----"--i----+---+-----1-+----l-------l--+--~------ t(ns)
-0.25---l-- 10 20 30 40 50 60 70 80 90 100
-0.50---'--0.75---'- - - - - -1.00-1.25 -1.50-
-1.4
--1.6
-1.8
VNOR(V)
...
'
-1.75-1.5-1.25 -1.0-0.75-0.5-0.25
Vm(V)
O---''-+----+---+----+-+---+---+--------½ t(ns)
-0.25-;- 10 20 30 40 50 60 70 80 90 100
-0.50--,---
----+---+-----+--+---+-----+---+-----+-----
-0.2
-0.4
-0.6
I
-0.8
-1.0
-1.2
-1.4
-1.6
-1.8
Yaa(V)
0 --++-+----+----+-+---+--~-'--+---+- -1---+ t(ns)
I
-0.25T 10 20 30 40 50 60 70 80 90 100
-1.25
-1.50
(a)
FIGURE 12. 7 Results of Section 12. 7 MECL II
NOR/OR Gate SPICE Simulation: (a) Voltage transfer
characteristics of NOR and OR output from .DC sweep,
----------.l
-o.50+
-o.15f-1.00
--(b)
(b) Transient response verifying realization of NOR and
OR logic functions from .TRAN sweep
CHAPTER12PROBLEMS
12.1
12.2
Analyze the temperature compensating reference
voltage circuit of Figure P12.1 to determine the
base voltage V8 and reference voltage Vrm• Neglect
the base current and use VrdECL) = 0. 75 V.
Repeat Problem 12.1 with RBL = 5 kn.
12.3
For the circuit of Figure P12.1, select a value for RBI_
which provides a reference voltage V1m = -2 V.
12.4
Determine the critical voltages Vo 11 , Vm, V1u V111,
and Vs for the OR output of the MECL II gate of
Figure 12.1. Use V1qo(ECL) = 0.75 V and neglect
base current.
Chapter 12 Problems
R""
3000
181
3500
RBH
Q.
v•. 0--
v••
Du
DLI
Du
Du
RBB
2 ill
RBB
RBL
-VBB =-5.2 V
FIGURE P12.13
FIGURE P12.1
Determine the critical voltages Vo 11, Vm, V1L, V1H,
and Vs for the OR output of the MECL II gate of
Figure 12.1 with Rc,R = Rc,1 = 600 n. Use Vs1/ECL)
= 0. 75 V and neglect base current.
12.6
Determine the critical voltages Vrn 1, V0 u V1L, Vni,
and Vs for the OR output of the MECL II gate of
Figure 12.1 with RE = 3 kn. Use VsE(ECL) = 0.75
V and neglect base current.
12.7
Determine the fan-out for the NOR output of the
MECL II gate of Figure 12.1 for V011 reduced by 0.1
V. Use VsdECL) = 0.75 V, VsE =vi)= 0.75 V, and
/3F = 49.
12.8
12.9
Determine the fan-out for the MECL II gate of Figure 12.1 with Rc. 1 = Rc,R = 600 n for V011 reduced
by 0.1 V. Use VsE(ECL) = 0.75 V, VHE =vi)= 0.75
V, and f3F = 49.
Determine the fan-out for the MECL II gate of Figure 12.1 with RE = 500 n for Vrn, reduced by 0.1
V. Use VBl,(ECL) = 0.75 V, VsE =vi)= 0.75 V, and
f3F = 49.
Repeat Problem 12.13 with Rs1 1 = 907
4.98 kn, and RBE = 6.1 kn.
12.15
Repeat Problem 12.13 by running a .DC analysis
using SPICE and the circuit of Figure P12.15.
RBH
3500HM
0
11
QB
V BB
0-------- 6
DL1
12
6
RBE
2KOHM
out
13
RBL
8
For a MECL II inverter similar to Figure 12.1, determine the average power dissipated.
8
12.11
For the MECL II gate of Figure 12.1 with RoNo =
RoNN = 3 kn, determine the average power dissipation.
VEEtDC5.2V
For the MECL II gate of Figure 12.1 with RE
=3
kn, determine the average power dissipation.
12.13
Determine the voltage V88 for the circuit of Figure
P12.13.
n,
12.14
12.10
12.12
1.958 ill
RBL
-VBB = -5.2 V
12.5
2ill
2.31 ill
n+ 8
FIGURE P12.15
1.958KOHM
RsL
=
13
MECL III
AND ECL 10K
In 1968 Motorola introduced a third family of ECL
logic referred to as the tv1ECL III logic faiTdly. This
logic family reduced the resistor values used in
MECL II improving the fan-out and dynamic response. Rise and fall times on the order of 1 ns are
attainable and flip-flop toggling rates of 500 MHz are
possible. With the 1 ns edge speeds, all but the
smallest systems require a transmission line environ ment and MECL III outputs are designed to drive
50 D loads. Multi-layer boards are recommended for
toggling rates above 200 MHz. Pull-down resistors
are included at each input so that unused inputs no
longer need to be tied to -VEE· Also, the output pulldown resistors have been removed to lower the
power dissipation.
In 1971 a slower version of the MECL llI family
referred to as the ECL lOK (or 10,000) series was
made commercially available. The circuit is schematically identical to that of the MECL III but with
larger resistor values. These larger resistor values
were intended to slow down the edge speeds to approximately 3.5 ns (- 1 µ,V/s, about 80% of that for
STTL) to make the newer ECL circuits more applicable. This minimizes ringing and reflection on interconnecting wires as well as reducing cross talk.
Thus, wire wrap applications and printed circuit
board utilization are possible with the ECL lOK series. The ECL lOK series was also used in large mainframes and high performance control and test systems. The larger resistor values also reduce the
power dissipation to about 25 mW/gate, or about half
of that for the MECL III gates.
13.1
Removal of Output Pull-Down
Resistors
The output pull-down resistors RDN and RDo present
in the MECL I and MECL II families have been removed, since their presence is not necessary for logic
operation. Removal of these resistors contributes to
a lower power dissipation, since they draw current
as explained in sections 11.8 and 12.6. As will be
seen, the effective input resistance of the load gate
will replace the resistances of RDN and RDo in analyses of the MECL III operation.
Input Pull-Down Resistors
Input pull-down resistors RDNi have been added to
each input, so that unused inputs no longer need to
be tied to the -VEE lower rail. Recall from the SPICE
simulations of the MECL I and MECL II circuits presented in sections 11.9 and 12.7, respectively, the
V 1:--:A inputs are swept, while the ViNB inputs are held
at a constant -VEE level. The pinch resistor fabrication
presented in section 3.11 is used for these input resistors of large magnitude.
Resistor Values
Comparing the MECL III circuit of Figure 13.1 with
the MECL II circuit of the previous chapter, it is seen
that the Rc 1, Rm., and RE resistor values for the MECL
Ill gate are about 1/1 the magnitude of those used in
the MECL II logic circuit. This provides a larger output sourcing current resulting in faster switching and
larger fan-out but also contributes to an increased
power dissipation. The resistor values of the temperature compensating bias network are approximately the same.
MECL III
Separate Vcc 1 and Vcc2
Starting with the MECL III ECL family, two separate
sources are used for the upper rail. VcCJ for the current switch and bias network and Vcc 2 for the emitter
Figure 13.1 shows the MECL III NOR/OR gate. Note
that the basic schematic is identical to the MECL II
gate of the previous chapter.
182
13.2
MECL III Voltage Transfer Characteristic
183
l12Q
-Vtill = -5.2 V
FIGURE 13.1
temperature compenstaing bias network
MECL III NOR/OR Gate with Input Pull-down Resistors and No Output Pull-down Resistors
follower output buffers, both of which are connected
to ground. The separate grounds isolate the current
switch from the large current spikes that appear in
the collectors of Q 8 N and Q 110 during output logic
transition. This provides additional noise immunity.
The purpose of each element in the MECL III
gate of Figure 13.1 is tabulated in Table 13.1.
13.2 MECL III VOLTAGE
TRANSFER CHARACTERISTIC
The voltage transfer characteristic for the MECL III
NOR output is obtained using a method similar to
that of the MECL I and MECL II circuits but with the
output pull-down resistors of those circuits replaced
with the input resistance of the load gate.
VN01<
=
-IB,BNRc1 -
VBE.B/'-i(ECL)
The base current of Q11 r-.: with no load is 111,BN
and the output high voltage is
0
Vo11 = - VBE(ECL)
Input Low and High Voltages= Vn.
As with the ECL families presented thus far, the
transition region of the MECL III NOR/OR gate is
narrow (- 0.1 V) and the input low and high voltages are symmetric about the transition region given
by
and
Vi11 = VnB + 0.05 V
= VoL
Output High Voltage = Vott
Output Low Voltage
With all inputs of the MECL III circuit of Figure 13.1
low, all Q, are cutoff. The VNOR output voltage is
written by following dashed path 1 giving
If any input is high, the corresponding input BJT is
forward active. The collector current of this input 13JT
then dominates the current through Rei, i.e. In.Be-:
184
Chapter 13/MECL III and ECL 10K
TABLE 13.1 Purpose of Each Element
for MECL III Gate
Element
Rm
RE
QBN
QBo
RDNn
Purpose
Input BJT for n th input, input side of
emitter-coupled pair
Reference voltage BJT, reference side of
emitter-coupled pair
Input side current switch collector resistor,
balances NOR side of circuit with OR
side
Reference side current switch collector
resistor
IRE sourcing current resistance
NOR output BJT, buffered output
OR output BJT, buffered output
Input pull-down resistor for n th input
Temperature Compensating Bias Network
QB
RBI,
Du
D 12
R8 L
RBE
Self-biasing BJT
Self biases Q 13
Level-shifting diode 1
Level-shifting diode 2
Base bias resistor
Emitter bias resistor
Separate Upper Rail Supplies
Vcci
Vcc2
Ground rail for current switch and bias
network
Ground rail for emitter follower output
buffers
<< Ic, 1. The VNOR output voltage is obtained by again
following dashed path 1, where
lc,r
is then obtained by following dashed path 2
(neglecting In,BN) yielding
VNOR Saturation Region
The input voltage at which Q 1 goes into saturation is
the same as found in section 11.2 with Vee"" GND
= 0. Hence,
Temoerature
Comnensatim!
L
L
Bias Network
U
111e temperature compensating bias network for the
MECL III logic family is the same as that for the
MECL II with slightly different resistor values. The
expression for calculating the reference voltage provided by the bias network is the same as that derived
in section 12.3:
The state of each BJT and diode in the MECL II
NOR/OR gate for the NOR output high and low
states is tabulated in Table 13.2.
Example 13.1 MECL III NOR/OR Gate
Bias Voltage and VTC
(a) Determine the reference voltage V1rn provided by
the bias network of Figure 13.1.
(b) Determine the critical voltages and sketch the
VTC for the NOR output.
Use VBdECL) = VD(ON) = 0.75 V and V8 c(SAT) =
0.6 V.
TABLE 13.2 States of BJTs for Output High
and Low Logic Levels for a MECL III Gate
Assuming this input is driven by a similar gate in the
output high state, VrN = V oH which was determined
earlier in this section. Substituting the expression for
Ic, 1 into the expression for V NOR with VrN = VOH and
VNoR = Vm yields
Element
Qin
QR
Q13:,;
Qllo
QR
Du
DL2
VNOH
Cutoff
Forward
Forward
Forward
Forward
On
On
active
active
active
active
VNOL
Forward
Cutoff
Forward
Forward
Forward
On
On
active
active
active
active
13.3
MECL III Fan-Out
185
output high state, since Q1 is cutoff for low inputs.
Thus,
v .• = -1.31
-1.0
-1.5 i
---+------~-
I1L
= l 8 ,1(0II)
l 8 _1(OFF) = 0
The maximum fan-out of an ECL gate is therefore
dependent upon the output high state of the driving
gate. Hence,
-0.5
-1.0
,v•• = -1.31
_!_
-1.5
VOL= -1.76
FIGURE 13.2 MECL II NOR and OR Output Voltage
Transfer Characteristics
Solution (a)
The reference voltage by direct sub-
stitution is
Input High Current = Iitt
Vaa = - (5.2) - 2(0.75) (350)
(350) + (1. 958k)
- (0.75) = -1.31 V
Solution (b) The critical voltages for the MECL III
gate are also found by direct substitution:
V 011
= -(0.75) = -0.75 V
= -1.36 V
(-1.31) + 0.05 = -1.26 V
VIL= (-1.31) - 0.05
~
The current through the input pull-down resistor
RDN is simply
- Vrn1 + Vu:
t,nN -
RuN
The current into the base of
relation
I'
[(0.75) - (5.2))
(100)
1
+ (365)
Examining Figure 13.3, the input high current is seen
to be
I'
_ (-0.75) - (0.75) + (5.2) (100) _ (0.75)
(365)
-1.76 V
(0.6) +
Figure 13.3 shows a MECL III NOR output
buffer emitter-follower connected to the inputs of
identical MECL III gates. All circuit elements and parameters for the load gate are distinguished with a
prime. Only the current switch portion of the load
gate is shown, since that is all that is needed for analysis. For the determination of fan -out, V OUT = v; N
= Vrn 1• Note this is slightly different from the MECL
I and MECL II fan-out analyses, since the MECL III
gate has no output pull-down resistors RDN and RDo-
-
B.I -
Qi is found by the
___!h;_
f3F + 1
-0.486 V
The current source current I~E in the load gate is
The VTC with the critical voltages labeled for the
MECL III gate is shown in Figure 13.2.
13.3
MECL III FAN-OUT
As mentioned in the previous chapters, for ECL
gates, no current flows at the gate input during the
and the voltage at the common emitters of the load
gate current switch is
Backward substitution yields the magnitude of r;H·
186
Chapter 13/MECL III and ECL 10K
Vcc,T7
I
V'cc,17
~
I
--=:=-
-::-
V'••
--0
-1.31 V
NOR output buffer of driving gate
R'DN
50 kn
-V'rm = -5.2 V
current switches of N load gates
FIGURE 13.3 MECL III NOR Output Driving N Identical Gates for Fan-out Analysis (Note: the NOR output of the
driving gate is driving the load gates)
13.4
Output High Current = 1011
13.4
The output high current for the MECL III gate is
1011
=
h,HN(FJ\)
=
(f3r + l)Ia,BN(FA)
= (f3F + l)IRC/(FA)
Note that the output high current is not degraded
since the output pull-down resistors hae been eliminated. The current through the resistor RCI is
IRCI
=
-V8 E,BN(FA) - V0 H(reduced)
R
lv!ECL lil Power Dissipc1tion
187
MECL III POWER DISSIPATION
The analysis for determining the power dissipated in
a MECL III gate is sirn.ilar to that of the MECL II
gate. As for the MECL II gate, a contribution to the
power dissipated in the bias network is included.
Since the output pull-down resistors have been removed, there is no contribution due to current leaving the emitter of the emitter-follower output buffers. However, a current does flow to -VEE through
the input pull-down resistor.
Cl
It was mentioned in section 13.2 that the base current I13 _nN = IRci is zero for an unloaded MECL III
output. Therefore, as with the MECL I and MECL II
gates, the fan-out is calculated using a reduced value
of VoH• The value often selected is
VcJH(reduced) = V0 11 (unloaded) - 0.03 V
Temperature Compensated Bias
Network Power Dissipation PTc
=
The current through RBL of Figure 13.1 is found by
writing KVL along dashed path 3 assuming the base
current of Q 8 is much less than IRBL yielding
Backward substitution then provides IoH•
Example 13.2
MECL III Fan-Out
Calculate the maximum fan-out for the MECL III
gate of Figure 13.1. Use f3F = 49 and VBE(ECL) =
0.75 V. Assume that the load gates have reduced VoH
of the driving gate from -0.75 V to -0.78 V.
Solution
Substituting into the derived equations
yields
Vi=
(-0.78) - (0.75)
=
Ifn =
(-1.53) + (5.2)
( )
= 10.05 mA
365
_
IRON -
(-0.78) + (5.2) _
(50k)
- 88.4
,.L\
fA",
1111 = (88.4µ,) + (200µ,) = 288 µA
-(0.75) - (-0.78)
Iw =
(lOO)
= 300 µA
1011
=
[(49)
+
The total current delivered to the -VEE voltage
source through the bias network is the sum
-1.53 V
,
(10.05111)
IB,1 = (49) + 1 = 200 µA
1
The current through R8 E is found by writing KVL
along dashed path 4 of Figure 13.1. Since the current
through R8 H is IRBH = IRsu we have
NOR Output High Current
Supplied = IEdNOH)
The NOR output high state is achieved for all inputs
low. Thus, all input BJTs QJN are cutoff and QR is
forward active. Assuming the inputs are driven by
another MECL III gate in the output low state, each
input pull-down resistor carries a current
1](300µ,) = 15 mA
N ::; (l 5 m) = 52.08
(288µ,)
Hence, the maximum fan-out for this MECL III gate
is 52.
The current through RE for the NOR output high
state is the emitter current of QR given by
188
Chapter 13/MECL III and ECL lOK
The total NOR output high current of-VF.Eis then
the sum of these and the current through the bias
network. Thus,
hdNOH) = I1~dNOH) + N;,,
X
11wN(NOH) +
he
where Nn is the number of inputs (since all inputs
are low for the NOR output high state).
NOR Output Low Current
Supplied = IEdNOL)
For anv
hivh.
.1 innut
1
u-, thP
--NOR
- - - n11tn11t
- ---,--- ic;
-- in
--- thP
---- rn1trn1t
--·-r-·low state. The corresponding input BJT Q1 is forward
active and QR is cutoff. Therefore, the current
through resistor RE is the emitter current of a forward
active input BJT. Assuming the high input is driven
by a MECL III output in the output high state, the
current through RE is obtained by following dashed
path 2 of Figure 13.1 yielding
where each possible output state is considered to
have equal occurrence.
Example 13.3
Find the average power dissipated for the two-input
MECL III NOR/OR gate of Figure 13.1. For the NOR
output low state, assume Vr:---:A is high and V1018 is low.
Use V13 E(ECL) = 0.75 V.
Solution (Bias Network Currents) First, the
power dissipated in the bias network 1_s obtained
substituting into the derived expressions yielding
(5.2) - 2(0. 75)
IRBL
I 1w[
= Vou R~ VEE
Ire = (1.60111) + (1.95m) = 3.55 mA
Solution (NOR Output High Currents) The current through RE for the NOR output high state is
I
The current through each input pull-down resistor
with a low input (some inputs can be low for a NOR
output low state) has the current Irw:.ANOH) specified above:
lRoN(NOH)
= VoL +
_ (5.2) - (1.60111)(350) - (0.75) _
( k)
- 1.95 mA
2
Thus, the total current in the bias network is
The current through each input pull-down resistor
with a high input is
l1wN(NOL)
= (350) + (1.958k) = 1.60 mA
and
Iiv(NOL) = Vou - Viiu(ECL) + VEE
Re
MECL III Power Dissipation
v[[
R[
(NOH) _ (-1.31) - (O. 75) + (5.2) _
(365)
- 8 .6
A
/11
Both inputs contribute currents through their input
pull-down resistors of magnitude
I
RD,\
,(NOH) = (- l. 76) + (5 -2)
(50k)
=
68.8 .. ,1
I-'-''
Rl)N
The total NOR output low current to -VEE is then
the sum of these and the current through the bias
network. Thus
hE(NOL) = IRE(NOL) + N 11 _ X l 1wN(NOL)
+ N 111 X l 1wN(NOH) + he
where N 1L is the number of inputs remaining low for
the NOR output low state and Nn-r is the number of
inputs driven high.
Average Power Dissipated= PEdavg)
The average power dissipated for two inputs is obtained by
PEE (avg)
=
hE(NOH) + 3h:c:(NOL) V
1-:1
4
The total output high current is then
lEc(NOH) = (8.6111)
+ 2 x (68.8µ,) + (3.55)
= 12.29 mA
Solution (NOR Output Low Currents) The current through RE for the output low state is
IRr(NOL)
=
(-0. 75) - (0. 75)
(
)
365
+ (5.2)
=
.
10.1 mA
The current through the input A (for input high)
pull-down resistor is
l1,P1\
(NOL)
=
(-0.75) + (5.2)
(50k)
=
89.0 µA
The current through the input B (for input low) pulldown resistor is
13.6
(-1.76)
11,/JN(NOL) =
+ (5.2)
( 0k)
5
= 68.8
µ.A
The total output low current is then
Iu(NOL)
=
+ (89.0µ..)
+ (68.8µ..) + (3.55m)
= 13.8 mA
(10.1111)
The average power dissipated is then found by
Pu(avg) =
(12.29111) + 3(13.8111)
4
189
both the current switch and the bias network. This
version of ECL is the ECL lOK or 10,000 series. Furthermore, the larger resistors reduce the power consumption and also the output current drive capability. The larger resistors also intentionally increase the
rise and fall time and the propagation delay.
13.6 ECL 10K SERIES
SPICE SIMULATION
(5.2) = 69.8 mW
Note that this is larger than previous MECL I and
MECL II gates and this result was expected.
13.5
ECL 10K Series SPICE Simulation
ECL 10K SERIES
Figure 13.4 shows an ECL circuit that is schematically
the same as the MECL III but with larger resistors in
Ra
Figure 13.5 shows the ECL 10K series NOR/OR gate
with appropriate SPICE labelings. Since the ECL 10K
series gates do not have output pull-down resistors,
the NOR and OR outputs are each shown driving
the current switch sections of separate load gates.
The SPICE input CIRcuit file for this circuit is as
follows:
ECL 1OK Series NOR/OR Gate
-OPTIONS NOMOD NOECHO NOPAGE
217Q
~j
-V""=-5.2 V
FIGURE 13.4 10K ECL NOR/OR Gate
temperature compensating bias network
190
Chapter 13/MECL III and ECL lOK
n+ 14
vcc2-:!:oc ov
n-' O
n+j1
VCC1-=-DC0V
n-: o
14
14
11
2
QBN
2
2
4
n+ 4
11
6
QR
srQIA
DL1
7
~7
VINB±
11
3
12
DL2~
.
4
! 13
RBE
5
RDNB SOKOHM RONA S0KOHM RE
8
7nOHM
RBL
8
4.9KOHM
8
n+ 1 8
VEE~ DC 5.2V
17OHM RCR2
RCl2
22
45OHM
Ql2
23
l1
41
26
DL1P!;41
.36~-~3__,6r
~
26
RBE2
8
6.1 KOHM
RBLP
32
33
QR3
Ql3
~
DL2P
36
43
RBE3
4.9KOHM
8
~
37
~-~--~
6.1 KOHM
8
8
CB
ECL NOR/OR Gate with Appropriate SPICE Labelings
450 M
33
)
---~B3
26
RCI
l3~
.41
23
27
FIGURE 13.5
- ~CR31170HM
RBHP i~070HM
QB2
22
1
C
13.6
ECL 10K Series SPICE Simulation
191
VIN/V)
0
I
I
I
I
I'
I
I
I
I
--. t(ns)
-0.25
10 20 30 40 50 60 70 80 90 100
-0.50 --0.75
-1.00 --1.25 --1.50 ---
-1.75 -1.5 -1.25 -1.0-0.75 -0.5 -0.25
l----1--
I
~--
--+----
...VIN (V)
-0.2
-0.4
-0.6
-0.8
VINB(V)
-1.0
0--l-----+---+----+- ----1---------l------"'--+--___,.. t(ns)
-0.25-- 10 20 30 40 50 60 70 80 90 100
-0.50--0.75--t-------1.00
-1.25
-1.50
-1.2
_ _ _ _..-,,,--1.4
-1.6
-1.8
VNO.(V)
0 -+---+---+-f------+---+---+--+----1---+--_,._ t(ns)
-1.75 -1.5-1.25 -1.0-0.75 -0.5 -0.25
VIN (V)
---+---l------+--+-----+-+----+---l--------►
· -0.2
-0.4
-0.6
I
-0.8
-1.0
-1.2
-1.4
-1.6
-1.8
(a)
FIGURE 13.6 Results of Section 13.6 SPICE
Simulation: (a) Voltage transfer characteristics of NOR
and OR outputs from .DC sweep, (b) Transient response
-0.25
10 20 30 40 50 60 70 80 90 100
-0.50
-0.75
-1.00-- -1.25
-1.50-L'----------'
V 0 .(V)
0 -+----+---+~-+~---+----+-+--ic---+--------i. t(ns)
-0.25
10 20 30 40 50 60 70 80 90 100
-0.50--0.75--L,----------.
-1.00-
-1.25
-1.50
(b)
verifying realization of NOR and OR logic functions from
.TRAN sweep
192
Chapter 13/MECL III and ECL 10K
VCC1 1 D DC DV
VCC2 14 □ DC DV
VEE D 8 DC 5-2V
VINAS D PULSE<-S-2V DV OS 2NS
+ 2NS 2SNS SONS)
VINB 4 D PULSE(-s.2v DV OS 2NS
+ 2NS SONS 1DONS)
RDNA S 8 50KOHM
RDNB 4 8 50KOHM
RCI 1 2 2170HM
RCR 1 3 24SOHM
RE 7 8 77 70Hf'l
QIB 2 4 7 QNPN
QIA 2 S 7 QNPN
QR 3 6 7 QNPN
QBN 14 2 9 QNPN
QB◊ 14 3 10 QNPN
RBH 1 11 9070HM
RBL 13 8 4-98KOHM
RBE 6 8 6-1KOHM
DL1 11 12 DIODE
DL2 12 13 DIODE
QB 1 11 6 QNPN
*NOR output load current
switch
RCI2 1
RCR2 1
RE2 27
QI2 22
QR2 23
*◊R
22 2170HM
23 2450HM
8 7770HM
9 27 QNPN
26 27 QNPN
output load current switch
RCI3 1
RCR3 1
RE3 37
QI3 32
QR3 33
32 2170HM
33 2450HM
8 7770HM
10 37 QNPN
36 37 QNPN
*bias network for load current
switches
RBHP 1 41 9070HM
RBLP 43 8 4-98KOHM
RBE2 26 8 6-1KOHM
DL1P 41 42 DIODE
DL2P 42 43 DIODE
QB2 1 41 26 QNPN
RBE3 36 8 6-1KOHM
QB3 1 41 36 QNPN
-MODEL QNPN NPN<IS=1E-14 BF=49
+ BR= □ -2 VA=80 TF=D-4SNS
+ TR=SNS CCS=3PFD CJE=7-6PFD
+ CJC=3PFD RB=13 RC=6-2)
-MODEL DIODE D(VJ=D-7S)
-DC VINA -5-2V DV □ -1V
-PLOT DC VC(QBN) VC(QBO)
-TRAN 1NS 125NS
-PLOT TRAN V<VINA) V<VINB)
+ VC(QBN) VC(QBO)
-END
The voltage transfer characteristic and transient response obtained from simulating this circuit are
shown in Figure 13.6a and b.
CHAPTER13PROBLEMS
13.1
Calculate the reference voltage V,18 in the MECL III
gate of Figure 13.1. Neglect the base current and
use V1dECL) =VD= 0.75 V.
13.6
Calculate the reference voltage V88 in the twoinput 10K ECL OR/NOR gate of Figure 13.4. Neglect the base current and use VBIJECL) = VD =
0.75 V.
13.2
Determine the bias voltage V1rn in the circuit of Figure 13.1 with the resistor values doubled.
13.3
Determine the critical voltages V011 , Vm, V11 ., and
V111 , and V5 for the OR output of the MECL III
circuit of Figure 13.1. Neglect base currents and use
V8 ,(ECL) = VD = 0.75 V and VBc(SAT) = 0.6 V.
13.7
Determine the critical voltages Vrn 1, V0 1,, V1L, and
V111, and Vs for the OR output of the two-input 10K
ECL OR/NOR gate of Figure 13.4. Neglect base
currents and use VmJECL) = V0 = 0.75 V and
VBc(SAT) = 0.6 V.
13.4
Repeat Problem 13.3 for a circuit with RE doubled
in magnitude.
13.8
Repeat Problem 13.7 for a circuit with Rr: doubled
in magnitude.
13.5
Repeat Problem 13.3 for a circuit with collector resistors doubled in magnitude.
13.9
Repeat Problem 13.7 for a circuit with the collector
resistors doubled in magnitude.
Chapter 13 Problems
13.10
Determine the fan-out of the MECL III gate of Figure 13.1 for Vrn I reduced by 0.1 V. Use VB 1 (ECL)
= VI) = 0.75 and /3, = 49.
13.11
Determine the fan-out of the two-input lOK ECL
NOR/OR gate of Figure 13.4 for Vrn I reduced by
0.1 V. Use V8 r(ECL) =VD= 0.75 and /3 1 = 49.
193
13.12
For the MECL III gate of Figure 13.1, determine the
average power dissipation.
13.13
Double all resistor values in Figure 13.1 and determine the average power dissipation.
13.14
For the lOK ECL NOR/OR gate of Figure 13.4, determine the average power dissipation.
14
MODERN
EMITTERCOUPLED LOGIC
Current Source Analysis
The ECL 100K series is an ECL subfamily that provides a voltage transfer characteristic completely
independent of supply voltage variations and temperature variations. In this chapter, the basic performance of this ECL subfamily is described. Additionally, other ECL subfamilies developed after the ECL
100K series called lOKH ECL and ECLinPS (which
represents ECL in picoseconds) are mentioned.
14.1
In Figure 14.1, transistor QE and resistor R{; along
with DC voltages V(lB and -VEE form an active current source. This avoids the condition in which the
input transistors can be driven into saturation. The
magnitude of the current lie in Figure 14.1 is given by
This current is switched between the reference transistor and the input transistors depending upon the
operating state of the gate.
100K ECL SUBFAMILY
The ECL 100K series is an emitter-coupled logic subfamily that utilizes advanced fabrication techniques
to achieve larger current amplification f3F and faster
switching speeds. The primary reason for improved
operation is due to the use of oxide isolation instead
of junction isolation. This results in walled emitter
transistor structures that enable the fabrication of
BJTs with ve1y small parasitic capacitances and base
widths. The design improvements have led to ve1y
high switching speeds for this subfamily of ECL.
Example 14.1 EGL Current Source
Magnitude
Calculate the current source magnitude for the 100K
ECL NOR/OR gate in Figure 14.1. Use V13 E(ECL) =
0.75 V.
Solution
If
Substituting values yields
= (-3.3) - (0. 75) - (-4.5) = l.S
mA
250
NOR/OR Gate
Voltage Transfer Characteristic
Figure 14.1 displays the ECL 100K NOR/OR gate
with voltages V 1m and V(lB representing the unique
compensation network of the 100K series described
in the next section. The compensation network provides two bias reference voltages that are stabilized
to temperature and DC supply variations. Note that
the DC supply voltage is reduced in magnitude to
VEE = 4.5 V in order to reduce power dissipation.
Furthermore, the 100K subfamily uses a current
source as a replacement for resistor RE. The circuit
also has very huge resistors connected between the
OR and NOR terminals to ground and we treat these
resistors as open circuits.
The operation of the NOR/OR ECL 100K gate of Figure 14.1 is quite siITtilar to the other subfamilies of
ECL. In particular, the output voltages at the NOR
and OR terminals are given by
VNoR = -IR0Rc1 - VaE(ECL)
and
However, the current through each collector resistor
is dependent upon that through the temperature
compensating parnlleled diodes Du and Du.
194
14.1
]()OK ECL Subfamily
195
500W
VNOJ(
-Vim;;:; -4.5 V
FIGURE 14.1
ECL 100K NOR/OR Gate
In the following example, the critical voltages
and the voltage transfer characteristic are obtained
by the methods of the previous ECL chapters.
magnitude. From the equivalent circuit, neglecting
base currents, note that
Va,o
= -2R11 - Vo,u(ON)
and therefore,
Example 14.2
100K ECL Critical Voltages
Find the critical voltages VoH, V 0L, V1H, and V1L for
the NOR/OR outputs of the ECL 100K gate in Figure
14.1. Use V8 E(ECL) = V0 (0N) = 0.75 V and neglect
the base currents.
Solution (VoL and VoHJ To determine VOH (and
V0 L from the OR output) we consider the condition
in which the NOR output is high. For this case, the
input transistors in Figure 14.1 are cutoff and QR is
conducting. Additionally, Du is conducting the forward voltage V0 (0N). The equivalent circuit for the
VNoR output high is displayed in Figure 14.2 with all
collector resistors labeled R, since they are equal in
Also, from the equivalent circuit
-V
I
-~
z R
However, the sum of 11 and 12 is the collector current
of QR which is approximately equal to the current
source IE. Hence,
Va,o
R
196
Chapter 14/Modern Emitter-Coupled Logic
R
Q.(OPEN)
Equivalent Circuit for ECL 100K NOR/OR Gate for V~oR
FIGURE 14.2
Rearranging and solving for Vs,o yields
V B"
·"
or
_ _ ~RI _ Vo,L(ON)
8,0 -
3
E
VNOR
Substituting values yields
=
V 8,0
VsE,ao(ECL)
-
=
and furthermore this voltage is the output low voltage
To determine the voltage at the NOR output,
from Figure 14,2, we have
=
Va,o
+ Vo,u(ON) + I,R
Substituting for I1 yields
V
B,N
= V
B,O
+V
(ON) _ Vs,o
D,L1
+ Vo,u(ON) R
2R
or
VBN
'
VB,o
Vo,u(ON)
2
2
= -- + ----
(0. 75) _
2
+ - - - -0,05
VB,N Vi1dECL)
= -0.8 V = V011
=
V11.
(-0.85) - (0.75)
= -1,6 V
Va,N
_ (-0,85)
--2
-
V
=
-0,05 - 0.75
Solution (VIL and Vi,-J The input high and low
voltages are determined in the same manner as in
previous ECL subfamilies and are therefore
Hence, the OR output voltage is
VoR
= V0 1.
Hence, the NOR output voltage is
3
2
(0, 75)
VB,O = - -3 (500)(1.8111) - -3- = -0.85 V
and VoR
Substituting values yields
3V8 ,o = -2Rh - Vo,1(ON)
V
= Vrn-,
=
vllll -
-1.25
v
+ 0.05 = -1.15
V
o.o5
=
and
V111 = Vm1
14.2 DC ANALYSIS OF THE
100K ECL BIAS NETWORK
Figure 14.3 displays the unique bias network used in
the 100K ECL subfamily. This circuit provides two
DC output voltages Vmi and V~ 8 . These voltages are
temperature compensated as well as CO!Ttpensated to
variations in the supply voltage -V EF> Note that a
PNP transistor is on the right side of the network
and acts as a shunt regulator. The behavior of this
regulator is discussed in the next section. Also, note
that the resistor Rx is used to compensate for variations in f3F and V8E(ECL).
14.2
~oon
DC Analysis of the 100K ECL Bias Network
197
R,
Q,,
v•• = -1.2 V
o-
----l - -- --
:
--~-------------2--
V'•• = -3.3 V
FIGURE 14.3
IR
!
----2
i
R
ECL 100K DC Bias Network Providing V88 and Vf 8
Bias Voltage Expressions
From the bias network circuit of Figure 14.3, the bias
voltage V88 following dashed path 1 is given by
VBB
Q,H
=
Solution (Vnnl First, IR is determined by realizing
that DL is driven quite hard resulting in V0 (0N) =
0.8 V which is greater than VBE,dECL). Thus, the
emitter current of Q52 is given by (with Rx = 0)
-IRRBII - VBE,Bl(ECL)
Following dashed path 2, bias voltage
Vf 8
is
v~a = -vEE +
Vi,E,S1(ECL) + I1,R
+ VB1,dECL) - ViJE,/32(ECL)
or since the last two VsE(ECL) voltages cancel, we
have
and substituting values yields
h:,s2
=
(0.8) - (0. 75)
(lO0)
= 0.5 mA
This emitter current is also approximately equal to
the collector current which is IR. Therefore,
IR
Example 14.3
ECL 100K Bias Voltages
Calculate the bias voltages V88 and V~ 8 . Use
V8 E(ECL) = 0.75 V, V0 (0N) = 0.8 V, and Rx = 0.
= li,;, 52
= 0.5 mA
Substituting into the expression for V88 yields
VBB = -(0.5111)(900) - (0.75) = -1.2 V
198
Chapter 14/Modern Emitter-Coupled Logic
Solution (V~H)
Substitution into the equation for
v~B yields
v~s
=
(-4.5) + (0.75) + (0.5111)(900) = -3.3
v
work shown in Figure 14.3 were determined. In this
section, we consider the temperature dependence of
these voltages, as well as the dependence of the bias
voltages upon the bias supply -VEE·
Bias Supply Dependence
Bias Network Power Dissipation
The bias network power dissipation is constant. This
is determined in the usual manner, namely, by considering the average power supplied by the supply
voltage. Thus, the average pm-ver is
Pmss
=
VEE(Io + Ic,s2 + Ic,s1)
where lsH is neglected, since it is much less than the
other currents. Also, since Ic, 51 = lc,s 2 = IR (by design), the average power dissipated by the bias supply network is
Considering V(m initially, suppose that -VEE were to
decrease becoming more negative. From the circuit
of Figure 14.3, the increased voltage appears across
R2 driving the shunt PNP transistor Q5 H harder. This
causes the shunt currPnt T0; 11 to increase and shunt
additional current through Qsl-f down to -VEE·
Hence, Ic,s 1, Ic,s 2, and ID are unchanged keeping IR
and VBE(ECL) unchanged. Also, the voltage V~ 5 is
given by the previous expression
and this varies in direct proportion to VEE· However,
as we have seen, V~ 13 is only used in circuits with
-VEE and the relative voltage Vf_m - (-VEE) is therefore independent of changes in the supply voltage
Example 14.4 Power Dissipation for EGL
100K Bias Network
Calculate the average power dissipated in the bias
network of Figure 14.3. Use V8 E(ECL) = 0.75 V and
V D(ON) = 0.8 V.
Solution In order to substitute into the power dissipation expression, the current ID is first calculated
from Figure 14.3. Note that
Io =
V/3u -
[-Va: + V0 (0N)]
-VI+
Next, considering V88 in the circuit of Figure
14.3, we again let-VEE become more negative. Since
Ic,s 2 remains constant because of the shunt transistor
Q51. 1, IR also remains constant. Furthermore, since
Io.L remains constant, VBE.Ill (ECL) and V13 E.,dECL)
are unchanged. Therefore,
VBB
= -IRR - Vin:,m(ECL)
is also unchanged when -VEE changes.
RE1
Substituting values yields
I
(-3.3) - [(-4.5)
D
0~
=
+ (0.8)] = 0.4 mA
Thus, since IR = 0.5 mA (from the previous example),
substitution yields
PDJss
=
(4.5)[(0.4m) + 2(0.5111)]
=
Temperature Dependence of Bias
Voltage VBB and V~B
The bias voltage expressions developed in the previous section are repeated for convenience as follows:
6.3 mW
and
v~ll =
14.3 BIAS NETWORK
COMPENSATION FOR
TEMPERATURE VARIATION
In the previous section, the DC voltages V813 and
V~ 5 provided by the 100K ECL subfamily bias net-
-Vu: + ViiE(ECL) + IRR
Also, for proper operation of the bias network, diode
D must be driven with higher current which results
in VD(ON) > V 8 E(ECL). This results in Q 52 operating
as an emitter follower with Ic, 52 being proportional
to V 0(ON) - V sE(ECL). Therefore, lc, 52 has a positive
temperature coefficient as does IR. This implies that
Chapter 14
both resistors labeled R have a positive tempernture
coefficient. Thus, in viewing the bias voltage equations for V1m and Vi'm, we observe that the negative
temperature coefficient of V1JE(ECL) is cancelled by
the positive temperature coefficient of VR = IRR.
Hence, V1rn and Vi'rn are independent of temperature.
P£davg) = h£VEE
where IEE = IE. That is, the average supply current is
equal to the current source IE current. Thus,
PEE(avg) = IEVEE
Example 14.5 Total Average Power
Dissipation Calculation
Calculate the total power dissipated in the ECL 100K
NOR/OR gate.
Solution The total average power dissipated in the
ECL 100K NOR/OR gate is given by
PmT/\1.
=
P0155 + Pu:
=
VE:£Uo + 21") + Vr:r:lr:
Substituting values gives
PmT1\L = (4.5)[(0.4111) + 2(0.5111)]
(4.5)(1.8m)
= 6.3111 + 8.lm = 14.4 mA
199
It should be noted that the bias network is normally
used to supply V 1rn and Vfm to several gates. Hence,
the power dissipation per gate is less than 6.3 mW.
For example, if the bias network is used to supply
four gates, then the power dissipation per gate for
the network is
P0155 (bias network)
14.4 POWER DISSIPATION
OF 100K ECL SUBFAMILY
Determining the power dissipation for the 100K ECL
subfamily circuit follows a procedure similar to that
for the other ECL circuits presented in previous
chapters.
Considering the circuit of Figure 14.1 and disregarding the bias network dissipation, the average
power dissipation is given by
Problems
14.5
6.3111
4
1.58 mW per gate
OTHER ECL FAMILIES
Two other ECL families with improved characteristics arc
1.
the ECL lOKH subfamily, and
2.
the ECLinPS subfamily
ECL 10KH Subfamily
This subfamily is a combination of the 10K and 100K
subfamilies. The lOKH series uses the same unique
bias network and the current source of the 100K series but does not interconnect the outputs with two
diodes (as in Figure 14.1). However, the lOKH series
provides slightly improved propagation delay with
similar power dissipation. This is achieved by using
a special device fabrication procedure developed by
Motorola and called the MOSAIC process. This fabrication procedure results in reduced parasitic capacitances and reduced device size which permits the
reduced propagation delays.
ECLinPS
The ECLinPS (which stands for ECL in picoseconds)
subfamily came out in 1987. This family takes advantage of advanced fabrication techniques and is
capable of achieving edge speeds of less than 1 ns.
CHAPTER14PROBLEMS
14.1
14.2
Analyze the temperature compensating and supply
compensating reference voltage circuit of Figure
14.3 to determine the reference voltage magnitudes
for VRR and v~B- Use vllE(ECL) = 0.75 V and
VD(ON) = 0.8 V with Rx = 0.
14.3
Repeat Problem 14.1 with R reduced to 500 D.
14.4
(a) Show that the bias network of Figure 14.3 does
indeed stabilize the voltages Vm, and V~B to
temperature variations.
(b) Also, show that V1m and V~B + VEE are stabilized to variations in power supply magnitudes.
Repeat Problem 14.1 with VEE = -5.2 V.
200
Chapter 14/Modern Emitter-Coupled Logic
14.10
Determine the critical voltages for the ECL 100K
NOR terminal of Figure 14.1. Use V81,(ECL) = 0.75
V and neglect the base currents.
Determine the average power dissipation per gate
for the ECL 100K circuit of Figure 14.1. Assume
that the bias supply circuit provides three identical
gates.
14.11
Determine the critical voltages for the ECL 100K
NOR/OR gate ofFigure 14.1 with the modified current source of Problem 14.5. Use VlldECL) = 0.75
V and neglect base currents.
Determine the average power dissipation per gate
for the ECL 100K circuit of Figure 14.1. Assume
that the bias circuit supplies three identical gates
with -VEE= -5.2 V.
14.12
Determine the average power dissipation per gate
for the ECL 100K circuit of Figure 14.1. Assume
that the bias supply circuit provides three identical
14.5
Determine the magnitude of the current source I1
in Figure 14.1 for R( = 500 n.
14.6
14.7
14.8
Determine the average power dissipation for the
compensating reference voltage circuit of Figure
1 A 'J
.J."'.1:.J.
14.9
Determine the average power dissipation for the
compensating reference voltage circuit of Figure
14.3 with -VEE= -5.2 V.
p-;itps
- -
U
with -V.-.I.J
=
-4 V
""
GATES
The previous several chapters traced development of
the basic ECL current switch through the various
ECL logic families. While the NAND function is the
naturally occurring logic function of the TTL logic
families presented earlier, the NOR and OR functions are inherent to the ECL current switch and logic
gates. With TTL other logic functions such as NOR
and OR are obtainable by modifying the NAND logic
gate as we have seen. With ECL, NAND and AND
functions are obtained through modifications of the
ECL NOR/OR gate in a similar fashion. There are
two circuit design techniques used for obtaining
NAND/AND functions from ECL. These are the
following:
1.
Collector dotting, which uses two current
switches in a wired-AND configuration.
2.
Series gating, which consists of stacking the ECL
current switch on an inverting BJT.
ploy complementary NOR and OR outputs, ANDing
and NANDing can easily be accomplished through
exploitation of De Morgan's NOR theorem.
Example 15.1 EGL Realization of ANDing
through De Morgan's NOR Theorem
How could the logic schematic of Figure 15.2a
(A
+
B)(C
+
D)
be realized using only ECL NOR/OR gates?
Solution Since the OR and NOR functions are already available, the question is how to obtain the
ANDing of the sub-logic expressions. Since a NOR
gate is the logical equivalent of the AND gate with
inverted inputs, we use the opposite outputs of the
first stage NOR/OR gates to obtain the logic
A+B
Extending these series gating methods allows more
complicated logic realizations as will be shown. Also,
minor rewiring of a ECL NAND/AND gate designed
with the series gating method allows the realization
of XNOR and XOR gates.
Before presenting the collector dotting and series
gating design techniques, a method of logic realization that has been useful and requires no circuit
modification is examined. This method simply exploits the natural ECL complementary signal outputs
and De Morgan's theorem.
and
C+D
Feeding these signals to a second stage ECL gate and
using the NOR output as shown in Figure 15.2b gives
the desired logic realization. Note that the OR output
of the second stage gate gives the inverse of the output signal, which may be desired as an inverted input
to an additional stage.
The previous example shows that AND and NAND
functions can easily be obtained with no additional
circuitry for ECL NOR/OR gates, since complementary outputs are available.
The remainder of this chapter presents modifications to the ECL NOR/OR logic circuit design to
obtain the remaining basic logic functions. Design
methods for obtaining XOR/XNOR functions and
15.1 USE OF NOR/OR GATES
AS AND/NAND GATES
WITH INVERTED INPUTS
De Morgan's NOR theorem as presented above
states that a NOR gate can be used as an AND gate
with inverted inputs. Since ECL gates naturally em-
201
202
T
Chapter 15/0ther ECL Gates
Tips, Tricks, and Gimmicks
De Morgan's Theorems
(a)
De Morgan's theorems are needed in the following section. These theorems can be stated
simply as follows:
De Morgan's NOR Theorem
(b)
A NOR gate is the logical equivalent of an
AND gate with inverted inputs. This is observed in Figt1re 15.1a1 \vhere
FIGURE 15.l DeMorgan's Theorems of Logic
Equivalency: (a) The NOR logic function is equivalent to
the logical AND function with inverted inputs, (b) The
NANO logic function is equivalent to the logical OR
function with inverted inputs
W+Y=WY
As a result, an OR gate is the logical equivalent
of a NAND gate with inverted inputs, observed
by inverting the previous equation yielding
(W + Y) = W + Y = W Y
De Morgan's NAND Theorem
complex OR-AND-invert logic functions are also
presented.
A NAND gate is the logical equivalent of an
OR gate with inverted inputs. This is observed
in Figure 15.1b, where
15.2 COLLECTOR DOTTING
WIRED-AND GATES
WY=W+Y
As a result, an AND gate is the logical equivalent of a NOR gate with inverted inputs, observed by inverting the previous equation
yielding
Circuit
An ECL design method for obtaining the logical
AND function rnllcd collector dotting achieves the
realization of the AND function by placing multiple
ECL current switches in parallel. Figure 15.3a shows
WY=WY=W+Y
ECL
gates
outputs
complementary
____
/_------ __
DeMorgan's theorem shows
that these logic schematics
are equiavlent
/_,
\
(A+ B)(C + D)
= (A + B)(C + D)
=(A+ B)(C + D)
...,(A+ B)(C + D)
(A+ B)(C +D)
C
D
(a)
FIGURE 15.2 (a) Desired ANDing of ECL signals,
(b) Since ECL gates naturally employ complementary
(b)
outputs, a NOR gate can serve as an AND gate with
inverted inputs
]5.:?.
Collcctm Dotting Wired-AND Gates
203
VrnA
temperature compensating bias network
Vm
V
~ ('
I
-·--t/~
On
',:i
(
l
INAD
~
parallel current switch input section
(a)
FIGURE 15.3
F=AB
INB -
(b)
ECL AND Gc1tc Designed with the Collector Dotting Method: (a) Circuit schematic, (b) Logic symbol
204
Chapter 15/0ther ECL Gates
YourCV)
VBB = -1.31
-1.5 ,
-1.0
- - - - -'- T1
!- -
tI
-0.5
-
-
-1- -
-
---;- -
obtained by writing KVL along dashed path 2 of Figure 1S.3a:
VIN(V)
I
---►
_ I
C.R -
''
'
''
· -0.5
''
_ Vim - VHu,(ECL)
R
F,R -
+
VEI
u
Thus, by substitution the output low voltage for the
ECL gate of Figure 9.3a is
: :,.:--------1-VOH = -0.75
'''
I,
R[/
. -1.0
I
'''
'''
'' ''
' '
V'BB . I..._ • ..;,.1.
~1
-
' '
' -1.5
tvoL=-1.76
I
(c)
Viir:,iw(ECL)
Output High Voltage = V0u
If both inputs are high, Q,A and QIB are both active
and the reference BJTs in both current switches are
cutoff. With both reference QR, and QR 2 cutoff, the
output voltage can be found by writing KVL along
dashed path 1 of Figure 15.3a with IRrn = 0:
Vo1 I
FIGURE 15.3 (continued) (c) Voltage transfer
characteristic
a two-input ECL AND gate constructed by using two
parallel current switches. The circuit symbol for this
logic gate is shown in Figure 15.3b. The additional
current switch input section is in the lower shaded
block of Figure 15.3a. The base terminals of both reference BJTs are connected as are the collector terminals. A slightly modified bias network (to produce
V,m) is present along with a single emitter-follower
output buffer Q 13 !': taken at the common collector terminals of QR, and QR 2. Note that the base of the
output buffer BJT QBN is fed from the same point as
the OR output buffer in a ECL NOR/OR gate.
Logic Realization and Critical Voltages
Output Low Voltage= VoL
If either input in the ECL gate of Figure 15.3a is low,
the reference BJT in the corresponding current switch
will be active, This will cause a current in the reference collector resistor Rm, bringing the voltage at the
base of the output buffer Q8 N down. Thus, following
dashed path 1 of Figure 15.3a, the output low voltage
of an unloaded gate is given by
VOL
=
-lc,RRc,R - VBr:,iw(ECL)
The collector current through QR, (or QR 2) is approximately equal to the emitter current IE.R and is
= 0 - v/lE,/lN(ECL) = - VidECL)
Input Low and High Voltages
=Vn and Vm
As was the case with the ECL NOR/OR gates of the
previous chapters, the transition region for the ECL
AND gate of Figure 15.3a is narrow, approximately
0.1 V. The input low and high voltage V1L and Vn-1
are symmetric about the reference voltage Vmi• That
is,
and
V1u
=
Vim
+ 0.05
The voltage transfer characteristic with the critical voltages labeled is displayed in Figure 15.3c.
Realization of Logical AND Function
Since the output is low for either input low and high
only when both inputs are high the logical AND
function is realized for this gate. This gate is sometimes referred to as a wired-AND gate since it is
made up of two ECL current switches with the noninverting outputs electrically connected (or "wired"
together).
SPICE Simulation of ECL
Collector Dotted AND Gate
Example 15.2
Perform a SPICE simulation of the ECL AND gate
of Figure 15.3a to prove that the logical AND function is realized. Place a 50 kf1 resistor between the
emitter of the output buffer BJT Q13 N and -VEE·
15.2
Collector Dotting Wired-AND Gates
VCC2 40 D DC DV
VEE D 30 DC 5-2V
VINA 1 D PULSE(-5,2V DV OS 1NS
+ 1NS 25NS SONS)
VINB 2 D PULSE(-5,2V DV OS 1NS
+ 1NS SONS 100NS)
RPA 1 30 50KOHM
RPB 2 30 50KOHM
Solution
Figure 15.4 shows the ECL AND gate of
Figure 15.3a with appropriate SPICE labclings and
an output pull-down resistor. The SPICE input CIRcuit file for this circuit is as follows:
ECL Collector Dotting AND Gate
,OPTIONS NOMOD NOECHO NOPAGE
VCC1 20 D DC DV
120
RCIAi2170HM RCR 2450HM
6
13
20
QB2
4030HM
Ji ___ -
6
3
QR1
5
QB1
DL1f
5
4
RPA 50KOHM RE1 7770HM
RBE
8
:i·--"-----____J
5
14
VINA¥
5040HM
20
6
QIA
DL2.f
I
·10
6.1KOHM ~
30
RBL 4.98KOHM
l
30
20
0
i
n+ 40
VCC2.,.. DCOV
RCIBJ;170HM
40
t2
6
i
o-
2
n+l2
V~1B
~11
6
*
13
11
13
RPO 50KOHM
2
RPB
QBN
QR2
VINBt
50KOHM RE2 7770HM
30
30
30
FIGURE 15.4
205
Collector-dotted ECL AND Gate with Load Resistors and Appropriate SPICE Labelings
206
Chapter 15/0ther ECL Gates
RCIA 20 3 2170HM
RCR 20 6 2450Hf1
RCIB 20 12 2170HM
RE1 4 30 7770HM
RE2 11 30 7770HM
QIA 3 1 4 QNPN
QIB 12 2 11 QNPN
QR1 6 5 4 QNPN
QR2 6 5 11 QNPN
QB 20 8 5 QNPN
Q82 20 7 6 QNPN
YmiV)
...
0-1
25
--
-
50
-+----i---
75
-- -1-
100
-
t
-
+- -► t(ns)
-2-
-3-4-
-5-
DL1 8 9 DIODE
DL2 9 10 DIODE
RBH1 20 7 4030HM
RBH2 7 8 5040HM
RBL 10 30 4,98KOHM
RBE 5 30 6,1KOHM
QBN 40 6 13 QNPN
RPO 13 30 SOKOHM
,MODEL QNPN NPN<IS=1E-14 BF=49
+ BR=0,2 VA=80 TF=0-45NS
+ TR=SNS CCS=3PFD CJE=7,6PFD
+ CJC=3PFD RB=13 RC=b-2)
-MODEL DIODE D(VJ=0,75)
,TRAN 10PS 10DNS
-PLOT TRAN V(VINA) V<VINB)
+ VE(QBN)
,END
The transient response obtained from this simulation
is shown in Figure 15.5. Note that the output is high
only when both inputs are high, and low when either
input is low. Thus, the logical AND function is indeed realized by use of the collector dotting method.
VINB(V)
...
25
50
75
100
0
t(ns)
-1 -
-2-
-3--4-
-5 -
Your(V)
...
0---
25
50
--t---+-
75
- -+- ---
100
-►
t(ns)
-1
-2--;-3-
-4--;-
-5--
Adding More Inputs
Additional inputs are added to the AND gate of Figure 15.3a by including additional identical current
switch input sections (shaded in Figure 15.3a). It is
simple to show that any input low will bring the reference BJT of the corresponding current switch input
section into active operation and in turn force the
output low.
15.3 COLLECTOR DOTTING
COMPLEX OR-AND LOGIC GATES
The collector dotting AND gate of Figure 15.3a can
easily be expanded to provide a complex OR-AND
FIGURE 15.5 Transient Response of Example 15.2
SPICE Simulation .TRAN Sweep
logical function. By adding additional input BJTs in
parallel with the existing input transistors, sub OR
ing of these inputs is performed and then ANDing
through the collector-dotting. Figure 15.6a shows
such a gate.
Input ORing Sections
Examining Figure 15.6a, if either input A or Bis high,
the reference BJT QR 1 is cutoff. If both A and B are
low, QR, is active. Thus, the collector voltage of QR 1
15.3
Ro,
Collector Dotting Complex OR-AND Logic Gates
2450
temperature compensating bias network
parallel current switch input section
(a)
FIGURE 15.6
ECL Complex OR-AND (OA) Logic Gate Through Collector Dotting Method: (a) Circuit
207
208
Chapter 15/Other ECL Gates
(A +B)(C + D)
Example 15 .3 Complex ECL Collector-Dotted
AND-OR Gate
What logic function is performed by the complex
ECL collector-dotted logic gate of Figure 15.7a?
(b)
FIGURE 15.6 (continued)
(b) Logic schematic
is the logical function VA OR Vll. Similarly, if either
input C or D is high the reference BJT QR 2 is cutoff.
QR 2 is active when both C and D are low. As with
the other current switch, the collector voltage of QR 2
is the logical function V c OR VD·
Output is ANDing of the ORings
If both reference BJTs are cutoff, then no current
flows through Rm and the output will be high. If
either reference BJT is active (which results from all
inputs in the corresponding current switch low) then
a current flows through Rm into the collector of the
corresponding reference BJT and the output is low.
Thus, the gate of Figure 15.6 realizes the logic function
VouT
=
(VA + VB)Wc + Vo)
as shown in Figure 15.6a. The logic schematic is
shown in Figure 15.6b.
Recipe for Other Complex Logic Gates
Any combination of OR-ANDing is possible with the
collector dotting design method using the following
rules:
1.
ORing of signals is performed by multiple input
BJT current switches.
2.
ANDingof ORed signals is performed by placing
multiple current switch input sections in parallel.
3.
A single output buffer is taken from the common
collector of all current switch reference BJTs.
4.
A single bias network similar to that shown in
Figure 15.3a is connected to the common base
and collector of the reference BJT in all current
switch input sections.
FIGURE 15.7
Solution The top current switch has two inputs, A
and B, and therefore embodies the sub - logic A + B.
TI1e middle current switch has the single input C and
output Cat the common collector. The bottom current switch has three inputs, D, E, and F and there fore perform s the sub-logic D + E + F. The collector
dotted current switches perform the AND operation
on the sub -logic of each section . Thus, the output
voltage of the ECL gate of Figure 15.7a realizes the
logic function (symbolized in Figure 15.7b) as
follows:
VouT
= (VA OR VB) AND Ve AND (V0 OR VE OR VF)
= (A + B)C(D + E + F)
Lack of Complementary Signal Outputs
The most notable disadvantage of the collector-dotting method is the lack of complementary output signals. That is, with the ECL logic gates of the previous
chapters NOR and OR (inverting and non-i nverting
for single input ECL gates) outputs are both naturally
available. With a collector dotted wired -AND ECL
gate, only an AND output is available.
The following sections presen t a second design
method for obtaining simultaneous ANDing and
NANDing of input signals.
15.4 SERIES GATING-BASIC ECL
NANO/AND CURRENT SWITCH
A second design technique for obtaining ANDing of
signals is th e series gating design technique. Series
gating employs the series connection of current
switches.
Circuit
Figure 15.8 shows the basic series gated ECL NAND/
AND current switch . Two current switches are
placed in series with th e common emitter of the first
(a) Six-input ECL collector dotted AND-OR (AO) logic circuit of Example 15.3
temperature compensating bias network
v= ,,....................
(a)
210
Chapter 15/0thcr ECL Gates
A--
NAND Output Low State
B -
If both A and B arc high, then a current will flow
through Re, approximately equal to the source current Ir+ This will bring the NAND output to the output low state given by
c--------1
~
F=(A+B)C(D+E+F)
D
EF--
v.\-oL
(b)
FIGURE 15.7 (continued)
solution to Example 15.3
(b) Logic schematic
current switch feeding the collector of the input BJT
of the second. The collectors of both reference transistors are connected to the resistor Rm.
Realization of Logical NAND Function
NAND Output High State
If input A or B is low, then the corresponding input
BJT will be cutoff and no current will flow through
Re,- Thus, the output labeled VNAND will be at the
high voltage given by
VN011
= Vco = 0
FIGURE 15.8
(NANO output high voltage)
= o - lc.11,RC/
= - IIERCI (NANO output low voltage)
Realization of Logical AND Function
=
AND Output Low State (VIJ Low)
If input Bin Figure 15.8 is low, then Qlll will be cutoff
and QRB will be turned on and a current will flow
through Rm into the collector of QRH· This will force
the voltage at the AND output to be low given by
V.,01 =
=
0 - lc.1wRrn
-lrERrn
(AND output lm.u voltage)
AND Output Low State
(Vn = High and VA == Low)
If VB is high, then Qm will be active and QR!l will be
cutoff. If V,\ is simultaneously low, then Q1,\ will be
cutoff and QRA will be active. A current will then flow
through Rm into the collector of QR/\ and subse-
Basic Series Gated ECL NANO/AND Current Switch; requires two reference voltages
15.5
=0-
V1, 011 = Vcc 1 = 0
(AND output hig/J voltage)
lc,1,ARCR
= - In:Rrn
15.5 SERIES GATING NAND/AND
GATE
(AND output low voltage)
AND Output High State
1f both inputs are high then the input BJTs Q1J\ and
Figure 15.9a shows an ECL NAND/AND gate constructed with the series gating design method. The
logic symbol for this gate is shown in Figure 15.96.
Q 1ri are both active. Both reference transistors, QRA
and QRB, are therefore cutoff and no current flows
'·--'
;.V,m=-5.2 V
temperature compensating hia~ network
(a)
A--j\
B -l__)~
F = AB
(b)
FIGURE 15.9
211
through the resistor Rm. Thus, the AND output is
high when both inputs are high and
quently into the collector of Qrn. This will again bring
the AND output low with approximately the same
voltage magnitude as above, given by
V;\OL
Series Gating NAi'\JD/AND Gates
ECL AND Gate Designed Using Series Gating Method: (a) Circuit schematic, (b) Logic symbol
212
Chapter 15/0ther ECL Gates
The reference voltage V8B is then determined relative
to Vm1 following part of dashed path 2 as
V NAND, VAND(V)
v •• =-1.32
v.=-0.486
t
-~--!;_SJ-,-~~-~--i~~ -~"' (V)
ii l
:
I
:::
Emitter Follower Input
-0.5
''
VNOR
: : :
: J,.:- - - - - - - - - - - -
''
v
-0.75
OH=
-1.0
TV•
8 =-1.32
t-1.5
VOL=
-1.76
(c)
FIGURE 15.9 (continued)
characteristic
(c) Voltage transfer
In the last section, the need for two distinct reference
voltages in a series gated ECL gate was mentioned.
Looking back to the NAND/AND current switch of
Figure 15.8, the lower current switch requires a reference voltage V88 reduced in magnitude from the
V88 voltage referencing the upper current switch. Examining the ECL NAND/AND gate of Figure 15.9a,
a modified bias network is observed.
Vnn Reference Voltage
The voltage V88 is obtained by first writing KVL for
dashed path 1 and solving for the current ID, yielding
VEE - 2V (0N)
I o = - - -0- - R/311 + RsL
From this current, the emitter voltage of Q8 is
= -IoRan - VaE.a(ECL)
= VEE - 2V0 (0N) RBf/ _
R Bl I + RBL
The previous section calculated the relative difference between the reference voltages of the two current switches in the series gated ECL circuit of Figure
15.9a. With the reference voltage to the second current switch lower than the reference voltage to the
first switch, the input to the second current switch
must be reduced by an equal magnitude so that the
voltage at the base of Qrn is varied about V~B· Note
from the circuit that the input voltage V,m is obtained
following dashed path 3 as
vll.1a = ViNa - vBcrn(ECL)
- Vo.u/ON) - I,,rnRun
Modified Bias Network
VsB
Virn = V,38 - 2VD(ON) - h.aRu1
V ·(ECL)
BE
V ~8 Reference Voltage
To obtain the second reference voltage V5 8 , the emitter current of Q 8 must first be determined. Writing
KVL along dashed path 2 and solving for Ii::,s gives
V 88 - 2Vo(ON) + VEE
hB = -------,
RaE1 + RaE2
Also, note that the input voltage at the base of Q 111
is V1"' 13 degraded by approximately V88 - V811 .
The series gated ECL NAND/AND gate of Figure 15. 9a has emitter-follower output buffers just as
the NOR/OR gates of the previous chapters. Figure
15.9c shows the voltage transfer characteristic of the
ECL NAND/AND gate of Figure 15.9a.
Example 15.4
Series Gated EGL NANDIAND
SPICE Simulation
Perform a transient SPICE simulation on the series
gated ECL NAND-AND gate of Figure 15.9a to
prove the realization of the logical NAND and AND
functions. Include 50 kD pull-down resistors between the output nodes and -VEE·
Solution Figure 15.10 shows the series gated ECL
NAND/AND gate of Figure 15.9a with output pulldown resistors and appropriate SPICE labelings. The
input circuit file for this simulation is as follows:
Series gated ECL NAND/AND Gate
-OPTIONS NOMOD NOECHO NOPAGE
VCC1 16 0 DC OV
VCC2 15 0 DC OV
VEE 8 0 DC -5-2V
VINA 1 0 DC -0.bV PULSE(-1.5V
+ -0-bV OS 1NS 1NS 25NS 50NS)
VINB 2 0 DC -0-bV PULSE(-1.5V
+ -0-bV OS 1NS 1NS 50NS 100NS)
15.5
213
Series Gating NAND/AJ,JD Gates
?1~5
VCC2~DCOV
--
---
'
--
-----
- - - I_ _ _ • -
16
I
15
29
QBN
2
0--~
0----
n+ 2
VINBnJo
I
RCR
*
20
n+ 1
VINAt
DLB
RLB1
19
--oV AND
6
7
29
22
DL1
6
QI.A
DL3
4
7100HM
DL4
7
4
DL2
RBE1
7200HM
19
RPOUTA
50KOHM
8
23
11
!
23
12
8
I
QBA
22
QB
RPOUTN
50KOHM
i
/15
7
16
11
24
9070HM
22
7
QLB
20
RBH
2450HM
29
16
24(
VNAND
---
RPAt
50KOHM
8
RLB2 3.13KOHM
12
8
iRPB
50KOH
!B
RBL
REIE2
9
4340HM
3.06KOHM
4.98KOHM I
6
8
6
~I- - - ~ - _ L _
n+ 8
VEE~
DC -5.2V
n• O
FIGURE 15.10
Series Gated ECL AND Gate with Output Pull-down Resistors and Appropriate SPICE Labelings
*series gated current switches
QIA 29 1 4 QNPN
QRA 7 6 4 QNPN
RPA 1 8 50KOHM
RPB 2 8 50KOHM
RCI 16 29 2170HM
RCR 16 7 2450HM
QLB 16 2 20 QNPN
DLB 20 21 DIODE
RLB1 21 11 7100HM
RLB2 11 8 3-13KOHM
QIB 4 11 9 QNPN
QRB 7 12 9 QNPN
RE 9 8 4340HM
*NAND and AND output buffers
*with output pull down
resistors
QBN 15 29 24 QNPN
RPOUTIN 24 8 50KOHM
QBA 15 7 19 QNPN
RPOUTA 19 8 50KOHM
*temperature compensating bias
*network
QB 16 22 6 QNPN
DL3 6 18 DIODE
DL4 18 17 DIODE
RBE1 17 12 7200HM
RBE2 12 8 3-06KOHM
RBH 16 22 9070HM
DL1 22 34 DIODE
214
Chapter 15/0ther ECL Cates
4
VNAND(V)
4
-l.75-l.5-l.25-1.0-0.75-0.5-0.25 I
VIN (V)
---+----t------+----+----+--+------+--+---------
t-0.2
t-0.4
0-------l-+----t---+---+---'f---+----+----1-----l---.i. t(ns)
-0.25J_ 10 20 30 40 50 60 70 80 90 100
-0.50-L
-0.75-1-1---1.00-r
-1.25~
-l.50J_
t-0.6
VINB(V)
t-0.8
0
+-1.0
I
. -1.2
t
I
I
►
t(ns)
-0.25+ 10 20 30 40 50 60 70 80 90 100
-0.50+
-0.75 - - - - - - -1.00-i
-1.25+
-1.50-
t-1.4
I
t-1.6
r-1.8
VNAND(V)
•
0-j - 4 -t--l--l~+-t--i-+--t-l--► t(ns)
V AND(V)
-l.75-l.5-l.25-l.0-0.75-0.5-0.25
tI
-0.25: 10 20 30 40 50 60 70 80 90 100
-0.50+
VIN(V)
- ~ - t - 1-t-1- + I- + I- + I- + I--I-•---►
+-0.2
r-o.4
- - - - - - - - - -0.6
1- -0.8
I
L1.o
L1.2
t-1.4
r1.6
--1.8
I
(a)
~¥,r (
-1.501\
-1.75 _1_
.
V AND(V)
0 -----;____+---+-----+--+-+---+------+---+----+--> t(ns)
4
-0.25--"- 10 20 30 40 50 60 70 80 90 100
-0.50+
:~--~f'___,\
-1.25 -1.50-1.75 - -
-----✓
(b)
FIGURE 15.11 Results of Example 15.4 SPICE
Simulation of Figure 15.10 Series-gated ECL Gate:
(a) Voltage transfer characteristics of V!\JAND and VAND
outputs obtained from .DC sweep, (b) Transient
response verifying realization of logical NAND and AND
functions obtained from .TRAN sweep
15.6
DL2 34 23 DIODE
RBL 23 8 4-98KOHM
.MODEL QNPN NPN<IS=1E-14 BF=49
+ BR=D-2 VA=8O TF= □ -45NS
+ TR=SNS CCS=3PFD CJE=7-6PFD
+ CJC=3PFD R8=13 RC=b-2)
.MODEL DIODE D(VJ=O-75)
-DC VINA -2.ov DV □- □ 1V
.PLOT DC VC(QBN) VC(QBA)
.TRAN 1NS 1DDNS
. PLOT TRAN V<VINA) V(VINB)
+ VE(QBN) VE(QBA)
-END
Series Gating Complex OR-AND Gates
215
BJT is cJctive cJnd Q1,B is cutoff. Thus, the pcJrallel input
BJTs in each current switch provide an ORing of
signals.
ANDing of the ORings
The previous section showed that the series gating
of current switches produces a NANDing and an
ANDing of the inputs. The series gating of the current switch in Figure 15.12a produces a NANDing
and ANDing of the individual current switch ORing .
That is, the output at the common collector of Q 1A
and Qrn is the logical function
Ve);\/ = (V1, OR Vii) AND (V;1 OR Vil)
Figure 15.lla shows the voltage transfer characteristics for the NAND and AND outputs obtained from
the .DC sweep of the VINA input with the ViNB input
held high. Note that these VTCs are similar to those
of ECL NOR and OR outputs.
The transient response obtained from the
.TRAN sweep is shown in Figure 15.116. Observing
the output of this simulation, it is seen that the
NAND and AND functions are indeed realized.
15.6 SERIES GATING COMPLEX
OR-AND GATES
Series gated ECL NAND/AND gates can easily be
expanded to realize complex OR-AND-invert and
OR-AND logic functions. This is accomplished by
parallel connection of additional input BJTs at each
current switch. Figure 15.12a shows a four-input series-gated ECL current switch that realizes the logic
functions
=
(A
+
B)(C
+
D)
F=
(A
+
B)(C
+
D)
F
and
The output at the common collectors of QRA and QRB
is the logirnl function
Vo/\ = (V;1 OR VB) AND (V1 , OR Vii)
Recipe for Other Complex Logic Gates
Any combination of OR-ANDing along with the
complementing OR-AND-inverting can be obtained
by obeying the following five steps:
1.
ORing of signals is performed by parallel input
BJTs in a single emitter coupled switch.
2.
ANDing of ORed signals is performed by series
gating the individual current switches.
3.
Output buffers are taken from both collectors of
the top current switch.
4.
A multiple bias reference circuit is needed for
each level of series gating (ANDing); the temperature compensating bias network of Figure
15.9a provides two bias voltages: V1m and V(m-
5.
Inputs to emitter coupled switches below the top
switch, need to be divided down in a manner
similar to V1N 13 through Dui, Ruiv and Rui 2 in
Figure 15.9a.
The circuit symbol for this logic gate is shown in Figure 15.12b.
Example 15.5 Complex Series Gated ECL
Current Switch
Input ORing Sections
What logic function is performed by the six-input
ECL current switch of Figure 15.13a?
Examining the series-gated current switch of Figure
15.12a, if either VA or VB is high, the corresponding
input BJT is active and the reference BJT QR/\ is cutoff.
If either Ve or V1i is high, the corresponding input
Solution The ECL current switch of Figure 15.13a
has three levels of series gating. The top current
switch has two parallel input BJTs with inputs V1N/\
and Vrf'-:B and therefore performs the ORing A + B.
216
Chapter 15/Othcr ECL Gates
I
--~L-1
R.,.
t
-o V~ a (V, + VJ(V, + VJ
r--~
I
'
~~ t----DVee
-
X
~-~~~
_V
~~-~~
r,_
I
I
I
~
V!NC
-
~~~o~
~--~~~-J
(a)
-----·
INA
F =(A+ B)(C + D)
INC
F =(A+ B)(C + D)
IND
(b)
FIGURE 15.12 Series Gated ECL Complex OR-AND-invert/OR-AND (OAI/OA) Current Switch: (a) Circuit
schematic, (b) Logic symbol
The bottom current switch has three parallel input
BJTs with inputs V 1Nn, ViNE, and ViNF and performs
the ORing D + E + F. The series gating ANDs the
two ORing sections along with the V1Nc single input
current switch in the middle. The complementary
logic functions performed by this current switch are
therefore
F = (A + B)C(D + E + F)
and
F = (A + B)C(D + E + F)
15.7
ECL XOR/XNOR GATES
The series gating methods of the previous sections
can be applied to realize the XOR and XNOR logic
functions. Figure 15.14a shows a current switch configuration with dual single input emitter coupled
pairs (Q 1A1 & QRAi and Q 1A 2 & QR/d series gated
into a third single input emitter coupled pair (Q 18 &
QR 1i). The input VINA is connected to both input BJTs
Q 1;\ 1 and Q 1A 2 in the upper current switches. Likewise, the reference voltage V,m is connected to both
15.7
VOUTI
ECL XOR/XNOR Cates
Ymm=?
=?
VINA
VINB 0--
o-~
VINC
0---
(a)
INA-
F =(A+ B)C(D + E + F)
INB
INC------------1
IND
INE
INF-
F =(A+ B)C(D + E + F)
(b)
FIGURE 15.13 Six-input Series-gated ECL AND-ORlnvert/AND-OR Current Switch of Example 15.5:
(a) Circuit schematic, (b) Logic symbol schematic
217
218
Chapter 15/0ther ECL Gates
Ra
VXOR
/
VINA (
}--~-----f
Q..,
l~~-
(a)
INA
INA
j'L__/~
~
XNOR
XOR
(b)
FIGURE 15.14
Series Gated ECL XOR/XNOR Current Switch: (a) Circuit schematic, (b) Logic symbol
reference BJTs QRAi and QRAz• The input ViNll is connected to the input BJT Qm of the lower emitter coupled pair. Note that the reference voltage V{lll connected to the reference BJT QRB must meet the
condition
as described in the previous sections on series gating.
Logic Analysis
Both Inputs High
When both inputs are high, Q1J\ 1 and Qm are both
active and current flows through R0 . Therefore, the
Vxcw output is low.
QR,\l and QRB are both cutoff when both inputs
are high. Therefore no current flow through Rm and
the Yx:---:oR output is high.
15.7
Both Inputs Low
With both inputs low, since QRJ\ 2 and Q1,n arc both
active, current flows through R0 . Therefore, the Vxcw
output is also low when both inputs are low.
With both inputs low, Q 1A 2 and Qrn are both cutoff and no current can flow through RcR· Thus, the
Yx:--:cw output is high.
VINA
High,
VINn
Low
With V1:--:,\ high and V11'n low, Q 111 and Q 1v\ 2 are both
cutoff and the YxoR output is high.
For this combination of inputs, Q 1/\2 and QRB are
both active and current flows through Rm. Thus, the
Vx:--:oR output is low.
VINA
Low,
v,NB High
Finally, with V 101 A low and ViNB high, Q1Ai and QRB
are both cutoff. Therefore no current flows through
Rc 1 and the Vxm output is high.
ECL XOR/XNOR Gates
Additionally, QRAJ and Q 111 are active and draw
current through Rm. Thus, the Vxl'-:oR output is low.
Realization of XOR
and XNOR Logic Functions
The preceding four sub-sections clearly show that
the circuit of Figure 15.14a realizes the XOR and
XNOR logic functions. Figure 15.146 shows the logic
symbol for this logic gate.
15.8 ECL DECODING TREE
Circuit
A useful application of series gated ECL that deserves brief mention is the realization of decoding
trees. Figure 15.15 shows a two-input, four-output
decoder that exemplifies the concept. Two single-in-put emitter coupled pairs are series gated to a third
Vcc,n
Ra,!
- -
F,=AB o
VINA
I
7
Roi
F2 =AB
F,=AB
I/
I
Q,.,
"'1
1------------{
FIGURE 15.15
219
Quad ECL Current Switch Series Gated Decoding Tree
V'••
220
Chapter 15/Other ECL Gates
single-input emitter coupled pair. V1:--:A is applied to
the input BJTs of both upper emitter coupled pairs,
while V1N 13 is fed to the single input of the lower emitter coupled pair. Reference voltages V138 and V~B are
required with
Vall>
v~B
as described in earlier sections.
TABLE 15.1 Truth Table for Quad ECL Series
Decoding Tree of Figure 15.15
1
2
3
4
v!Nl
VINZ
F1
F2
F3
F4
0
0
1
1
0
1
0
1
0
1
1
1
1
0
1
1
1
1
0
1
1
1
1
0
Logic Realization
Examining the circuit of Figure 15.15 under all four
combinations of input logic levels, it is easily verified
that the four outputs realize the logic functions
F1 =AB
F2 =AB
F3 =AB
The truth table for all four outputs of this gate is
shown in Table 15.1. It is seen that each output is
brought low for a single combination of input logic
levels. This provides a method of designing complex
decoder circuits with relatively few circuit elements.
Verification of the logic functions for this circuit
is left as a homework problem.
and
CHAPTER15PROBLEMS
15.9
15.1
Using collector dotting wired-AND gates, draw the
schematic for a three-input AND gate.
15.2
Determine the critical voltages for the circuit of Figure 15.3a. Use V8 dECL) = VD(ON) = 0.75 V,
V8 c(SAT) = 0.6 V, and neglect base currents.
15.3
Calculate the bias voltages V813 and V{m in the circuit of Figure 15.9. Use VBE(ECL) = V0 (ON) = 0. 75
V and neglect base currents.
15.4
Calculate the critical voltages for the AND output
in the circuit of Figure 15.9. Use V8 E(ECL) =
V0 (ON) = 0.75 V and neglect base currents.
15.5
Using collector dotting wired-AND gates, draw the
schematic for a logic circuit that realizes the logic
function
F
= AB(C +
D)
15.10
Repeat Problem 15.9 using series gated ECL.
15.11
Using collector dotting wired-AND gates, draw the
schematic for a logic circuit that realizes the logic
function
F
15.12
Calculate the average power dissipation for the circuit of Figure 15.3a. Use V8 dECL) = V0 (ON) =
0.75 V and neglect base currents.
=
(A
+
B)(C
+
D)(E
+ F)
Using collector dotting wired-AND gates, draw the
schematic for a logic circuit that realizes the logic
function
F
= (A +
B)(C
+
D)(E
+ F)
15.6
Calcualte the average power dissipation for the circuit of Figure 15. 9. Use VBE(ECL) = Vn(ON) = 0. 75
V and neglect base currents.
15.13
Construct a truth table with ls and Os to verify that
the gate of Figure 15.13 produces the XOR logic
operation.
15.7
Draw the schematic for a logic circuit that realizes
the logic function
15.14
Construct a truth table with ls and Os to verify that
the gate of Figure 15.14 produces the XNOR logic
operation.
15.15
Verify the logic values in Table 15.1.
F
15.8
= A(B + C)
Repeat Problem 15.7 using series gated ECL.
METAL OXIDE
SEMICONDUCTOR
FIELD EFFECT
TRA SISTORS
The most important metal-oxide-semiconductor
field-effect-transistor for digital logic ICs is the silicon N-channel enhancement-only transistor. This
device has superior properties to those of the corresponding P-channel MOSFET due primarily to the
higher mobility of electrons. Furthermore, the en hancement-only MOSFET is nonnally off when no
voltages are applied making these devices ideal for
digital logic circuits. However, innovative circuit design using pairs of matched (complementary)
N-channel and P-channel MOSFETs has evolved
into the very effective, low power consuming CMOS
(complementary MOS) digital logic family. The fabrication sequences for silicon NMOSFETs and
CMOS circuits are shown in Figures 16.1, 16.2, and
16.10.
The NMOS family consists of logic elements
whose circuit components involve only N-channel
MOSFETs. The main device in each gate is an enhancement-only MOSFET. However, the load device
is either an enhancement-only or enhancementdepletion type MOSFET. Both NMOS and CMOS
digital IC families using silicon are used extensively
in VLSI and ULSI circuits because of the typically
small size of MOSFETs compared with BJTs and also
because of lower power dissipation.
This chapter describes the basics of silicon MOSFETs including geometry, current-voltage characteristics, parameters, and SPICE modelling.
In addition to the usual device fabrication steps consisting of source/drain formation, thin oxide growth
and metalization, there are two other important processes. These are the p+ implant everywhere outside
the active MOSFET device area and the channel im plant. The p+ implant creates surface regions that do
not invert to N-type and are necessary in order to
isolate adjacent devices. The channel implant is used
to adjust the threshold voltage to a desired value.
Note that the oxide layer above the channel stop
regions is much thicker than the gate oxide. This
thicker oxidation is referred to as the thick oxide or
field oxide and is usually about one to two orders of
magnitude larger than the thin gate oxide.
16.2 SILICON GATE
N-CHANNEL MOSFETs
Figure 16.2 displays the fabrication sequence for the
N-channel polysilicon gate MOSFET. In this sequence a silicon nitride (Si 3 N4) layer is used as a
mask for the implanted p+ -channel stop region.
Then, the field oxide is grown with Si 3 N 4 inhibiting
growth in the active transistor region. The other processing steps are essentially the same as the metal
gate case.
16.3 MOSFET MODES
OF OPERATION
16.1 METAL GATE
N-CHANNEL MOSFETs
The circuit symbol for the N-channel MOSFET is
shown in Figure 16.3a. Note that the source and
body (substrate) are connected. This is not always
the case as shown in Figure 16.3d.
The basic processing sequence for silicon N-channel
MOSFETs with metal gate is displayed in Figure 16.1.
221
222
Chapter 16/Metal Oxide Semiconductor Field Effect Transistors
Si0 2
P+
I
gate oxide
\
Si02
'::::,
Si02
D
G
\ P+
(a)
r
s
P substrate
{
@I
B
~
(d)
P substrate
G
(b)
Si02
Si02
1mpant
(e)
gate oxide
P substrate
(c)
FIGURE 16.1
Basic Processing Sequence for Silicon
N-channel M0SFET with Metal Gate: (a) Source/drain
N+ diffusion/implant, (b) Channel stop P+ implant,
(c) Channel implant and gate oxide growth, (d) Metal
deposition and etch, (c) Layout defining channel width
W and length L
Threshold Voltage
TABLE 16.1
Voltage
In order for drain current to flow from drain to source
in an N-channel MOSFET, the gate-to-source voltage must be greater than the specific device threshold voltage VT and the drain-to-source voltage must
be greater than zero. The threshold voltage is dependent upon the physical dimensions and parameters of the MOS device as discussed shortly. For the
enhancement-only NMOS transistor, the threshold
voltage is positive and for the enhancement-depletion NMOS, the threshold voltage is negative. For
PMOS devices, the threshold voltage is opposite in
sign to the corresponding NMOS. The threshold
voltage signs are tabulated in Table 16.1.
Cutoff
If the gate-to-source voltage V cs for a NMOS device
is less than the threshold voltage, the NMOS device
is in the cutoff mode of operation and no drain cur-
Signs of MOSFET Threshold
NMOS
Enhancement-only
Enhancement-depletion
rent flows in the channel (ID
indicated in Figure 16.3a.
PMOS
+
+
= O). This situation is
Linear tviode
As Yes is increased above Vr, a drain current conducts as indicated in Figure 16.3b for VDs > 0. For
VDs ~ Vc;s - VT the NMOS device is in the linear
mode of operation and the drain current expression
for this mode is given by
16.3
\
M0SFET Modes of Operation
223
~SiO~\
gate oxide
-7
P+
(a)
polysilicon
P+
P+
P substrate
(d)
gate oxide
P+
P+
\_
p substrate
~---~
______
1::n1-i
(b)
LJ'Y
olysilicon
....... :
______ ]'_
(e)
(c)
Basic Processing Sequence for Silicon
N-channel M0SFET with Polysilicon Gate: (a) Gate
oxide growth, Si 0 N 4 growth and etch, channel stop
implant, thick oxide growth, (b) Si 0 N4 removal, polysilicon
deposition, (c) Etch polysilicon and source/drain N +
implant, (d) Metal deposition and etch and passivation
layer deposition, (e) Layout defining channel width W
and length L
as shown in Figure 16.3b, where k is a transconductance parameter described in more detail in section
16.4.
lowing empirical equation:
FIGURE 16.2
nel-length modulation parameter,\ and using the fol-
h)(SAT)
Saturation Mode
As VDs is increased with Yes> VT and VDs 2: Yes VT, the NMOS device operates in the saturation
mode sometimes referred to as FET saturation. The
drain current expression for the saturation mode is
given by
This expression indicates that the saturation drain
current has no dependence on VDs• This is not entirely true in the actual case and the variation with
VDs is sometimes accounted for by specifying a chan-
=
k
2 (Vcs
,
- Vy)·(l
+ ,\V05)
The voltage and current expressions for the saturation mode of operation are shown in Figure
16.3c.
Family of Curves
Figure 16.4 shows a family of current-voltage characteristics for a N-channel MOSFET. The drain current ID is plotted versus the voltage V Ds with Vcs as
a paraIT1eter. Note that unlike the family of curves
for the BJT, ID does not increase approximately linearly for equal increments in the input parameter,
Yes, This is a result of the quadratic dependence of
224
Chapter 16/Metal Oxide Semiconductor Field Effect Transistors
DI
I,,=0 ___.
~-~
+
H
Yos<VT
V 00 •oon-,em
I
-6
s
s
(a) cutoff mode
(b) linear mode
VT(VSB > 0) = Yro + 'YL( ✓v•• + 2cp,; - ~ )
J
Ia= 0
___.
~ ~]
V >V
OS -
+
8
-1-
Vos= non-zero
Yos<O
T
s
(c) saturation mode
FIGURE 16.3 MOSFET Modes of Operation:
(a) Cutoff mode, (b) Linear mode, (c) Saturation mode,
ID on Vcs- The linear mode of operation is to the left
of the V0 s = Vcs - VT dashed curve and the saturation mode is to the right. As with the BJT, the cutoff
mode of operation is defined to be the region where
all currents are zero and I0 = 0.
Which Way Is Up?
In section 3.3 the reverse-action mode for the BJT
was described. This involves operating the BJT
"backwards," that is, reversing the positions of the
fabricated emitter and collector. However, due to
the inherent symmetric fabrication of MOSFETs, the
source and drain are interchangeable. Thus, there is
no reverse-active mode of operation for MOSFETs.
Often, the desired source region is connected to the
body (substrate) and this therefore defines which
end of the channel is the source.
As already mentioned, not all MOSFETs in ICs
can have their sources connected to the body. The
drain is then defined as the channel side region at a
(d) body-bias effect on threshold voltage
(d) Body-bias effect on threshold voltage
i
I
Yos(V)
FIGURE 16.4 MOSFET Family of II) versus VDs Curves
with Vcs as a Parameter
16.4
MOSFET Transconductance Parameter
lower potential (source)
higher potential (drain)
+
DC
Ii~'
7,~1
•
'
g .
I
V>O
--OB
---·
J
g_ l:------a
_,..../
B
I
l
'
s --.. . . . . . . _________-
lower potential (source)
'~
····•..........
+-
higher potential (drain)
(b)
(a)
FIGURE 16,5
225
Determination of Drain and Source for Symmetric NMOS, i.e. body not tied to either end of channel
higher voltage, while the source is the channel side
at a lower voltage. Hence, the voltage relationship
Vi,s
2:
0
is always true for an active N-channel MOSFET and
if VDs changes sign, the source and drain are interchanged. Figure 16.5a and b demonstrate NMOS devices where alternate regions are used as the source
and then the drain.
Example 16.1
Calculation
NMOS Drain Current
An NMOS transistor has k = 20µA/V 2 and VTo = 1
V. Assume YL = 0. Find the drain current for the
edge of saturation (i.e. V0 5 = VGs - VT) for VGs = 3
V using both the linear and saturation drain current
expressions.
Solution The drain-source voltage at the edge of
saturation is
V0 5 = (3) - (1) = 2 V
Using the linear drain current expression:
Using the saturation drain current expression:
2
I 0 (SAT) = ( 0µ,) (3 - 1) 2 = 40 µA
2
with both expressions agreeing, which was expected.
16.4 MOSFET
TRANSCONDUCTANCE PARAMETER
The previous section introduced the transconductance parameter kin the current-voltage expressions
for the linear and saturation modes of MOSFET operation. Examining these expressions shows that k
has units of A/V2 • The magnitude of k for a MOSFET
is a direct function of the physical characteristics of
the device.
Device Transconductance
Parameter = k
The parameter k, more appropriately referred to as
the device transconductance parameter of a MOSFET,
is related to the channel width and length by the
expression
k = k' W
L
where k' is referred to as the process transconductance
parameter. k is called the device transconductance parameter because of its relationship to the channel
width and length, which are determined individually
for each separate device (MOSFET). Figures 16.le
and 16.2e show the top views of metal gate and silicon gate N-channel MOSFETs, respectively, with
the widths and lengths of the channels labeled.
Process Transconductance
Parameter= k'
The process transconductance parameter is determined from the expression
k' = µ,Cbx
226
Chapter 16/Metal Oxide Semiconductor Field Effect Transistors
where µ, is the mobility and C()x is the gate oxide
capacitance per unit area. k' is called the process
transconductance parameter because its value is determined by the fabrication process and all MOSFETs
on a given IC have the same k'.
For N-channel MOSFETs, typically
0
/J,N
cnr
= 580 - V·s
Also, the hole mobility for P-channel MOSFETs is
typically
= 230
The threshold voltage of a typical silicon MOSFET
depends upon the device geometry as well as material parameters. The expression for VT with V58 =
0 (that is, zero body-to-source bias) is referred to as
the zero body-bias threshold voltage and is given
by
Vrn =
-l<bMsl - l2¢FI -
-v
.s
<b Ms
Gate Capacitance Per Unit Area
Cbx
The gate capacitance per unit area of a MOSFET is
inversely proportional to the gate oxide thickness
tox:
=
(per unit area)
C' - Eox
ox - tax
where Eox is the permittivity of the gate oxide and is
related to the permittivity of vacuum by the relation
Eox
= k0 x
X
E0
= 3.9
X
Eo
where k0 x is the dielectric constant of SiO 2 .
For SiO 2 , Eox has the value
Eox
lzLI l~i:I
+
Z:x
Each of the terms in this expression are defined as
follows:
C/112
jl,p
Zero Body Bias Threshold Voltage
= 3.45 X 10-t3 I_
cm
MOSFET capacitances are explained in more detail
in section 16.7.
16.5 MOSFET THRESHOLD
VOLTAGE
One of the most important parameters for a MOSFET is the threshold voltage VT. The usual definition
of this parameter is as follows: the threshold voltage
is the critical gate bias voltage at which conduction
between the source and drain can be initiated.
Hence, if the gate to source bias voltage is less than
VT, the drain current is zero:
<b F
Qf3
Q~ 5
= difference of gate-metal and silicon
work functions [V]
= surface potential [V]
= surface depletion region charge per
unit area [C/cni]
= surface state charge per unit area asso-
ciated with Si-SiO 2 interface states
[C/cm 2 ]
Q1 = ion implantation into the channel region [C/cm 2 ]
Note that all terms are negative except for the last
term. Q1 represents ion implantation into the channel region that is necessary to make VTo positive.
Also, the primes indicate per unit area.
Body Bias Dependence
of Threshold Voltage
Figures 16.3b and c show the body (or substrate)
connected to the source for both the linear and saturation modes of operation. In integrated circuits
employing many MOSFETs, this is generally not the
case. With the body and source not connected, there
will then be a non-zero source-body voltage V58, as
shown in Figure 16.3d. The voltage V58 is referred to
as a body-bias. The presence of a body-bias voltage
has the effect of shifting the threshold voltage. The
threshold voltage dependence on the body-bias is
described by the expression
Vy(Vsll > 0) = Vrn
+ y1,(YVsB +
2¢F - ~ )
where VTo is the zero body-bias threshold voltage,
YL is a body-effect coefficient, and <b F is the surface
potential from the previous sub-section.
1G.7
Example 16.2
Calculation
MOSFET Capacitances
227
v"'(VBS,P > o) = vTO,P - ye( ✓v BS,P + 2 I$r.1 - ✓2 I$r. I )
NMOS Threshold Voltage
+
For the MOSFET of Example 16.1, calculate the
threshold voltage for a body-bias of 3 V. Use YL =
112
0.54 V , and 2</>" = 0.6 V.
Solution For VsB = 3 V, by direct substitution the
threshold voltage is obtained as
Vr = (1) + (0.54) [V (3) + (0.6) = 1.61 V
\/(o.6)]
PMOS drain
current is out
of drain
~ +Ioy(SAT) ~
=
(Vso.P + VTP)2
or
10 .P(LIN) = kp [<Vso.P + VTP)Vso,P - V\o.P -I
-
16.6
2 -
P-CHANNEL MOSFET
The modes of operation for a P-channel MOSFET
are the same as those for the N-channel MOSFET.
The drain current expressions are identical in form
with the voltage polarities and current directions reversed. Using the polarities and current directions
shown in Figure 16.6 the PMOS modes of operation
and threshold voltage are described by the following
expressions using P subscripts to denote PMOS.
FIGURE 16.6 P-channel MOSFET, Reversal of Voltage
Subscripts and Current Direction
Threshold Voltage
• Enhancement-only == VTo.P < 0
• Enhancement-depletion == VTo,P > 0
• Body bias effect ==
Vn, =
• Cutoff== Vsc,r
:S
-VT!'
2: -VT!'
yp(\!VBs,J> + 21</>rpl
~)
• Zero body-bias threshold voltage == VT 0, 1,
Io,r(OFF)
• Linear == V scy
Vro,!' -
=0
and V soy
:S
Vsc,r +
16.7
MOSFET CAPACITANCES
VT!'
Vio,P]
-
[
lny(UN) = lcr (V,c;,r + Vrr)Vsn.P - -
• Saturation== Vsc, 1,
2: -Vn,
and V 50 y
2:
2
Vscy
+ Vn,
or
Note that the polarity change in voltage for
PMOS is accompanied by reversing the subscripts.
The sign change in the drain current is achieved by
reversing the positive current direction in Figure
16.6.
The capacitances associated with a MOSFET can be
modeled as shown in Figure 16.7. A capacitance exists between each pair of terminals except the source
and drain.
Junction Capacitances
The capacitances CBs and C1m are PN junction capacitances between either the source or drain and
the body (substrate). These can be calculated by the
relations
228
Chapter 16/Mctal Oxide Semiconductor Field Effect Transistors
C(1x = gate capacitance per unit area of the
gate dielectric [Finl] given by
D
y
Coo
C.o
' _ Eox
C ox -
tax
~--10--------~-'-------r-------------t/ (,_____._~
+
+
G
Eox
= permittivity of Si0
t0 x
= gate oxide thickness
2 = k 0 xEo = 3.45 X
10- 13 Flem
kox = dielectric constant of Si0 2 = 3.9
E0 = permittivity of vacuum 8.85 X 10- 14
Yoo
Flem
B
Vos
Cos
16.8
+
SPICE MOSFET MODEL
Yoe
This section introduces the SPICE MOSFET model and
.the physical significance of each of the SPICE MOSFET
model parameters.
Coe
s
FIGURE 16. 7
D
MOSFET Capacitances
__; RoJ
C.o
I
where
CHso & C 1mo
= zero-bias junction capacitances
Yeo
[Fl
l<l
<p sB & <p u 11 = junction potentials (typically
0.9 to 1 V)
mll
= grading coefficient (m
or 1/3)
8
=
¢10
½
I
Gate Oxide Capacitances
Yes
c..
The capacitances Ccs, Ccu, and Cell between the
gate and over the thin oxide overlapping the remaining semiconductor regions are due to the physical overlap area between the gate and these regions.
A simple approximation for the relationship between
these capacitance values (that neglects fringing electrical fields) is that the sum of these is equal to the
total gate capacitance or
Ccs + Ceo+ Cell
Rs
= Cc = WLC[ix
0
where
s
W
L
= channel width [ml
= channel length [m]
FIGURE 16.8
SPICE MOSFET Model
B
16.8
The MOSFET model used by SPICE to calculate
operating characteristics is shown in Figure 16.8.
SPICE MOSFET DC Characteristic
SPICE MOSFET Transient Response
Table 16.3 displays the SPICE MOSFET parameters
for transient response calculations. The transition capacitances are calculated by
The drain current is calculated from
lu
width [
= KP length Wes -
x
(1
VTWos -
229
SPICE MOSFET Model
Vfisj
C/ls
2
=
n
CJ sarea
Vss
+
.
C]SW spenm
1--
PB
+ LAMBDAV05 )
and
In =
KP width
2
length
Wes - Vy)2(1 + LAMBDAVns)
C80
for VDs > Vcs - V 1. Note that the width and length
are not model parameters and are specified on separate device lines. The threshold voltage is calculated
from
VT= VTO
+ GAMMA(\/PHI + Vs/l - \/PHi)
Table 16.2 displays the parameters that are used to
calculate the DC response of the SPICE MOSFET.
Note that parasitic resistances for the drain, source,
gate, and body regions arc parameters.
TABLE 16.2
SPICE DC MOSFET Model Parameters
Symbol
Name
Vrn
k'
VTO
KP
GAMMA
PHI
LAMBDA
RD
RS
RG
RB
RDS
RSH
NSUB
NSS
NFS
TPG
XJ
LD
uo
VMAX
XQC
=
Hi
CJ darea
Vim
1--
PB
where the first term in each expression is the bulk
junction bottom capacitance and the second term is
the bulk junction sidewall capacitance. sarea,
sperim, darea, and dperim are also not model parameters and are specified on device lines. These parameters refer to the source and drain areas and
perimeters. Alternatively, CBS,CBD, and MJ, and
Parameter
Zero-bias threshold voltage
Transconductance
Bulk threshold parameter
Surface potential
Channel-length modulation factor
Drain resistance
Source resistance
Gate resistance
Bulk resistance
Drain-source shunt resistance
Drain and source diffusion sheet resistance
Substrate doping density
Surface state density
Fast surface state density
Gate material type
+1
opposite to substrate
-1
same as substrate
0 = aluminum
Metallurgic junction depth
Lateral diffusion
Surface mobility
Maximum drift velocity
Fraction of channel length attributed to drain
=
=
+ C]SW dperim
Units
V
A!V2
y'V
V
V'
D,
D,
D,
D,
D,
!1/□
l/cm 3
1/cm 2
1/cm 2
+1
m
m
cm 2 N · s
m/s
Default
Typical
0
2E-5
0
0.6
0
0
0
0
0
1.0
3. lE-5
0.37
0.65
0.02
1.0
1.0
0.1
0.1
co
0
0
0
0
10.0
4.0E15
1.0ElO
1.0ElO
0.0
0.0
600
0.0
1
1U
0.8U
700
5.0E4
0.4
230
Chapter 16/Metal Oxide Semiconductor Field Effect Transistors
TABLE 16.3
SPICE Transient MOSFET Model Parameters
Symbol
Name
Parameter
Cimo
CBSO
CBD
CBS
IS
PB
FC
CGSO
Zero-bias bulk-drain junction capacitance
Zero-bias bulk-source junction capacitance
Bulk junction saturation capacitance
Bulk junction potential
Forward-bias depletion capacitance coefficient
Gate-source overlap capacitance per meter channel
width
Gate-drain overlap capacitance per meter channel
width
Gate-bulk overlap capacitance per n1eter channel
length
Zero-bias bulk junction bottom capacitance per
square meter of junction area
Bulk junction bottom grading coefficient
Zero-bias bulk junction capacitance per meter of
junction perimeter
Bulk junction sidewall grading coefficient
Bulk junction saturation current per square meter
of junction area
Oxide thickness
<pBS
CGDO
rrnA
\......\JUV
CJ
m;-;
MJ
CJSW
MSJW
JS
tax
TOX
Units
Default
Typical
0
0
lE-14
0.8
0.5
0
20FF
20FF
1.0E-15
0.87
4.0E-11
·F/m
0
4.0E-11
rill\
r' I .• -
0
2.0E-10
F/m 2
0
2.0E-4
F/m
0.5
0
0.5
1.0E-9
A/m 2
0.33
0
1.0E-8
m
lE-7
1.0E-7
F
F
A
V
F/m
FC can be specified and the transition capacitances
are calculated from
CBS
V BS
PB )
Ml
GN (polysilicon)
passivation
\
\
and
C,o
~
';ff'
CBD
(, _
P substrate
(a)
For the gate capacitance, the three overlap capacitances are calculated separately:
Ccs = width
x CGSO
Ceo = width x CGDO
and
CcB = width X CGBO
Note that TOX must be specified in order for SPICE
to calculate the gate capacitances.
16.9
CMOS Devices
Since CMOS uses complementary N- and P-channel
MOSFETs in pairs, portions of the semiconductor
N substrate
(b)
FIGURE 16,9 CMOS Cross Sections (a) N-well CMOS
process: P-substrate with PMOS device built inside
N-wells, (b) P-well CMOS process: N-substrate with
NMOS device built inside P-wells
16.9
surface must be N-type and nearby also P-type. Figure 16.9 shows two different cross sections with
complementary MOSFETs that have been used to
achieve CMOS digital ICs. Note that Figure 16.9a
starts with a P-type substrate and the N-tub at the
surface is formed by diffusion/implantation. On the
other hand, Figure 16.9b starts with the opposite
type substrate and hence the P-tub must be manufactured into the surface. In the past, either of these
structures resulted in adequate circuit performance.
Twin Tub CMOS Process
Figure 16.10 displays a modern process sequence
used for CMOS. Note that in this case, both tubs are
manufactured into the surface of a lightly doped Nregion. The resulting cross section is referred to as a
huin-tub CMOS structure. In the first processing step,
phosphorous is implanted into the surface with a nitride layer n,asking the adjacent surface region. The
CMOS Devices
231
implant goes directly through a thin oxide which reduces surface damage of the silicon from the implant.
This is followed by a thick oxide growth (which
spreads the implanted impurities downward into the
substrate), nitride removal, and a boron implant
again through the thin oxide for surface protection.
Thick oxide growth then spreads the P-type impurities downward. Thick oxide removal and thin oxide
growth then results in the cross-section of Figure
16.10c.
To complete the fabrication of the complementary MOSFETs, gate oxide growth and polysilicon
deposition followed by source/drain ion implants for
both the P- and N-channel devices are carried out.
The resulting cross section after the Boron and Phosphorus implants is shown in Figure 16.10d. The techniques used are entirely analogous to the NMOS
case described in the previous section. The resulting
cross-section, after deposition of metalization and a
passivation layer is shown in Figure 16.lOe. This is
Sl,N,
\
'------------;
~
N- substrate
(a)
N- substrate
thick oxide
(d)
phosphorus glass
(b)
GN (polysilicon)
s.
-~
\
G. (polysilicon)
DN
field oxide
_P_w_e_ll_ _ _ _ _ A·----~N~w=e'~'____,
N- substrate
1
N- substrate
(e)
(c)
FIGURE 16.10 Basic Processing Steps for Twin Tub
CMOS Process with Silicon Gate: (a) Phosphorous
implant, (b) Grow thick oxide, remove Si,N4 , boron
implant, (c) Diffusion/drive-in to form N and P wells and
thick oxide, (d) Source/drain implant, thin gate oxide,
polysilicon deposition, and etch, (e) Metal deposition and
etch, phosphorous glass deposition
232
Chapter 16/Metal Oxide Semiconductor Field Effect Transistors
the final cross-section for the CMOS twin tub process.
other (top) capacitor plate. The capacitance associated with this capacitor is
C = k0 xE0 A = EoxA
d
16.10 INTEGRATED CIRCUIT
CAPACITORS
d
where
kox = dielectric constant of SiO2 = 3.9
E0 = permittivity of free space
= 8.85 X 10- 14 Flem
d
oxide thickness
A - ovcrlJy area of parallel plates
Eo
permittivity of SiO 2
= 3.45 x 10- i:i Flem
The usual capacitor used with silicon integrated circuits is the metal-oxide-semiconductor (MOS) parallelplate capacitor shown in Figure 16.11. This device is
fabricated by growing a thin SiO 2 layer over an N+
emitter surface region that becomes the bottom capacitor plate. The last step in fabrication is to deposit
metal on top of the thin oxide and this becomes the
=
=
The parallel plate MOS capacitor structure of
Figure 16.11 is compatible with the double diffused
epitaxial BJT family as well as the NMOS and CMOS
families. Since the magnitude of the capacitance depends directly on the overlap area of the two parallel
plates, large values of capacitance require large chip
areas.
P substrate
MOS Parallel Plate Capacitor
FIGURE 16.11
CHAPTER 16 PROBLEMS
16.1
Outline the basic processing steps for the fabrication of a NMOS transistor.
16.2
Repeat Problem 16.1 for CMOS devices.
16.3
Draw the two-dimensional cross-section of a
NMOS transistor and label the different regions.
Be sure to indicate the relative doping densities, i.e.
N , N, N ', p·-, P, or P'.
16.4
Repeat Problem 16.3 for the CMOS configuration.
16.5
For the CMOS configuration of Figure P16.5.
(a) find all the successive NPN layers
(b) find all the successive PNP layers
(As will be seen in Chapter 23 these NPN and
passivation
••
)
GN (polysilicon)G (
• po 1ys1 1icon
1
I
16.6
Sketch the drain-source current-voltage characteristics for a MOSFET with drain current in mA given
by
s(1 + Vtr
lr,(SAT) =
16.7
Repeat Problem 16.6 for
In(SAT) =
16.8
s(
-1 +
V;~sr
Repeat Problem 16.6 for
li,(SAT) = 5Wcs - 1)2
16.9
What type of NPN BJT (i.e. type of isolation) is
compatible with the parallel-plate capacitor of Figure 16.11?
16.10
Using typical values from the SPICE MOSFET tables, derive and plot ID(LIN) and ID(SAT). Let W/
L = 10 and use five different values for Vcs- Also,
V11s = 0.
"
N substrate
FIGURE P16.5
PNP layers act as BJTs and are responsible for
a CMOS operational problem called latch-up.)
Chapter 16
16.11
Calculate the threshold voltage for body bias voltages of 1, 2, 3 V. Use the typical SPICE parameters
from the tables.
16.12
Calculate the gate capacitance for a MOS capacitor
made of Al-SiOrSi. Use L = 5 µm, W = 20 µm,
and t0 x = 0.07 µm.
16.13
Repeat Problem 16.12 for t0 x = 50
A and 2000 A.
Problems
233
16.14
Outline the basic processing steps for the fabrication of a MOS parallel-plate capacitor.
16.15
Draw the two-dimensional cross section of a MOS
parallel-plate capacitor and label each region (including re!Jtive doping densities).
17
INTRODUCTION
TO MOS DIGITAL
CIRCUITS
There are several important MOS logic families used
to manufacture digital integrated circuits. The most
important of these are called NMOS, CMOS, and
HCMOS. Each of these families use only MOSFET
transistors, not only as the active devices but also as
load elements. For the case of NMOS, only N-channel transistors are used whereas in CMOS and
HCMOS, pairs of N-channel and P-channel devices
are used. The "C'' stands for f_omplementary, since the
N-channel and P-channel transistors complement
each other. "H" stands for h_igh density and ftigh
speed.
It should be mentioned that PN junction diodes
are sometimes used at MOS logic circuit inputs to
protect the gates from static charge buildup and destruction. However, these devices are not used as actual logic circuit elements in MOSFET families.
In this chapter, the discussion emphasizes
N-channel MOSFETs. Furthermore, enhancementonly MOSFETs are emphasized since they are the
primary devices used in MOS digital logic families.
17.1
the gate current le of a MOSFET is essentially zero.
The output is taken at the drain, and thus
Note that the voltage V1, across the load in Figure
17.1 can be directly expressed as a function of the
output as follows:
Vi.
=
VLWow) = Voo - VouT
Also, since the input current is negligible, the current
though the load is equal to the drain current through
the channel of the MOSFET:
I0 = Ir_
These relations between the voltages and currents of
the inverting NMOS and the load device are used to
detennine the inverter VTC and power dissipation
for NMOS.
As will be seen in later chapters, digital circuits
employing MOSFET technologies are qualitatively
no more complex than the general NMOS inverter
presented here.
GENERAL NMOS INVERTER
17.2 THE ZERO DRAIN CURRENT
ACTIVE MOSFET
A MOSFET can be used to achieve logic inversion in
the same fashion as the BJT inverter in section 4.2.
The generalized NMOS inverter is shown in Figure
17.1. The load device may be a resistor, like that used
in the BJT inverter, but in an actual MOSFET inverter
a better choice for a load is another MOSFET, as will
be seen. The input to this inverter is applied directly
to the gate. Hence, the input voltage is equal to the
gate-to-source voltage
Before demonstrating methods for solving operation
of MOS logic circuits, the current-voltage characteristic of MOSFETs with small drain-to-source voltages must be studied.
N-Channel MOSFET Linear Mode
of Operation
In section 16.3, an N-channel MOSFET with terminal voltages meeting the condition
ViN = Vcs
No input resistor (corresponding to RB for the BJT
inverter) is needed to limit the input current since
Vos< Vcs - VT
234
(linear mode)
17.2
The Zero Drain Current Active MOSFET
235
NMOS Active Operation
In addition to the above inequality relating V05 and
Vcs, the gate-to-source voltage must meet the condition
Vcs
> VT
(active operation)
in order to bring the NMOS device into active operation.
Operation of N-Channel MOSFET
with Zero Drain Current
FIGURE 17.1
Generic Load
General NMOS Inverter Shown with a
was said to operate in the linear mode of operation.
An NMOS transistor in the linear mode has a drain
current of
In(LIN)
=
klI(Vc;s -
V,)VDs
TJsj
V
2
This expression shows a drain current dependent
upon both the gate-to-source voltage Vcs and drainto-source (channel) voltage Vos-
In this section, it will be shown that an N-channel
MOSFET meeting the Vcs > VT condition is still in
active operation even with zero drain current. This
can be shown both graphically and analytically.
Graphical Analysis of NMOS Device
with Zero Drain Current
Figure 17.2a show a single I0 versus Vos curve for a
N-channel MOSFET with a constant Vcs• When VDs
< Vcs - VT (i.e. when VDs is small) the NMOS device is in the linear mode of operation. If the drain
current in a NMOS device described by this curve is
forced to take on smaller and smaller magnitudes,
the drain-to-source voltage also takes on smaller and
smaller magnitudes.
If the drain current is forced close to ID = 0, then
Io(LIN) = 0 for Vos = 0
(MOSFET is still active)
(a)
FIGURE 17.2 (a) Current voltage characteristic of a Nchannel MOSFET with Yes= 5 Y-constant; if ID is
forced low while Ycs is held constant (at a voltage
greater than Y1 ), YDs also decreases (b) Resistor loaded
(b)
N-channel MOSFET with Yes= 5 Y; as RL increases,
II) = IRL decreases, this represents the current-voltage
curve of (a)
236
Chapter 17/Introduction to MOS Digital Circuits
the drain-to-source voltage will also be forced close
to zero:
Indeed, examining the curve of Figure 17.2a, if the
drain current is forced all the way to zero, the drainto-source voltage will also be zero:
[0
= 0
⇒
V05 = 0
Note that this discussion of decreasingly smaller
r11rrr-'.lntc: has taken place vvhile the gateto-source voltage has maintained the requirement
Yes > VT necessary to keep the NMOS device in
active operation.
This graphical analysis has shown that an active
NMOS device whose drain current is forced low, will
have a correspondingly small drain-to-source voltage and
Rewriting as a quadratic in V1is yields
Vf)s - 2(V(~S - Vr) Vns = 0
This has the solutions VDs = 0 and VDs = 2(Vcs Vr). Since the second of these solutions does not
meet the Vos < Vcs - V1 condition necessary to
guarantee the linear mode of operation, the drainto-source voltage for an N-channel MOSFET with
zero drain current is
r1r;-iln
an active MOSFET with zero drain
current has a drain-to-source voltage of
zero
General NMOS Inverter with an Increasing
Resistor Load
The previous graphical analysis in the previous section describes an NMOS inverter with a constant
gate-to-source voltage and an increasingly resistive
load, as indicated in Figure 17.2b. Clearly, the drain
current is equal to the load resistor current
lo =
II<L
As the load resistance increases, the current ID = I1s1_
decreases, and the voltage V NOT = V05 decreases:
Analytical Analysis of NMOS Device
with Zero Drain Current
The drain-to-source voltage for an N-channel MOSFET with zero drain current can also be obtained analytically. Setting I 0 = 0 in the linear mode drain
current expression gives
0
= k [ Wes
- VT)VDs -
vis]
2
Multiplying both sides by 2/k gives
0 = 2Wcs - V.r)VDS -
vis
N-Channel MOSFET as an Output
Pull-Down Device
The previous sub-sections show the usefulness of the
N-channel MOSFET as an output pull-down device.
With proper selection of a load device, a high gateto-source voltage results in a low drain-to-source
voltage. In Chapter 23 it is shown that the zero-drain
current active MOSFET is the basis for the superior
input-to-output voltage transfer and low power dissipation of the MOSFET logic family known as Complementary Metal-Oxide Semiconductor (CMOS)
logic.
Resistance of Drain-to-Source
Channel of NMOS Device Operating
in Linear Mode
Example 17 .1
What is the resistance of the drain-to-source channel
of an NMOS transistor operating in the linear mode
for Vos= 3, 2, 1, and O V? Assume Vcs = 5 V, VT=
1 V, and k = 40 µ,AN 2 .
Solution For VDs = 3, 2, 1, and OV and Vcs = 5 V,
a MOSFET with a threshold voltage of 1 V is in the
linear mode of operation. The resistance of the drainto-source channel can then be found by taking a derivative of the linear mode drain current expression
as follows:
RDS=
d~:sl
Vr;,
= [
c::J-11,;,
= (k[(VGs - Vi) - VusW 1
or
17.3
Substituting values for each magnitude of V1is yields
Rns(Vns
=
1
(40µ,)[(5) - (1) - (3)]
3 V)
= 25
RosWos
kfl
1
(40µ)[(5) - (1) - (2)]
= 2 V)
= 12.5
RosWns
kn
1
(40µ,)[(5) - (1) - (1)]
= l V)
= 8.33 Hl
Rns(Vos
1
(40µ)[ (5) - (1)
= 0 V)
(O)]
= 6.25 kn
Examining these values, it is seen that the lower the
drain-to-source voltage, the lower the resistivity of
the drain-to-source channel. Alternatively, this can
be viewed as progressively increasing channel conductances:
GDs(Vos
= 3 V) =
r:-:1 I
GnsWns = 2 V) = - 1 I
Ros v,,s=2V
Gos(Vns
= 1 V) =
= 25 1kn= 40 µ,u
Vc,=3V
OS
=
f-1
G05 (V05
= 0 V) = - 1
1
Ros
I
v,;s=OV
=
23 7
transistor. Furthermore, a given relationship be
tween the current IL and voltage V L for the load device exists, that is, IL = IL(V 1J Hence, since the drain
current (either the linear or saturation) expression is
known, a system of two equations with two unknowns exists. The two unknowns are ID and VDs
and the two equations relating them are the load
equation IL = IL(V os) and the 10 versus V0 s MOSFET
relation.
Superimposing the load curve (in terms of V0 s)
over the family of curves for the inverter transistor
gives rise to a graphical solution for the VTC of the
NMOS inverter. This is done in Figure 17.3a for a
load device with linear IL versus VL. The intersection
between the family of curves and the load line is
marked in five places, labeled A, B, C, D, and E. For
each of these points, the input and output voltage,
respectively, can be read from the particular Vcs
curve and the vertical axis. Plotting these five ordered
pairs of (Vcs, VDs) on Vos versus Vcs coordinate axes,
graphically determines the VTC. Figure 17.3b shows
these plotted points with a smooth curve connecting
them to complete the VTC. This method of VTC determination is demonstrated in the following
example.
1 kn= 80 f-lU
12.5
s.33
DS \/c;s=lV
Graphical Solution of the NMOS Inverter
kn =
1 kn
6.25 ~ L
120
µu
= 160 µ,u
In this example, it is shown that N-channel
MOSFETs operating in the linear mode of operation
become more conductive as the drain-to-source
voltage decreases. This provides further support for
using an NMOS device as an output pull-down device.
17.3 GRAPHICAL SOLUTION
OF THE NMOS INVERTER
The previous section has shown that the voltage and
current of the load device can each be expressed in
terms of the voltage and current of the inverting
Example 17 .2
Inverter VTC
Graphical Solution of NMOS
Figure 17.4a shows the family of I0 versus Vos curves
for an NMOS inverting transistor and IL = Ill versus
Vos = VDD - VL curve for a linear load device.
Graphically determine the VTC. Use VDD = 10 V and
a load resistance RL = 1 kn. Use k. 0 = 2 mA/V 2 and
V 1 = 1 V for the NMOS.
Solution Reading (Vc;s, VDs) ordered pairs directly
from the graph and plotting them on the VDs versus
Vcs coordinate axes of Figure 17.4b, the VTC is obtained. This is expedited by constructing the following table:
Yes
10
= (Yes -
1
0
2
3
4
5
1
4
9
16
1)2
YDs
10
9
6
2
1
238
Chapter 17/Introduction to MOS Digital Circuits
.
Your (V)
resistor load line
A
4-
C
3-
,
C
Vm=3V
------..:,;;.~B_,,,_Vm=2V
I
~ A Vmi;l V
3
4
VOL"' 1--------
D
-------i--------------~!~~E
'
'
'
0 ~--+-------,/1-1---~-+-------1-__. V mCV)
5
0
Vr=l
2
VIL
Your= Vos= Yoo- VRL (V)
(a)
3
Vrn=4
5
(b)
FIGURE 17.3 Graphical Determination of an NMOS
Inverter's Voltage Transfer Characteristic: (a) NMOS ID
versus VDs current-voltage family of curves with
superimposed resistor load line, (b) NMOS inverter
voltage transfer characteristic from curve intersections
in (a)
V our = V os(V)
16
.-..,----------V s = 5 V
0
14
10
i
i
s!
12
10
6
t
8
4
4
2
2
r----------~~_,,.-Vas = 2 V
;,-,....;--,......,.~,---1---,..--,.-1--...--~A~. V~ 1 V
2
4
6
8
10
Your= Vos= Yoo - VRL (V)
(a)
FIGURE 17.4 Graphical Solution of Example 17.2
NMOS Inverter Voltage Transfer Characteristic:
(a) NMOS ID versus VDs current-voltage family of curves
-1 :
0
t-+t;·-+
VIL
j..._'----1-----1~'---+-------+~
-
+io► V m(V)
VIll
(b)
with superimposed resistor load line, (b) Voltage transfer
characteristic from intersections in (a)
17.4
17.4
PARTIAL DIFFERENTIALS
Partial Differentials
239
and
ar(x,y)
ay
a
"
(4r + 2x + 3y)
ay
_'J _ _ = -
=
3
Analytical analyses of the operation of NMOS inverters involves solving equations with partial differentials of drain currents in the linear or saturation
mode of operation. This section presents fundamentals of partial differentials. Before proceeding with a
description of partial differentials, it is necessary to
briefly review ordinary differentials.
The partial differential df(x,y) of f(x, y) is then found
by substituting these partial differentials into the expression
Ordinary Differentials
yielding
df(x,y) = af~y) dx + aJ~y) dy
If a function f is a function of a single variable x
df(x,y) = (8x + 2)dx + 3dy
f = f(x)
then small change df inf are equal to small changes
dx in x multiplied by the derivative off. That is
)
d'f(
;X,y
df(x,y)
=~X
d
X
As mentioned at the beginning of this section, analyses of the operation of various NMOS inverter will
involve partial differential of NMOS drain currents.
The following example demonstrates taking partial
differentials of NMOS drain current expressions.
Partial Differentials
If a function f is a function of multiple variables, say
y
x and
f = f(x,y)
then small changes df inf are equal to the sum of
small changes in x and y each multiplied by the partial derivative off with respect to x and y, respectively. That is
af(x,y) d
aJ(x,y) d
df(x,y ) = - - x + - - y
ax
;;y
Example 17 .4 Partial Differential of an
NMOS Drain Current Expression
Find an expression for the partial differential of the
drain current expression for an N-channel MOSFET
in the linear mode of operation.
Solution The linear mode drain current expression
is a function of Vcs and Vos:
In(LIN) = k [ Wes - VTWos - -Vf)s]
2
The following example gives an example of partial differentials.
= IoWcs, Vos)
The partial derivatives of this expression with respect
to V cs and VDs are
Partial Derivatives
Example 17.3
aio(Vcs, Vos) _ kV
avcs
Determine the expression for the partial differential
of the function
Solution To determine the expression for the partial differential df(x,y), it is first necessary to find the
partial derivatives of f(x,y) as follows:
ar(x,y)
ax
a
(4r + 2x + 3y)
ax
?
=
os
and
f(x,y) = 4x 2 + 2x + 3y
_'J _ _ = -
-
8x
+2
aJDWcs, VDs) = k[Wcs
aVos
'
VT) - Vos]
= kWcs - VT - VDs)
The partial differential dI 0 (Vcs, V0 5 ) of I0 (Vcs, V0 s)
takes the form
240
Chapter 17/Introduction to MOS Digital Circuits
= alo(VGS, Vi)s) dV
dl L) (Vcs, V us)
c,
aVc;s
'·
Blo(Vcs, Vos) d VDs
+ __c::....:._-=..::.c_=:..
aVDs
Substituting the partial differentials found above
yields
d]D(Vcs, VDs) = kVos dVcs
MOS Transient Power Dissipation
A significant additional power dissipation also occurs
for MOS families driving switching from one logic
state to another. This switching dissipation is negligible for BJT logic families, in comparison with BJT
static power dissipation. An expression for the MOS
power dissipation during transient switching, called
the dynamic power dissipation, is given by
+ k(Vcs - VT - VDs) dVos
This expression for the partial differential of the linear mode drain current expression will be used in
Chapters 19, 20, and 21 in analyzing the operation
of the various transistor loaded NMOS inverters.
17.5 ANALYTICAL SOLUTION
OF THE NMOS INVERTER
Analytical solutions for NMOS inverters with a general load are presented in detail in the MOSFET logic
family chapters that follow this chapter. It is essential
that the proper expression (for linear or saturation
operation) for the drain current be used in each region of operation of the NMOS inverter. The previous section graphically demonstrates that the
N-channel MOSFET in the inverter circuit operates
in all three modes, namely, the cutoff, saturation, and
linear modes of operation.
17.6
POWER DISSIPATION
MOS logic families have the lowest power dissipation per gate of any of the logic families. This is because of the large values of MOSFET resistance and
consequently small current levels. In particular,
CMOS has the lowest power dissipation per gate, as
we shall see. The following description is given for
introductory purposes.
MOS Static Power Dissipation
An NMOS or CMOS gate dissipates power in the
same manner as the BJT gates. That is, the power
dissipated is given by the product of the power supply voltage and average current for a NMOS inverter
p
_ V
DD -
DD
IDD(OH) + Io 0 (0L)
2
Pn = CLvviD
vvhere CL is the total load capacitance at the output
of the gate and vis the frequency at which the gate
is switched.
The low power dissipation per gate of MOS families is demonstrated in the following example.
Example 17 .5 NMOS Power Dissipation
Consider an NMOS inverter with VDD = 5 V, v =
0.5 MHz, CL = 10 pF, IDD(OH) = 5 µ,A, and IDD(OL)
= 100 µA Calculate the power dissipated due to
switching and that due to the average current for the
output high and low states.
Solution The power dissipation due to switching
is calculated by direct substitution as follows:
P,11/1 1 = (10 X 10- 12)(0.5 X 10 6)(5) 2 = 125 µ,W
The average power dissipation for the high and low
output states is obtained by direct substitution as
p
_
nn -
5
(5 X 10- 6 ) + (100 X 10- 6 )
= 262 µ,W
2
Note that the total average power dissipation is
P1,,1,,1(avg) = 125µ,
+
262µ, = 387 µ,W
which is more than an order of magnitude less than
the average power dissipation for a bipolar logic gate.
17.7
MOS FAN-OUT
Since the gate terminal is always an input terminal
and the gate sinks zero current for all input voltages,
fan-out for MOS families is unlimited. This is true
for all load devices including a P-channel MOSFET,
as is the case for the CMOS inverter. Thus, the fanout based upon current limitations is infinite for all
17.7
MOS Fan-Out
241
Charging of Load Capacitance
in Output High State
When the input is switched high-to-low, the output
capacitance is charged from VoL to VoH through the
load device. Assuming that the input is driven by a
similar gate and VOL of that gate is less than the
threshold voltage Vr, the NMOS device is cutoff and
100% of the current through the load device is used
to charge the output capacitance CL as shown in Figure 17.6a.
Discharging of Load Capacitance
in Output Low State
output load modelled
as a capacitance
FIGURE 17.5 General NMOS Inverter Shown Driving
a Load Capacitance
When the input is switched low-to-high, as shown
in Figure 17.66, the output capacitance is discharged
from VoH to V 0 L through the NMOS device. Note
that in this situation there may still be a current in
the load device. Thus, the output capacitance discharging currenty is equal to the difference of the
NMOS drain current and the load current given by
NMOS and CMOS gates. The maximum fan-out is
restricted, however, by the maximum propagation
delays tolerable.
IcL
= Io - 11.
Output Response Time
NMOS Inverter Driving
a Load Capacitance
Figure 17.5 shows the general NMOS inverter of Figure 17.1 driving a load capacitance.
The time required for the output to switch low-tohigh and high-to-low is directly proportional to the
output capacitance and inversely proportional to the
output charging and discharging currents provided
L
~
iIL<I0
-1-L
-1
I
--
-.
Your
--0 -
v~ J
V.._
';_ ··-I
tlo
1_ . Yf NO
r-1
I
~ la,=1
C..
load capacitance charging
load capacitance discharging
Ia. =IL =-c.. <i~F
Ia. = ID - IL = -c.. d~tl!I
(a)
FIGURE 17 .6
capacitance from
General NMOS Inverter: (a) Charging a load capacitance from
Vrn1 from VoL
0
"--.__ v"'
(b)
VoL
-IL
to Vrn 1, (b) Discharging a load
V._
242
Chapter 17/Introduction to MOS Digital Circuits
by the MOSFET inverter. The output capacitance is
generally the input capacitance of succeeding gates
and is dependent upon the type of gate being driven.
The charging and discharging currents are dependent upon the type of gate driving the load capacitance.
The following example demonstrates the determination of the maximum load capacitance that can
be driven and still meet a specified response time.
Finally, solving this expression for C gives
Thus, the maximum capacitance that can be charged
from V0 1. to VoH in 1 µ,s with a charging current of
IcRc = 50 µA is
.
CviAx(clwrgmg)
Example 17.6
1\,10S Fan-Out
What is the maximum load capacitance that can be
driven by an NMOS inverter that provides an output
charging current of Irnc = 50 µ,A and discharging
current of IDrs = -20 µA with a maximum switching
time of 1 µ,s. Assume VOL = 0.5 V and VoH = 5 V.
(For this example, assume that the charging and discharging currents are constant during transition of
the output state.)
Solution The current-voltage relationship of a capacitor is
le= C dVc
dt
(1µ,)
.5) (50µ) = 11.1 pF
4
= (
The n1axirrlurr1 capacitance that can be discharged
from VoH to Vm in 1 µs with a discharging current
of -20 µ,A is
.
.
CA1Ax(d1schargmg)
(1µ)
= -(-4.5
--)
(-20µ) = 4.44 pF
These calculations indicate that the maximum output
capacitance that can be driven by the specified gate
with a maximum switching time of 1 µs is limited by
the high-to-low transition (as expected since the discharging current is less than the charging current).
Thus, the maximum capacitance that can be driven
by this gate and maintain a 1 µ,s switching time is
C,\1Ax = CMAx(disclwrging)
Solving for dt gives
= 4.44 pF
C
dt = - dVc
le
The time M = t 2 - t1 required to charge a capacitor
from a voltage V1 to V2 is found by integrating the
above expression as follows:
ll.t = t 2
t1 =
-
l
t,
f1
dt = C
JV,
1
-I dV
V1
C
Assuming that the current is constant, that is, not a
function of the capacitor voltage V0 this can be simplified to
t:,.t
C
= -
fv
2
C
C
dV = - (V? - Vi) = le v,
le le
~V
The previous example demonstrated that the
fan-out of a MOSFET logic gate is determined as the
maximum load capacitance that can be driven and
still maintain an acceptable switching time.
This is an extremely simplified example since the
charging and discharging currents were assumed to
be constant during the output transition. In actual
MOSFET logic gates, the current magnitudes vary
during the output transitions. Chapters 18 and 23
derive the expressions for the transition times of two
different MOSFET logic families, and as will be seen,
these derivations are quite lengthy.
CHAPTER17PROBLEMS
17.1
Sketch the source-drain current-voltage characteristics for a MOSFET with saturation drain current
given in mA as follows:
I 0 (SAT)
=
s(1+ V;sr
17.2
Repeat Problem 17.1 for
In(SAT) =
17.3
s(-1 + V;sr
Repeat Problem 17.1 for
In(SAT) = 5(Vcs - 1) 2
Chapter 17
17.4
Sketch the current-voltage (1 1, versus VIJ,;) characteristics for a lv!OSFET with the linear region current expression given in mA as follows:
17.9
Problems
243
Consider the lv!OSFET of Problem 17.3 to be used
in the inverter circuit of Figure Pl 7.7. Graphically
determine the VTC for the inverter circuit for Vr s
V1N S Vim•
17.10
17.5
Repeat Problem 17.4 for
Consider the MOSFET of Problem 17.4 to be used
in the inverter circuit of Figure P17.7. Graphically
determine the VTC for the inverter circuit for Vr s
VIN s VJ)!)•
17.6
Consider the MOSFET of Problem 17.5 to be used
in the inverter circuit of Figure Pl 7. 7. Graphically
determine the VTC for the inverter circuit for V 1 s
7.12
Consider the MOSFET of Problem 17.6 to be used
in the inverter circuit of Figure Pl 7. 7. Graphically
determine the VTC for the inverter circuit for VT s
Repeat Problem 17.4 for
lv(LIN) = 2.5
17.7
17.11
V1N s vi)!)•
[Wes -
l)Vns -
Vbs]
2
Consider the MOSFET of Problem 17.1 to be used
in the inverter circuit of Figure Pl 7. 7. Graphically
determine the VTC for the inverter circuit for Vr s
VIN s Vr,l),
17.13
Calculate the average static power dissipation for a
MOSFET inverter with V1m = 5 V, I1m(OH) = 0,
and ID 0 (0L) = 0.3 mA.
17.14
Calculate the average static power dissipation for
the MOSFET inverter of Problem 17. 7.
17.15
Calculate the average static power dissipation for
the MOSFET inverter of Problem 17.8.
17.16
Calculate the average static power dissipation for
the MOSFET inverter of Problem 17.9.
17.17
Calculate the average static power dissipation for
the MOSFET inverter of Problem 17.10.
17.18
Calculate the average static power dissipation for
the MOSFET inverter of Problem 17.11.
17.19
Calculate the average static power dissipation for
the MOSFET inverter of Problem 17.12.
17.20
Calculate the transient power dissipation for a
MOS inverter with 12 gates connected to the output. Let v = 10 MHz, V1m = 5 V and each MOSFET
has a parasitic gate-to-source capacitance of 1 pF.
VIN s VDD·
17.8
Consider the MOSFET of Problem 17.2 to be used
in the inverter circuit of Figure Pl 7. 7. Graphically
determine the VTC for the inverter circuit for Vr s
VIN s VD!)·
V00 = 5V
soon
0 YNor
FIGURE P17.7
+
18
RESISTOR
LOADEDNMOS
INVERTER
In the next several chapters, inverter characteristics
are described in detail for various MOSFET cases
with different loads. The details are quite cumbersome, but once understood lead to the reasoning involved in MOSFET device design. This chapter provides a description of the resistor loaded NMOS
inverter which is the simplest type of MOS inverter,
but not at all practical. This example promotes an
excellent understanding of the concepts involved in
MOS logic families.
The operation of the resistor loaded NMOS inverter is qualitatively described, listing the mode of
operation for the output N-channel MOSFET during
switching of the output state. A graphical analysis of
the voltage transfer characteristic is then presented
followed by an analytical analysis of the VTC critical
voltages. A discussion of power dissipation for this
type of inverter is presented followed by an analysis
of the dynamic response of the inverter. The chapter
concludes with a SPICE simulation to corroborate
the results found in the analytical analyses.
point, only a small current flows and the drain voltage is slightly less than V00 . As long as VDs 2:
Vc;s - VT, N 0 is operating in the saturation region.
With further increase of the input, a larger drain current conducts and the output voltage continues to
fall. The analytical form of the VTC can be found by
equating the drain current with the resistor current
to obtain
18.1 OPERATION OF RESISTOR
LOADED NMOS INVERTER
As V1:,..: is further increased, I0 increases and the
voltage drop across RL can become sufficient to reduce the drain voltage such that VDs :S Vcs - VT.
Under this condition N 0 operates in the linear region. The VTC of the resistor loaded NMOS inverter
has the form shown in Figure 18.2b and will be explained in detail in the next section.
In summary, for a low input the output is high.
Conversely, for a high input the output is low. The
logical NOT function is therefore realized. The next
two sections present the graphical and analytical
procedures for determining the voltage transfer characteristic of this inverter.
or
Substituting Vcs
= V,:--.: and VDs = VoL'T yields
Solving for VoL'T, we have
Figure 18.1 shows the NMOS inverter with resistive
load, RL. The input to the inverter is at the gate of
the N-channel output transistor N 0 and V,N = Vcs•
The output is at the drain and VouT = VDs = VoD IRLRL. For V,N < VT, N 0 is cutoff and does not conduct drain current. Since the resistor current is equal
to the drain current, with VrN < VT IRL = ID(OFF) =
0 and the output is Your = vl)D•
As the input is increased slightly above the
threshold voltage, N 0 begins to conduct. At this
244
18.2
Graphical Determination of VTC for Resistor Loaded NMOS Inverter
245
Tips, Tricks, and Gimmicks
N-Cha.nnel MOSFETs
The equations and parameters governing the operation of N-channel MOSFETs introduced in the
introductory chapter 16 are also required in this
chapter and are listed again as follows:
I-·-
l 0 (0FF)
=
_
+
st
0
FIGURE 18.1
2:
Yam:= VNITT
:~,rNo
Vos
Cutoff== Yes s Vr
• Saturation == Vcs
~W
I
VIN
Regions of Operation
-0
Vr and Vos
2:
Vcs - VT
Resistor Loaded NMOS Inverter
18.2 GRAPHICAL DETERMINATION
OF VTC FOR RESISTOR LOADED
NMOS INVERTER
The resistor current is equal to the NMOS drain current and can be expressed as a function of V05 as
follows:
or
Voo - Vos
I1n = - - - - =
R1.
MOSFET Parameters
• Device transconductance parameter ==
• Process transconductance parameter ==
k'
= /LNCox
• Electron mobility == µ, = 580 cm 2N · s
Channel-Length Modulation Parameter 11
A[V- 1 ]
• Gate Capacitance per Unit Area
• Permittivity of SiO 2 ==
cm
Eax
= 3.45
• Thickness of gate oxide == tax
Threshold Voltage
• Enhancement-only == VT > 0
• Enhancement-depletion == VT < 0
X 10- 13 Fl
lo
This is a linear relation relating I0 to VDs for a constant R1,. This suggests that the voltage transfer characteristic can be obtained graphically by superimposing the output load (resistor) line over the NMOS
10 versus V 0 5 family of characteristics (with V Gs as a
parameter), as shown in Figure 18.2a where VoD =
5 V. Ordered pairs of points (Vcs, V Ds) are read from
the intersection of the output load line with the family of curves. These are in turn plotted on V 05 versus
V cs coordinate axes as shown in Figure 18.2b. The
voltage transfer characteristic is the resulting curve
through these plotted points.
Note that the output voltage never reaches zero.
To explain this, consider Figure 18.3 which displays
an inverter driving another inverter. The highest output of the driving gate is V ouT,o(MAX) = VoH = VDo,
as already determined. Therefore, the highest input
of the load gate is V1N,L(MAX) = Vc)H = VDD· This
corresponds to VGs = V,)D = 5 V and the top currentvoltage of Figure 18.2a. The input at the intersection
of this specific ID versus VDs curve with the resistor
load line is VDs = Vm. > 0.
This qualitative analysis gives insight into the
246
Chapter 18/Resistor Loaded Nlv!OS Inverter
0/)
VOIIT
resistor load line
A
5-----Hi,......
4---
C
D
VOL"'
1~-------!------)--------------~!~E
:
I --lt---------,------1--+--------> Vm(V)
0
0
Vr=l
Your= Vos= Yoo - VRL 0/)
l2
(a)
Yrn=4
5
(b)
FIGURE 18.2 Graphical Determination of Resistor
Loaded Nlv!OS Inverter Voltage Transfer Characteristic:
(a) Enhancement-only NMOS ID versus VDs current-
driving gate
FIGURE 18.3
3
Vrr.
voltage family of curves with superimposed resistor load
line, (b) Voltage transfer characteristic from curve
intersections of (a)
load gate
Cascaded Resistor Loaded NMOS Inverters for V01 _ Illustration
operation of N 0 for the resistor loaded NMOS inverter. For instance, in the output high state, N 0
turns on in the saturation region of operation. For
the output low state, N 0 is in the linear region. The
state of N 0 can be determined for the other critical
points as well. Table 18.1 lists the state of N 0 for each
of the critical points. Recall that VM is the midpoint
voltage at which V,:---i = Vo1-:T = VM.
TABLE 18.1 States of N 0 for the Resistor
Loaded NMOS Inverter
Critical Point
State of N 0
Vo,1
V11_
Cutoff
Saturation
Linear
Linear
Saturation
v,r1
Vo1.
VM
18.3
C:ilculation of VTC Critical Points for Resistor Loaded NMOS Inverter
Graphirnl analyses for other types of loads are
developed in the next several chapters. Explicit values for the critical points of the VTC are calculated
in the following section.
This quadratic relation has a positive and negative
solution of which only the positive is valid. Usually
Vm is sufficiently small and the squared term V~)I. is
negligible. The quadratic expression reduces then to
V
18.3 CALCULATION OF VTC
CRITICAL POINTS FOR RESISTOR
LOADED NMOS INVERTER
24 7
OL -
Vnn
kRLWon - Vr) + 1
Substituting V0 D, k, Ri., and Vr into this expression
and verifying
Output High Voltage = Vott
V011 is found by noting that N 0 is cutoff for V1N =
Vcs < VT. With N 0 off, IRL = ID = 0 and since the
output is VoL'T = VDD - IDRL, we have
Vrn, = Voo
Output Low Voltage=
VoL
In the output low state, N 0 is in the linear region of
operation. Assuming this inverter is driven by a similar gate in the output high state, as in Figure 18.3,
vii': = VoH = VDD· Substituting this and vl)S = VOL
into the linear drain current expression gives
In(LIN) = k
[Wes -
VrWDs -
Vbs]
2
= k[Wno - VrWm - v;)L]
or
Vm
S:
Wno - Vr)
confirms the operation to be in the linear region.
We now consider the magnitude of the RL term
in the denominator of the expression for VoL• Since
k is typically in the range 10 µ,AN 2 to 100 µ,A/V 2, RL
must be at least 10 kD to 100 kD to obtain a low
value for VOL. Consequently, the primary design flaw
for the resistor loaded NMOS inverter is the required
large value of Rt., Integrated circuit resistors of this
magnitude require relatively enormous silicon areas.
Input Low Voltage= V1L
For MOS logic families the input low voltage is defined as the point on the VTC slightly below VoL'T =
Vrn- 1 (see Figure 18.2b) where the slope is -1 or
dVour
dVIN
Making the same substitutions into the resistor current expression yields
--=
-1
At the input low voltage, N 0 is in saturation. Substituting Vcs = V1L into the saturation drain current
expression gives
By equating the NMOS drain and resistor currents
V0 L is found as follows:
10 (LIN)
=
IRL
Substituting VDs = Vrnm the resistor current is obtained as
or
Rearranging yields
k(V
- V )V
1)0
or
T
OL
wi,. 2
-
vl)D - V 01,
Rt
RL
With Io = ID(V1N) and IRL = IRL(VouT), equating
differentials of the drain and resistor currents gives
dloW1L)
= dI1vJV0U'/J
or
dl 0
dVn
dvlL
dI,n
= -dV dVour
OUT
248
Chapter 18/Resistor Loaded NMOS Inverter
Solving for dV 0urldV1N = dVm.7 /dV 1L and equating
to -1, yields
or
olo
aID
d[RL
- - dV,n + - - dVouT = - - dVouT
r7Vu,
oVmrr
dVouT
dl 0
dV0 u7
dV,L
_
dVouT
=--=--=
1
dV1N
dVouT
Solving for dV oL7 -/dVrN
to -1, yields
ol0
and rearranging, we have
dl 0
dVIL
dVouT
dVI,\'
dIRL
dVouT
Substituting the derivatives yields
v,L
=
dln
a10
dVouT
dVou,
-1
-----
ol 0
IIVu,
Substituting the derivatives yields
1
vT + kRL
Note that the input low voltage is slightly above the
threshold voltage and independent of VDD·
avu,
dVouT
dV,/-1
Rearranging yields
1
k(V,L - VT)= RL
Finally, solving for V1L yields
= dV 0 urldV 11-1 and equating
1
kVouT = - + k[(V,11 - VT) - VouT)]
RL
The 1/RL term is negligible compared to the other
terms, thus reducing the expression to
VouT = V,n - VT - Vour
Input High Voltage
= Vm
For MOS logic families, the input high voltage is defined as the point on the VTC before Vm (see Figure
18.2b) where
dVouT = _ 1
dV/N
At the input high voltage, N 0 is in the linear region
of operation. Substituting Vcs = V 1H and VDs = VouT
into the linear drain current expression yields
Solving for VolJl· gives
VouT(IH) = Vu1 ; VT
This is the output voltage corresponding to the input
high voltage. To solve for V1H, we equate the resistor
and drain currents and substitute the expression for
Vmn0H) as follows:
l 0 (LIN) = k [ Wes - VT)Vos - Vi'is]
2
viuT]
= k [ (VIH - VT)VOUT - -2-
= Voo _ VIH - VT
R1,
The resistor current is still given by
2RL
Rearranging gives a quadratic in (Vu-, - VT)
3
With 10 = ID(VJN, Your) and IRL = IRL(Vour),
equating differentials of the drain and resistor currents yields
dlo(Vu,, VouT) = dIRL (VouT)
k
8
?
W,11 - VT)- +
1
Voo
RL W,n - VT) - RL
2
=0
Solving for (Vn-1 - VT) in turn gives a solution for VrH
and the corresponding VocT(IH).
The linear region of operation is verified by testing if
18.3
Calculation of VTC Critical Points For Resistor Loaded NMOS Inverter
249
Solution The transconductance parameter for the
transistor must first be calculated
or
W = (20µ,) (10µ,)
A
k = k , -L
= 40µ, -:;
5µ,
v-
VourUH) s Vu 1 - VT
After calculations, this verification is possible and the
original assumption is validated.
Midpoint Voltage= VM
V011
At the midpoint voltage, where V1N = Your = Vtvt,
N 0 is in the saturation region of operation since
which after substituting Vcs
= VDs = Vtvt reduces to
VM:::::VM-VT
which is clearly satisfied. Substituting Vcs = VM, the
saturated drain current is given by
ID(SAT) =
k
2 (Vcs
VoH, V1u and Vm are obtained by substituting directly into their derived expressions.
?
- V.1)- =
k
Vu.
=5
V
1
=
(40µ,)(50k)
+ (1) = 1.5 V
(5)
(40µ,)(50k)[(5) - (1)] + 1
= 0.556 V
The linear operation of N 0 for the output low state
is verified by
0.556 s 5 - 1 = 4
?
(V,11 - Vr)-
2
Substituting VDs = V;vi, the resistor current is given
by
The coefficients for the quadratic in V1H
Au 1 = 3
k
-
Vr are
3(40µ.)
= 15µ.
8
8= -
1
1
Bui = 2RL = 2(50k) = lOµ,
By equating the drain and resistor currents, Vtvt is
obtained as follows:
Voo
(5)
C111 = - = - - - = -100µ,
RL
(50k)
Utilizing the quadratic formula
or
~ (V
2
M
_ V )2 _ V DD - V,11
T
RL
-(10µ,) :±:
2
M
+
(2. - )v
R1.
kV
T
M
+ (~ V2
2
T
-
-
4(15µ,)(-100µ,)
2(15µ,)
Expanding and rearranging terms gives
~2 V
V (10µ.) 2
= 2.27 or -2.94 V
Vno) = O
R1
which is a quadratic relation for Vtv1,
The positive 2.27 V is the correct solution. Vn 1 1s
therefore
V111 = VT + 2.27 = (1) + 2.27 = 3.27 V
The corresponding output is
Example 18.1 Resistor Loaded NMOS
Inverter VTC
Calculate the critical points for the voltage transfer
characteristic of a resistor loaded NMOS inverter.
Use V00 = 5 V, k' = 20 µ,AN 2, W/L = 10 µ,m/5 µ,m,
VT= 1 V, and RL = 50 kn.
VourUH) =
(3.27) - (1)
2
= 1.14 V
The linear operation of N 0 is verified by the following inequality:
1.14 s 3.27 - 1 = 2.27
250
Chapter 18/Resistor Loaded NMOS Inverter
The coefficients of the midpoint voltage quadratic are
AA,J
=
k
(40µ)
For the output low state, N 0 is in the linear region
of operation. The terminal voltages of N 0 for this
state, as found in the previous section, are
2 = -2- = 20µ
1
1
BM = Ri. - kVT = (50k) - (40µ)(1) = -20µ
C
=~
1v1
2
v2.1 -
Voo
RL
= (40µ) (1)2 - ___@_ = -80
2
(50k)
Output Low Current = Iu 0 (OL)
µ
and
V
Utilizing the quadratic formula
-V
LJS -
- B,1,1 :±: V Br1 - 4AMCv1
V,v1 = - - - - - - - - -
2Ai11
~-~~------(-20µ) ± V(-20µ)2 - 4(20µ)(-80µ)
2(20µ)
-
OL -
Vi)D
kRr.(V00
-
VT) + 1
The current supplied for the output low state can be
found by substituting these voltages into the resistor
current expression or the linear drain current expression yielding
= 2.56 or -1.56 V
Hence, VM is the positive value, 2.56 V.
The analysis of the resistor loaded NMOS inverter provides valuable information about general
digital MOSFET operation, since this case offers an
NMOS inverter with a relatively simple analysis.
However, its usage is son,ewhat impractical since the
physical size of integrated circuit resistors is hundreds of times larger than transistors. This is overcome by using NMOS transistors as loads. The next
several chapters discuss various transistor loaded
NMOS inverters.
Static Power Dissipation= P00 (avg)
The static power dissipated for an inverter is obtained from
PnD (avg)
=
loo(OH) + Ion(OL)
2
V00
Iw(OL)VrnJ
2
Dynamic Power Dissipated= Puu(dyn)
As mentioned in the introductory MOS chapter, a
significant additional power dissipation for MOS
logic circuits occurs during the switching of logic
states. This contribution takes the form
POWER DISSIPATION
OF RESISTOR LOADED
NMOS INVERTER
18.4
To determine the power dissipation of a resistor
loaded NMOS inverter, the DC currents supplied by
VDlJ for the high and low output states must first be
obtained.
Pno(dyn) = CLvVbD
where CL is the total load capacitance at the output
of the gate and vis the frequency at which the gate
switches logic states.
Output High Current
Supplied = I00 (OH)
For an NMOS inverter in the output high state, N 0
is cutoff (see Table 18.1). With N 0 cutoff,
lw(OH)
= 11v_(OH) =
I 0 (OFF)
=0
Example 18.2 Power Dissipation of Resistor
Loaded NMOS
(a) Find the static power dissipated in the resistor
loaded NMOS inverter of Example 18.1.
18.4
(b) Find the dynamic power dissipated for the same
gate. Let Ci, = 1 pF and v = 1 MHz.
Solution (a) For the output low state, the terminal
voltages of N 0 were found in Example 18.1 to be
Vcs = ViN(OL) = 5 V
and
VoL
Tips, Tricks, and Gimmicks
Abridged Integral Table
The following integrals will be used in the analysis of the resistor loaded NMOS inverter transient response:
I ax :x bx Inc : bx)
= 0.556 V
2
1f
251
Power Dissipation of Resistor Loaded NMOS Inverter
=;
and
Tips, Tricks, and Gimmicks
I
Capacitor Current- Voltage
Characteristic
The resistor loaded NMOS inverter dynamic or
transient response presented in the following
section requires knowledge of the current-voltage characteristic of capacitors. Shown in Figure 18.4, we recall that the current-voltage
characteristic of a capacitor is
le
=
dVe
C
If the voltage Ve across the capacitor as labeled
is increasing, then dVeldt is positive and the
capacitor current le as labeled is positive, with
⇒ le> 0
Similarly, if the voltage Ve across the capacitor
as labeled is decreasing, then dV eldt is negative
and the capacitor current le as labeled is negative. Thus,
dVc
Ve decreasing - < 0
dt
= In u(x)
The current in the output low state is therefore
In
5 6
2
= (40µ,) [ (5 - 1)(0.556) - (0. : )
]
= 82.8 µA
The static power dissipated is therefore
dt
dVe
> 0
Ve increasing - dt
u'(x)
-(-) dx
ux
⇒ le< 0
(82.8µ,)
Prm(avg) = - (5) = 207 µ,W
2
Solution (b) The dynamic power dissipated is
P00 (dyn) = (1p)(1M)(5)2 = 25 µ,W
Note that the static power dissipated in a resistor
loaded NMOS inverter is actually much greater than
the dynamic power dissipation.
The previous example calculated the power dissipation for a resistor loaded NMOS inverter toggling at a frequency of 1 MHz. The dynamic response
1f
Tips, Tricks, and Gimmicks
Difference Property of Logarithms
Vc decreasing
➔ ~ < 0 => le < 0
The following difference property of logarithms
will be used in the analysis of the resistorloaded NMOS inverter transient response:
(reversed)
In a - In b = In
FIGURE 18.4
Charging and Discharging of a Capacitor
ba
252
Chapter 18/Resistor Loaded NMOS Inverter
analysis for this inverter in the following section indicates that operating frequencies higher than this
are not possible for most applications.
approximate sum of the gate-source, gate-drain, and
gate-body capacitance as follows:
Cc
Input Capacitance of a Resistor Loaded
NMOS Inverter
r,
••
-11'
r"7
10. 1
1 __
'1
,1
·, •
'
,.
_
Ccs
+
Ceo
+
CcB
=
C1N
This total gate capacitance is the input capacitance
between the gate and ground of a resistor loaded
NMOS inverter. When the input logic state to a resistor loaded NMOS inverter is switched low-tohigh or high-to-low, this input (gate) capacitance
must be charged or discharged, depending upon the
direction of the input change.
18.5 RESISTOR LOADED NMOS
INVERTER DYNAMIC RESPONSE
.::iecuon
=
•
uescr 1Des rne pdrnsmc 1u11cno11 cdpdu-
Load Capacitance on a Resistor Loaded
NMOS Inverter
tances that exist in a MOSFET. Figure 16.7 shows
that a capacitance is present between every pair of
terminals for a MOSFET. The gate capacitance is the
dominant capacitance and can be evaluated as the
Examining Figure 18.5a, when one resistor loaded
NMOS inverter drives other resistor loaded NMOS
V'DD
~--() V'mm
V'DD
driving inverter
[
all load inverters
contribute to the
capacitive load on
the driving inverter
.
L- - - - - - - - ·
►
,
C0
I- - J V'mm
I
1 l~-
~-~-------~\y,LJtx7 l=- jf N'm
load inverters
(a)
FIGURE 18.5 Resistor Loaded NMOS Inverter Driving
a Load Capacitance: (a) Each load inverter contributes an
effective capacitance (shown extracted) to the output of
the driving inverter
18.5
253
Resistor Loc1dcd NMOS Inverter Dvnamic Response
rent through the load resistor is negligible (valid for
R1 large). Solving for the tin1e differential considering the NMOS drain current a function of the output
voltage yields
The time period M required for a given change in
output voltage during the output high-to-low transition is obtained by integrating both sides of this
expression to obtain
output load modelled
as a capacitance
1,(11"" 1
M=t2-t1=
f
~v,> dt=-C f,v,
i,(V()[rr~V,)
(b)
FIGURE 18.5 (continued) (b) Resistor loc1ded NMOS
inverter driving a load capacitance
inverters, the input capacitance of each load inverter
must be charged or discharged simultaneously. This
situation is equivalently modeled as a single load capacitance at the output of a resistor loaded NMOS
inverter as shown in Figure 18.56. The dynamic response of a resistor loaded NMOS inverter is determined considering this capacitive load in the following sub-sections.
1
dV
our
v, Io(Vour)
Examining Figure 18.6a, it is noted that the NMOS
device changes from the saturation to linear mode of
operation during the high-to-low transition at V0 cr
= YDD - Y1 , while V1N = YDo during this entire
transition. Hence, the above integral necessitates
separate integrals for each region of operation as follows:
The NMOS drain currents for the two active modes
of operation are obtained by substutiting Yes = Y1N
= Y0 1-1 = Vrm and YDs = Ym;r yielding
Output High-to-Low Transition
The transient characteristics of interest during the
output high-to-low transition are the fall time t1 and
the high-to-low propagation time tp 1IL· Figure 18.6a
shows the step-up input voltage stimulus and the
resulting resistor loaded NMOS inverter output response with tr and tp 1IL labeled. Prior to the input
voltage change (V 1:--; low), the inverter is in the output
high state with N 0 cutoff. Upon switching of the input, Yes = YuD bringing N 0 into active operation.
Figure 18.66 displays this situation with a load
capacitance discharging through an active N-channcl MOSFET. KCL at the inverter output node results in
and
Substituting these NMOS drain current expressions
into the integrands in ~t gives
M = M(SA T) + M(LIN)
VDn-v-,
dV
-C
_ _ _O_U_T_ _
I
J~
k
2
where the negative sign is necessary, since dYm;1 /dt
is negative. Also, it has been assumed that the cur-
,
(Vnv - Vr)~
254
Chapter 18/Resistor Loaded NMOS Inverter
Vn/,..V)
t
VOH = VDD
l/1,rMOS
VoH=Voo
enters saturation mode
----------NMOS cutoff
NMOS enters linear mode
(a)
load capacitance discharging
I0 --
-c~Ymrr
dt
(b)
FIGURE 18.6 Resistor Loaded NMOS Inverter Output
High-to-low Transition: (a) Step-up input and output
response curves, (b) Load capacitance discharges through
active NMOS (load resistance is assumed very large)
18.5
The first of the integral terms is easily integrated as
follows:
v,,,,--v, dV
OUT
M(SAT) = -C 1
v,
-k- (Vi)/) - VT)-"
J,
Resistor Loaded NMOS Inverter Dvnamic Response
Summing the flt terms gives an expression for the
time period required for a voltage change during the
output high-to-low transition as follows:
M
M(SAT)
2CL
kW on - Vr)
2
J,\l"",
1,
\I'
dVmrr
+ k(Vn:~
VnpVr
2C1,VnuT
kWno - Vrf v1
I
Substituting the limits of integration gives
-2C1.(VDD - Vr - V,)
M(SAT) = - - - - - - k(Vov - Vr)2
The second integral term is obtained by utilizing the
first indefinite integral given in the Tips, Tricks, and
Gimmicks box preceding this section as follows:
M(UN)
dVouT
Vr)VouT - -Vznnj
2
C l.
k
J,v,
v,,,,-v,
+ M(UN)
-2CL(VLJD - v, - V,)
k(Von - Vr) 2
2
-
dVoL/1
255
v,)
2
lnCVno - ~ v,
- vJ
Rewriting to eliminate the negative sign m each
term, we have
M = 2C1 (Vr + V1 - ~/JD)
k(V[)l) - V1Y
+
CL
ln(2Vn 0
k(Vo/J - Vr)
-
2Vr - V2 )
V2
Note that fit in this expression is directly proportional to the load capacitance CL and inversely proportional to the NMOS transconductance parameter
k. Since k = k'(W/L), high-to-low transition times
of CMOS inverters are inversely proportional to the
channel width/length ratio.
Output Fall Time == t1
The output fall time t1 is defined as the time difference necessa1y for the output to fall from 90% to 10%
of the output high voltage. The voltages for 90% and
10% are obtained respectively as
V1 = Vm + 0.9(Vo11 - Vo,) = 0.9Vo11 + 0.1 Vo1.
= 0.9V00 + 0.1 Vo1.
and
Substituting the limits of integration yields
M(UN)
k(V0 v - Vy)
V2 = Vm + 0.l(V011 - Vm) = 0.1 Ve)// + 0.9VoL
= 0.1V00 + 0.9V0 1.
Substituting these values into the output high-tolow transition period expression yields
tr =
2CL(Vr + 0.9Vrm + 0.1VoL - Vnu)
k(VnD - Vy)2
CL
+----k(Vi)l) - V,)
ln(2VDD - 2V1 - 0.1 Vno - 0.9V01 )
0.1 Voo + 0.9VoL
Using the difference property of logarithms gives
2C,.(Vy + 0.1VoL - 0.lVoD)
kWoo - Vr)2
+
CL
k(VDD - V1)
ln(1.9Vvv - 2VT - 0.9Vm)
0.1Vv 0 + 0.9V0 1.
256
Chapter 18/Resistor Loaded NMOS Inverter
Note that this expression is directly proportional to
the load capacitance and inversely proportional to
the W/L ratio of the NMOS transistor. Substituting
k = k'(W/L) yields
_ J;__
[2(VT
t, - WIL
+ 0.1VOL -
0.1V00)
k'Won - Vrf
+
1
1
k Woo - VT)
ln(1.9V00 - 2VT - 0.9Vo1.)]
0.1 v/)/) + 0.9VoL
Output Propagation High-to-Low Delay
Time= tPHL
The output propagation high-to-low delay time tl'HL
is defined as the time difference between the input
at 50% of V 1N,MAX to the output at 50% of V011 VOL. Since a step input (instantaneous low-to-high
switching of the input) is used for this analysis, t 1,HL
is the time the output takes to drop from Vc)H to the
voltage halfway to VoL• Thus, substituting
Output Low-to-High Transition
The analysis of the output low-to-high transition involves the charging of the output load capacitance
through the load resistor RL of the inverter. The transient characteristics during the output switching lowto-high are the output rise time t, and the low-tohigh propagation delay tl'LH· Figure 18.7a shows a
step-down voltage input stimulus and the resulting
output for the resistor loaded NMOS inverter. The
output responses t, and tl'LH are as defined in the
figure. Prior to the input step-down, the output
NMOS device is in the linear mode of operation. After the input is switched, Vcs = 0 and the N-channel
MOSFET is cutoff.
This situation is displayed in Figure 18. 7b with a
load capacitance charging through the load resistor.
This is a simple RC charging circuit. Writing KCL at
the inverter output node yields
IR1
= Vo11 = Voo
Vi
and
V2 = VOL
=
+
= le
or
Vim - VouT _ C dVmrr
RL
- L dt
0.5(V011 - Vrn) = 0.SV011 - 0.SV01.
Solving for the time differential yields
0.5Vno - 0.5Vcn
into the output high-to-low transition period expression M yields
dt
= RLCL
dVouT
Voo
VouT
The period of time M required for a change in the
output voltage during the charging of the load capacitance is obtained by integrating both sides of this
differential expression to obtain
ln(2Voo - 2VT - 0.5V00 - O.SVOL)
0.5Vn 0 - 0.SVOL
This integration is again carried out by utilizing the
second indefinite integral given in the Tips, Tricks,
and Gimmicks box preceding this section yielding
k(Vw - Vr)2
+
C1.
kWoo - VT)
M = - RLCL ln(Voo - Vour)I~!
ln(l.SVDD - 2VT - O.SVOL)
0.5Vo 0
-
0.5VOL
Substituting the limits of integration yields
M = -Ri.Cdln(V00
As with tr, this expression is directly proportional to
the load capacitance and inversely proportional to
W/L.
-
V4 )
-
ln(Vuo - V3)]
18.5
Resistor Loaded NMOS Inverter Dynamic Response
25 7
VmCV)
+
VOH = VDD
I
L~~~~~
1. .
t(ns)
Vmrr(V)
VoH= Yoo
NMOS linear
~ . . NMOS~~t,,.·
.,rs·
.j
··~~~·
-~o,)
(a)
load capacitance charging
IRL --c<!Ymzr
dt
(b)
FIGURE 18.7 Resistor Loaded NMOS Inverter Output
Low-to-high Transition: (a) Step-down input and output
response curves, (b) Load capacitance charges through
resistor Rr.
258
Chapter 18/Resistor Loaded NMOS Inverter
Output Rise Time= tr
The output rise time is defined as the time it takes
for the output to rise from 10% to 90% of the tran sition region between VoL and VO H· Therefore, substituting these yields VJ and V4 as follows:
+ 0.1(VoH - VOL)= 0.1Vou + 0.9VaL
= 0.1 VDo + 0.9VOL
V3 = VaL
and
V4 = VoL + 0.9(Vo11 - VoL) = 0. 9VoH + 0.1VoL
Example 18.3 Dynamic Response of Resistor
Loaded NMOS Inverter
Determine t1, tp 1.1L, t" and t 1u 1 for the resistor loaded
NMOS inverter of Example 18.1 with a capacitive
load of CL = 1 pF.
Solution The dynamic response times are calcu lated by substituting directly into the expressions de rived in this section to obtain
t, =
2(1p)[(1) + 0.1(0.566) - 0.1(5)]
(40µ,)[(5) - (1)]2
= 0.9V00 + 0.1 VoL
+
Substituting these expressions into the M expression
for the output low- to-high transition period corre sponding to the rise time yi elds
_
~ - RLCL
_
-
RL
l [Voo - (0.1 Voo
n
.
Voo - (0.9Voo
+
+
In[ 1.9(5) - 2(1) - 0.9(0.566)]
0.1(5) + 0.9(0.566)
0.9V0 L)]
0.1 VoL)
CL l11 [0.9VDo - 0.9VoL]
0.1 Vvo - 0.1 V0L
(1p)
(40µ,)[(5) - (1)]
13.9
11S
2(1p) (1)
//'/IL
= (40µ,)[(5) - (1)]2
(lp)
+ (40µ,)[(5) - (1)]
Note that this expression is once again directly pro portional to the load capacitance CL.
ln[ 1.5(5) - 2(1) - 0.5(0.566)]
0.5(5) + 0.5(0.566)
Output Low-To-High Propagation
Delay= trLH
The output low-to - high propagation delay is defined
as the time difference between the 50% points of the
input voltage transition and the corresponding out put voltage transition. Since a step-down input stim ulus was assumed for the analyses of th e previous
sub -sections, the output low-to-high propagation
delay is obtained using
V3 = VoL
8.47
tr
115
= (50k)(l ) ln[ 0.9(5) - 0.9(0.566)]
p
0.1(5) - 0.1(0.566)
110 ns
tl'L 11
= (50k)(lp) ln(2) = 34 .7 115
These dynamic response times are typically much
longer than the response times that can be achieved
with the other NMOS logic families and CMOS
technology.
and
V4 = VOL + 0.5(V011 - VOL) = 0.5Vo11 + 0.5VoL
= 0.5V00 + 0.5Voi.
Substituting these into the M expression for the output low - to-high transition yields the low -to - high
propagation delay as follows:
tpw
= RLCL ln(
Voo - VoL
)
Voo - (0.5Voo + 0.5VoL)
= RLCL ln(2)
18.6 RESISTOR LOADED NMOS
SPICE SIMULATION
Figure 18.8 shows a resistor loaded NMOS inverter
with a capacitive load with appropriate SPICE label ings. The SPICE input CIRcuit file that represents
this circuit is as follows:
Resistor Loaded NMOS Inverter
VIN 1 D PULSE CDV SV OS 2NS 2NS
Resistor Loaded NMOS SPICE Simu!Jtion
18.6
---i
n+ 3
i
VDD - DC 5V
nj_o
FIGURE 18.8 Resistor Loaded NMOS Inverter with
Capacitive Load and Appropriate SPICE Labelings
259
+ 5DDNS 1US)
VDD 3 D DC 5V
-MODEL NMOSFET NMOS(VT0=1
+ KP=20U GAMMA=D-37 PHI=0-6
+ CBD=3.1E-15 CBS=3-1E-15)
MN◊ 2 1 DD NMOSFET W=10U L=SU
RL 3 2 50KOHM
CL 2 D 1PF
-DC VIND 5 0-1
-PLOT DC VDSCMNO)
-TRAN 2DNS 1-25US
-PLOT TRAN VCVIN) VDS(MNO)
-END
The VTC and transient response obtained from simulating this circuit are shown in Figure 18.9a and b.
5-i----4
Your (V)
/;.
3
2 -
5 - - -....
4-
------+--~....__..,...._-1-----+-- t(µs)
O··
1
0
3-+
0.25
0.50
0.75
1.00
1.25
Votrr(V)
2-
5
4
-
3
0 :_______ ~.----1,---+,--+----+--------- V IN(V)
0
1
2
3
4
5
2
+L
.- + --t- --
1 ~~~__,..___.!,J
0
0
(a)
FIGURE 18.9 Results of Section 18.6 Resistor Loaded
NMOS Inverter SPICE Simulation: (a) Voltage transfer
0.25
0.50
0.75
1.00
-- ► t(µs)
1.25
(b)
characteristic obtained from .DC sweep, (6) Transient
response obtained from .TRAN sweep
260
Chapter 18/Resistor Loaded NMOS Inverter
CHAPTER18PROBLEMS
18.1
For the resistor loaded NMOS inverter, what is the
state of N 0 for each of the VIC critical points Vrn 1,
VoL, V1L, Y111, and VM.
18.2
For the NMOS inverter with resistive load RL
shown in Figure P18.2, graphically determine the
critical voltages Vm 1, VoL, V11., V1H, and VM. Use V.r
= 1 V and k = 0.1 mA/V2 for N 0 . Sketch the VIC
and determine the noise margins.
18.4
Repeat Problem 18.2 with k = 1 mA/V2 •
18.5
Repeat Problem 18.3 with k = 1 mA/V2.
18.6
Repeat Problem 18.2 with RL = 100 kD
18.7
Repeat Problem 18.3 with RL = 100 kD
For the NMOS inverter with rrsistivP lmirl RL
18.8
shown in Figure P18.2, analytically determine the
18.9
Repeat Problem 18.2 with R1 = 200 kD
Repeat Problem 18.3 with RL = 200 kn
183
V.o ·
FIGURE P18.2
1~r
critical voltages Voi-1, V01 _, V1L, V111 , and V~ 1- Use VT
= 1 V and k = 0.1 mA/V2 for N 0 . Sketch the VIC
and determine the noise margins.
18.10
Determine the average static power dissipated in
the NMOS inverter of Problem 18.3.
18.11
Determine the average static power dissipated in
the NMOS inverter of Problem 18.5.
18.12
Determine the average static power dissipated in
the NMOS inverter of Problem 18.7.
18.13
Determine the average static power dissipated in
the NMOS inverter of Problem 18.9.
18.14
Modify the SPICE simulation of section 18.5 for the
different load resistor values
VNor
0
N
(a) RL 3 2 25K0HM
(b) RL 3 2 1D0K0HM
(cl RL 3 2 25DK0HM
Compare the results of the different load resistor values.
SATURATED
HANCEME TON
LOADED
NMOS INVERTER
In this chapter, the operation of the saturated enhancement-only loaded NMOS inverter is described.
This basic inverter consists of two enhancement-only
NMOS transistors and is much more practical than
the resistor-loaded inverter, since the resistor (which
is thousands of times larger than a MOSFET) has
been eliminated.
V011 = VoD - VT,L
As the input is increased above VT,o, transistors
N 0 , and NL begin to conduct with equal drain currents. Since VDs,o 2: Vcs,o - VT,o, transistor No is
operating in the saturation region of operation. The
equation for the VTC is obtained by equating the
drain currents of N 0 and N1. as follows:
In,o(SAT)
19.1 OPERATION OF SATURATED
ENHANCEMENT-ONLY LOADED
NMOS INVERTER
ko
2
Vi,s.L
=
Vcs.L
>
Vcs.L -
ko
2
(ViN -
2
= V1N and Vcs,L = VDD - VoUT
vT,())?~ = kL
2
(VDI)
VOUT
-
-
V T,L )'"
Solving for Your gives
VT,L
VouT
and thus the load transistor NL operates in saturation
only. The input to this inverter is at the gate of the
output transistor N 0 and V1N = Vcs.o- The output is
at the drain of N 0 and VouT = VDs,o = VDD - VDs,L•
For V,N < VT,o, transistor N 0 is cutoff and does
not conduct drain current. The load N,,, however, is
still in the saturation region of operation. The output
voltage is therefore Vou-r = VDD - Vcs,L- With
ID,L = 0, the saturation drain current expression can
be solved for Vcs,L as follows:
= -
)
VIN
+
Vr,o
fi2k° +
L
Voo - V T,L
Note that the output drops linearly with a slope of
-(k 0 /kJ 112 . As a result, the larger the rati9 ko/kL,
the steeper the transition region.
When VDs,o drops below Vcs,o - VT,o, transistor
N 0 enters the linear region of operation and the VTC
begins to reduce quadratically. The VTC of the saturated enhancement-only loaded NMOS inverter
has the form exhibited in Figure 19.2b and will be
explained further in the following section.
As with the resistor loaded NMOS inverter, this
section shows that a low input produces a high output and a high input produces a low output. This
transistor loaded NMOS inverter therefore also realizes the logical NOT function. The next two sections provide graphical and analytical procedures for
ln,L = kL Wcs,1 - Vu. )2 -- 0
2-
Vcs,L
0
V T,o )2 -_ k1 (VGS,L _ V 1'.L) -
(VGs,o -
Substituting Vcs,o
yields
Figure 19. la shows the NMOS inverter with an enhancement-only N-channel MOSFET as a load device. With the gate and drain of the load transistor
N1, connected, we have
= Io.1(SAT)
= Vr,L
As a result, the output high voltage is VDD degraded
by the threshold voltage of NL or
261
262
Chapter 19/Saturated Enhanccmcnt-Onlv Loaded NMOS Irwerter
load NMOS has a
~ body bias of VseJ.
~
=
Your=VNar
WL N
4L
+
Yos,o
(a)
FIGURE 19.1
body-bias
(b)
Saturated Enhancement-only Loaded NMOS Inverter: (a) Source-body connected load, (b) Load with
Your
(V)
t
YOH=
A
VDD - VT;J, -,--.+..l
=4
I
3---+--
V
1-=_ __
OL
--i---_;:B-=----r----Ym=2V
~--!1---------+---=:a.,:;~A:..........,._~~lV
5
Your = V os,o =
Yoo- VD.SJ.(V)
(a)
FIGURE 19.2 Graphical Solution of Saturated
Enhancement-only Load NMOS Inverter: (a)
Enhancement-only NMOS ID versus VDs family of curves
I
~----+---+--1---_;_--+------+--•
Yn,=VT,o=l 2
I
3
4
Vm(V)
5
ylll
(b)
with superimposed saturated enhancement-only NMOS
load curve, (b) Voltage transfer characteristic from
intersections of curves in (a)
19.2
Graphical Determination of Saturated Enhancement-Only Loaded NMOS Inverter VTC
determining the voltage transfer characteristic of the
saturated enhancement-only loaded NMOS inverter. Not only does this case provide a circuit that
can be fabricated in IC form, but also the VTC can
be very abrupt, as we will see.
19.2 GRAPHICAL DETERMINATION
Of SATURATED ENHANCEMENTONLY LOADED NMOS
INVERTER VTC
To determine the VTC graphically, we first realize
that the drain current of NL is equal to the drain
current of N 0 . Also, VDs.L = VDD - VDs,o, so the
drain current Ii).L can be expressed as a function of
VDs,o as follows:
kL
ID.l (SAT) =
2 (Vos.L
=
2 [(VoD
=
kL
kL
2
?
- Vr.L)7
- VDs.o) - VuJ7
[(VDD - Vu) - Vns,oJ- =
ID,o
This expression is the 1-V characteristic for the load
transistor NL, similar to the load-line equation for the
resistor loaded inverter. Therefore, having obtained
this load equation, the voltage transfer characteristic
can be obtained in the same graphical manner as the
resistor loaded NMOS inverter. Figure 19.2a shows
a family of ID.o versus VDs,o characteristics with
Vcs.o as a parameter with the transistor NL load
equation superimposed. Unlike the resistor loaded
NMOS inverter, this output load curve is nonlinear.
To obtain the VTC, ordered pairs of (Vcs,o,
VDs,o) are read from the intersection of the output
load curve with the family of curves. These points are
then mapped into the VDs,o versus Vcs,o coordinate
axes in Figure 19.2b. The resulting curve through the
plotted points is the VTC
Similar to the resistor loaded NMOS inverter,
the output does not reach O as V1N is increased. To
demonstrate this, we again assume that the inverter
is being driven by a similar gate as in Figure 19.3.
The maximum output of the driving gate was determined to be VoUT,D(MAX) = VoH = VDD - Vu, This
corresponds to the Vcs.o = VoH 1-V curve of Figure
19.2a. The output voltage at the intersection of this
specific curve with the load curve is VDs = Vm,
The state of N 0 for each critical point can be
determined by examining the graphs of Figure 19.2a
and b. First, N 0 is cutoff for Vm 1 = VDD - Vu, Then,
for VM, N 0 is in the saturation region of operation
and N 0 is in the linear region of operation for both
VrH and VoL• For an enhancement-only load, VrL is
defined as the threshold voltage of N 0 . The state of
' :1r:N',
V'oo,
V'os,o
\___~
driving gate
FIGURE 19.3
263
load gate
Cascaded Saturated Enhancement-only Loaded NMOS Inverters Illustrating V0 L
264
Chapter 19/Saturated Enhancement-Only Loaded NMOS In verte r
TABLE 19.1 States of Transistors for Saturated
Enhancement-Only Loaded NMOS Inverter
Critical Point
Output N 0
Load NL
VoH
Cutoff
EOC
Saturation
Linear
Linear
Saturation
Saturation
Saturation
Saturation
Saturation
VIL
VM
V11-1
VoL
N 0 at V1L is therefore the edge of conduction. Note
that NL is always in the saturation region of opera tion for the saturated enhancement-only load. These
states are summarized in Table 19.1.
19.3 CALCULATION OF VTC
CRITICAL POINTS FOR SATURATED
ENHANCEMENT-ONLY LOADED
NMOS INVERTER
Va,-, was found in section 19.1 and is repeated here for
convenience
Output High Voltage
= Vott
Output Low Voltage
= VoL
ln the output low state, N 0 and N1. are in the linear
and saturation regions of operation, respectively. Assuming this gate is driven by a sifftilar gate in the
output high state, as in Figure 19.3, V, r- -: = V0 ,_1 =
VoD - Vu. Substituting Vos.a = VoL, and Vcs, 1. =
VDD - Vm into the linear and saturated drain current
expressions gives
and
The output low voltage is found by equating the
drain currents of N 0 and NL as follows:
or
For V, N = Vcs.o < VT,o, N 0 is cutoff and no drain
current conducts in either transistor. With
lru(SAT) = 10 , 0 (0FF) = 0, Vc s,L is found by solving
which yields Vcs,L = Vu. Since the output is VouT
= Voo - Vc s. L, substituting for Vcs.L yields
After some algebra, rearranging terms gives a qua dratic in V01 _ as follows :
kl + ko
2
Input Low Voltage= V1L
The input low voltage cannot be found from dVo uT/
dV,r---: = -1. This is because a discontinuity appears
at V,N = VT,o and the magnitude of the slope follow ing this point is (for a properly designed gate) greater
than unity, as seen in Figure 19.2b. The input low
voltage for this type of loaded gate is therefore
v,l = vT.a
?
V ol+ [- k,.Woo - v.,,1,)
- ko W oo - VT.L - V1,o)JV01
+
kl
,
2 Woo - v,.,)- = o
where V0 1. is sufficiently small to neglect Vb1. resulting in the following expression for Vm:
1lJ.3
265
Calculation of VTC Critical Points For Saturc1ted Enhancement-Only Loaded NMOS Inverter
Solving for V0 c1 gives
Input High Voltage= Vrn
The input high voltage is defined as the point on the
VTC above VoL where
This is the output voltage corresponding to ViH· To
solve for V1H, we equate the drain currents of the two
transistors as follows:
-1
At the input high voltage, N 0 and NL are in the linear
and saturation regions of operation, respectively.
Substituting Vcs,o = V1H, Vos,o = VoL:T, and Ycs,L
= V1)1) - V0 c 1 into the drain current equations yields
ID,o(LIN) = Io,L(SAT)
vil/T]
[
ko (Vi11 - vT,o)VouT - -2-
= kL Won - VcJLIT - Vr,L )2
2
2
k0 [(VIll _ V-1,0)(V111 - VT,o) _ ~ (Vi11 - VT.CJ) ]
2
2
2
2
= kL2 DD (V111 - VT,o) _ V T,L ]
[v _
and
ln,L(SAT) =
=
kL
2 Wcs,L
kL
2
-
VLL
2
)2
,
Wm) - VouT - VT,L)-
where we have substituted for Your and neglected
din,L/dV0ur, for simplicity. Rearranging yields
2
V _ Vi11 - VT,o)
3k 0
4k (Vi11 - VT,o)- = Voo
T,L
2
L
?
With ILJ,o = Io,o(V1N, Vmrr) and Io,L = ID,L(Vour),
equating differentials of the drain currents gives
dlu.0W111, Vm/T) = dln.1Woml
(
Taking the square root of both sides, we have
0
1 ~k
V111 - VT,o
- -k (Vi11 - VT,(J) = Voo - Vr,L 2
I.
2
or
iJlo,o
iJlu,o
dlo,L
- - dVi 11 + - - dVouT = -dV dVour
rJV111
iJVow
ouT
Solving for dVouT/dV 1r--: yields
or
1(~
)(Vi11 2
✓~ + 1
Vr,o)
Voo -
V.r,L
Solving for V1H gives
dVc)UT
dV1N
dio,1. _ iJIJJ,o
d Vour
iJVour
-1
and rearranging, we have
iJlo,o
--=
rJVi11
dlu,L
iJlD,o
--+-
dVouT
BVouT
Substituting for the derivatives yields
koVmrr = kL(Vllo - Vmn
V.r,L)
+ kofW111 - VT,o) - VouT]
Plugging V1H back into the expression for V0 UT(IH)
gives the output corresponding to ViH•
Verification of Output Transistor in Linear
Mode for Vm
The linear region of operation for the output transistor N 0 is verified by testing
V Ds,o
:S
V cs,o - Vr,o
266
Chapter 19/Saturated Enhancement-Only Loaded NMOS In ver ter
or
V ouT(IH)
:S
Vu 1
-
Example 19 .1 Saturated Enhancement-Only
Loaded NMOS Inverter VTC
Vi: o
After calculations, this verification is verified .
Midpoint Voltage
= VM
Find the critical points for the voltage transfer characteristic of a saturated enhancement-only loaded
NMOS inverter. Use VDD = 10 V, (W/L) 0 = 10µ,m/
5µ,ITt, and (W/L) = 5µ,m/15µ,m. Also, use k' = 20
µ,AN" and VTO = 1.2 V for both transistors.
Solution We begin by calculating the transcon1"
At the midpoint voltage, where V,N = V0 ur = VM,
N 0 and NL are both in the saturation region of op eration . For N 0 this is verified by
which upon substituting Vcs,o = V 05 , 0 = VM reduces
to
VM::::,: VM - VT,0
and is clearly satisfied. Substituting Vcs,o = V M,
VDs,o = VM, and Vcs,L = VDD - VM into the saturation drain current expressions gives
Io,o(SAT) =
ko
2
1
ductak:c:p::(~r: f:::::( ;y:o:::s ~:\lows
,(W)
(
A
-5µ,) = 6.67µ,---:,
15µ,
vThis gives a ratio of k 0 /kL = 6.
The critical points can now be found by substituting directly into the derived expressions:
Vo 11 = (10) - (1.2) = 8.8 V
kL
=
k
L
= (20µ,)
L
VIL= 1 .2 V
?
W cs,o - VT_o) -
= -ko (VM - Vrn)?
2
'
6.67µ,(10 - 1.2)2
VOL = - - - - - - - - 2(6,67µ,)(10 - 1.2)
+ 2(40µ,)(10 - 1.2 - 1.2)
=
0 .71 V
and
Vf II = (1. 2) +
2[(10) - (1 ,2)]
--'-;:======-=-_:__:._
3(40,u)
(6.67µ,)
+l
(6.67µ.)[(10) - (1.2))
(40µ,)[(4.6) - (1 .2)]
+
Now VM is found by equating these currents as follows:
Io,o(SAT) = 10 ,L(SAT)
VouT(IH) == - - - ' - - - - - - - 2( 40µ,) + (6.67µ,)
=
2.25 V
(10) - (1 .2)
+
(4 0µ,) (1.2)
6 67
V,v, = -------,===(==·=--µ,-)- - = 3.4 V
1+
Dividing both sides by kL/2 and taking the square
root of both sides gives
~
✓ ki. (VM - VT.O)
(40µ,)
(6.67 µ,)
Note that a larger value for k 0 and/or a smaller value
for kL provides a steeper VTC or narrower transition
width.
= Voo - VM - Vu
19.4 BODY BIAS CONSIDERATIONS
FOR SATURATED ENHANCEMENTONLY LOADED NMOS INVERTER
Finally, solving for V M yields
Voo - Vu
V,v, =
1
+
+
~V
~
✓ ki.
T,o
In the previous section, the threshold voltage of the
load N1_ was taken as constant with VT.L = VTo,L• This,
however, is not at all the case. Figure 19.lb shows
l Y.4
Body Bias Considerations For Saturated Enhancement-Only Loaded NMOS Inverter
26 7
Output High Voltage= Vott
Tips, Tricks, and Gimmicks
Body Bias Effect on NMOS Threshold
Voltage
111 the following section an analysis co11sideri11g the
body bias effect 011 the threshold voltage of N1, will
be presented-the following equation relating the
function depe11de11ce of v,/l 011 VT will be required
As mentioned in the previous section the maximum
output voltage is the source voltage VDD diminished
by the threshold voltage of the load NL or
Von = Vim - Vu(VsR,L = Vos,o)
Taking account of the source to body voltage of NL,
by substitution
Vo11
T11resl10ld Voltage
vl)/)
-
[Vn!,L + YL(YV011 + 2</>r,L
-~)]
V2cf;;)
V1WsB) = Vrn + y(YVsB + 2</>r •
=
Zero body-bias threshold voltage = Vrn
VDD - Vrn,L
Surface potential = <f> r-
+y1,~
Body-Effect Coefficient
=
+ 2</>r.L
Adding 2</> F,L to each side yields
Vol!
= 1.60
•
Elementary charge= q
•
Acceptor
[1/cni3]
•
Permittivity of Silicon = Esi
Flem
•
Gate capacitance per unit area =
dopant
YL YV011
X
+ 2</>r,L = VDD - Vrn,L - Y1YV011 + 2<f>F:L
+ YL ~ + 2<f>F,L
10- 19 C
concentration
=
NA
Rearranging terms gives
Wo1, +
= 1.04
X 10- 12
+ Y1YV011 + 2</>F.L
+ (-Voo + Vrn,L - Y 1 ~ - 2</>F,/) = 0
2</>n)
This is a quadratic (VOH + 2</> F.L). After solving the
quadratic, VoH is easily obtained.
Output Low Voltage = VoL
the saturated enhancement-only loaded NMOS inverter for the actual case with the substrate or body
common to both transistors. Thus, since the substrate of each transistor is grounded, with the source
of N1, at VoL:T, a body bias of Vs11,1. = VDs,o = Vmn
is always present for N1, and should be taken into
consideration to obtain an accurate solution. With
the body bias present, the threshold voltage of N1, is
increased as
The procedure for finding VoL considering the body
bias VsB,L is numerical in nature. The procedure is as
follows:
•
Guess a value for Vm (a good initial guess is
5% of vl)l))
•
Determine the threshold voltage of NL for
this output as follows:
VuWsB,L
=
VDs,o
=
Vo1)
= VTo,1 + Y1(YV01 + 2</>r,L - ~ )
•
Solve for the (saturation) drain current of the
load for this body bias and output as follows:
•
Equate the drain current of N1, to the (linear)
drain current of N 0 to obtain
VT,L Wsu,L = VDs,o = Vm!T)
= Vnu + Y1(YVsu,1 + 2</>r,L - ~ )
= Vrn,L + Y1(YVDs,o + 2¢F.L - ~ )
= Vro,L + YL(\/Vour + 2</>r,L
~)
The following sub-sections illustrate procedures for
analytically solving for the voltage transfer characteristic critical points considering the body bias of NL.
268
Chapter 19/Saturated Enhancement-Onlv Loaded NMOS ln\'erter
•
Determine the threshold voltage of NL for
this output
VufVs1u
Vos,o = VouTUH)] = VTU,L
=
+ 'YL(YVouT(IH) + 2<f>r,L - ~ )
•
Solve for V 1;\J to obtain
•
V IN -- V T,O + Vo1. + ~
k V
2
0 OL
•
Repeat this procedure until V1N is within a
few percent of the VoH calculated in the last
sub-section (we have assumed that this gate
is driven by a similar gate in the output high
state, see Figure 19 ,4)
Input High Voltage
Solve for the (saturated) drain current of the
load
lo.1(SAT) =
=
•
kL
2 Wcs,L
kL
2 Woo
?
- VT,L)- Vou-rUH) - VT,L]2
Equate the (linear) drain current of the output
transistor N 0 to that of the load transistor NL
Io.o(LIN) = ko [ Wcs,o - VuJ)Vos,o - -Viiso]
-'2
= Vm
The method for finding V111 considering the body bias
is also numerical and very similar to the procedure for finding Vm, This numerical solution
method is as follows:
= k0 [ W111 - VT,oWouT(IH) - Vzx/T(IH)]
2
VsB,I.
•
Guess a value for V1H (a good initial guess is
V 1H approximately 45% of V1)I))
•
Determine VoL'T(IH) from the expression
= Io,L
•
VourUH)
Io,L
V111 = VTO + - - - - + - - ~ - '
2
koVowUH)
•
_ VIll - V T,O
V OUT (IH) 2
which was derived in the previous section
Solve for V1H
Repeat this procedure until the solved V,H is
within a few percent of the "guessed" V,H
As will be seen in the next example (Example
19.2), the body bias has little effect on the input high
V'oo
9
WL N
4L
Your= YoH
V'our = YoL
-+-
----y·
driving gate
FIGURE 19.4
-----y--
~---__;
load gate
Cascaded Saturated Enhancement-only Loaded NMOS Inverters with Body Biases
J lJ.4
voltage and the first order approximation is generally
acceptable.
Solution (Output High Voltage) VoH is found by
first solving a quadratic with the coefficients given by
= VM
Midpoint Voltage
Ao11 = l
Bou
The midpoint voltage where VIN = Votsr = V:vt is
found by the following numerical procedure:
=
= V:vI
Vr,L (V,B,1. = Vos,o = VM)
,
Determine the (saturated) drain current for
NL using this Vu and VouT = V:vi
kL
kL
2 (Voo
-
•
Vr.o
- VM - Vu)-
+
~
Repeat this procedure until the solved value
ofVM is within a few percent of the "guessed"
value of V1v1
Input Low Voltage= V1L
A body bias on NL will have no effect on the input
low voltage since it is simply the threshold voltage
at which N 0 enters conduction. Hence,
=
YBz)J/ -
-(0.5)
v'(o.5)2 - 4(1)(-9.79)
4AonC011
2Ao11
:::t::
= 2.89 or -3.39
7
Solve for VM
V 11 .
-Bon±
= ----------
2(1)
2
=
Ve)// +
VT.L)-
ln,o(SAT) = ko (Vcs,o - VT,o )"-
VM
~---1
V
2cf>r,L
7
2 (Vcs,L
• Equate the drain current of N0 (SAT) to the
drain current of NL
•
-9.79.
Using the quadratic formula
= Vrn.L + YL(YVM + 2</>r,L - ~ )
=
Vim+ Vnu - Y 1 . ~ - 2<f>F.L
-(10) + (1.2) - (0.5)\/(o.6) - (0.6)
• Evaluate V.r.L for an output of Vovr
10 ,L(SAT) =
= 0.5
YL
Cou =
Guess a value for VM
•
269
Body Bias Considerations For SJturated Enhancement-Only Loaded NMOS Inverter
Vr,o
Example 19.2 Saturated Enhancement-Only
Loaded NMOS Inverted: Body Bias
Considerations for VTC
Calculate the VTC critical points for the NMOS inverter of Example 19.1 considering the body bias effect of NL. Use y 1_ = 0.5 VI 12 and 2¢r-L = 0.6 V.
The negative term is physically incorrect, hence 2.8
V is the valid solution. Vrn-i is then obtained as
V011 = 2.89 2
-
2c/>r.L = 2.89 2
-
(0.06) = 7.75 V
Solution (Output Low Voltage) Vm must be
found numerically. Initial guesses for Vm are listed
below with the resulting load threshold voltage,
drain current, and solved V1N values.
Vm(guess) (V)
VT,L(V)
10 (µA)
VIN (V)
0.7
0.8
0.9
0.85
0.82
1.38
1.40
1.43
1.41
1.41
209
203
196
199
201
9.01
7.93
7.10
7.49
7.74
The guess of Vm = 0.82 V results in a V1N of 7.74 V,
the value calculated for V011 above.
Solution (Input High Voltage) V1H is also found
numerically. Initial guesses for V1H are shown below
with the resulting corresponding output, threshold
voltage of NL, and the value of V1H for this load
threshold voltage.
V11 1(guess) (V)
VouT (V)
VT,L (V)
Io,L (µA)
V1H (V)
4.3
4.4
4.5
4.45
4.42
1.55
1.60
1.65
1.63
1.61
1.55
1.55
1.56
1.56
1.56
159
156
154
155
156
4.54
4.44
4.35
4.40
4.42
2 70
Chapter 19/Saturated Enhancement-Only Loaded NMOS Inverter
From this iteration, V11_1 = 4.42 V. Comparing this to
the value of V111 calculated in Example 19.1, we see
a difference of only 0.18 V. The iteration process for
determining V1H hence appears unnecessary and the
first order approximation of the previous section
shall suffice.
state is then obtained by substituting these voltages
into the linear drain current expression yielding
Solution (Midpoint Voltage) The numerical determination of V :vr is tabulated below.
Static Power Dissipation = P00 (avg)
VM(V)
VT.L (V)
Io,L (µ.A)
VM (V)
~
1
J.i
1
_l.J/
U/.U
0'7 L
'] ')[\
J.L.../
3.2
3.3
3.25
3.23
1.79
1.80
1.79
1.79
83.8
80.0
81.9
82.6
3.24
3.20
3.22
3.23
'7'7
Thus, VM is 3.23 V, which is also quite close to the
value calculated in Example 19.1, which was 3.4 V.
Solution (Input Low Voltage) VrL is unaffected
by the body bias for this type of load and remains as
VIL= 1.2 V
Ivo(OL)
=
Io,L(SAT)
= ko [ (Vcs,o
=
-
ID_o(LIN)
Vr.o)Vos,o - -Vbs,o]
2
The average DC power dissipated is now found by
substituting into
Poo(avg) = loo(OH) + foo(OL) Voo
2
Ioo(OLWoo
2
Dynamic Power Dissipated= P00 (dyn)
As with resistor-loaded NMOS, a significant additional power dissipation for enhancement-only
loaded NMOS logic circuits occurs during the
switching of logic states. This contribution takes the
form
P/)/J(dyn) = CL1Nbo
19.5 POWER DISSIPATION OF
SATURATED ENHANCEMENT-ONLY
LOADED NMOS
To determine the power dissipation of a saturated
enhancement-only loaded NMOS inverter, the DC
currents supplied by VDD for the high and low output
states are first obtained.
Output High Current
Supplied = I00 (OH)
where CL is the total load capacitance at the output
of the gate and vis the frequency at which the gate
switches logic states.
Example 19.3 Power Dissipation of
Enhancement-Only Loaded NMOS
(a) Find the static power dissipated in the saturated
enhancen-ient-only loaded NMOS inverter of
Example 19.2.
(b) Find the dynamic power dissipated for the same
gate. Let CL = 1.5 pF and v = 10 MHz.
In section 19.2 it was seen that N 0 is cutoff in the
output high state (see Table 19.1). With N 0 cutoff,
Solution (a) For the output low state, the terminal
voltages of N 0 were found in Example 19.2 to be
l 00 (OH) = Io,i(SAT) = Io.o(OFF) = 0
Vcs,o = ViN(OL) = 7.74 V
Output Low Current = I00 (OL)
For the output low state, N 0 is in the linear region
of operation. For the terminal voltages of N 0 for this
state, the expressions of section 19.3 for non-bodybias considerations can be evaluated for an approximate solution, or the numerically determined values
of the previous section may be used for a more accurate result. The current supplied for the output low
and
VOL= 0.82 V
The current dissipated in the output low state is
therefore
10
2
= (40J.L) [ (7.74 - 1.2)(0.82) - -(0.82)- ]
2
= 201 J.LA
19_(,
Hence, the JverJge DC power dissipJted is
,,-+la
VDDn.T DC 1OV
O
...L
0
271
Saturated Enhancement-Only Loaded N!V!OS SPICE Simulation
PDD(avg)
(201 µ,)
(10) = 1.01 mW
2
=- -
Solution (b) The dynamic power dissipated is
PDD(dyn) = (1.5p)(10M)(10) 2 = 1.SmW
Your
19.6 SATURATED ENHANCEMENT ONLY LOADED NMOS SPICE
SIMULATION
Figure 19.5 shows a saturated enhancement-only
loaded NMOS inverter with a capacitive load with
appropriJte SPICE labelings. The SPICE input CIRcuit file that represents this circuit is as follows:
FIGURE 19.5 Saturated Enhancement-only Loaded
N!V!OS Inverters with Capacitive Load and Appropriate
SPICE Labelings
Saturated E-0 Loaded NM◊S
Inverter
VIN 1 D PULSE<DV 10V OS 2NS 2NS
+ 500NS 1US)
Ym(Y)
•
10--1,,-----.
9 .
8
7
6- 5 -
Your (Y)
4.
10-L
4-
9+
3 2
1
O
8~
I
7~
t(µs)
0
6
0.25
0.50
0.75
1.00
1.25
YourCY)
5~
4
109
3
8
2
76
5
4
1
0
I
0
1
2
3
4
5
6
7
8
9
10
3
2
1
0 +-------+---f------+--------1------1----- t(µs)
0.25
0.50
0.75
1.00
1.25
0
(a)
FIGURE 19.6 Results of Section 19.6 Saturated
Enhancement-only Loaded NMOS SPICE Simulation:
(b)
(a) Voltage transfer characteristic obtained from .DC
sweep, (b) Transient response from .TRAN sweep
272
Chapter 19/S aturated Enhancement-Only Luc1ded Nf'vlOS Im w ter
VDD 3 0 10V
,MODEL NMOSFE T NMOS<V T0=1,2
+ KP=20U GAMMA=0,5 PHI=0-6
+ CBD=3,1E-15 CBS=3-1E - 15)
MN◊ 2 1 0 0 NMOSFET W=10U L=SU
MNL 3 3 2 0 NMOSFET W=SU L=15U
CL 2 0 1PF
-DC VINO 10 0-1
-PLO T DC VDS<MNO)
,TRAN 20NS 1-25US
,PLOT TRAN V<VIN) VDS(MNO)
,END
Th e VTC and transi ent response obtained fro m simulating this circuit are shown in Figure 19.6a and b.
CHAPTER19PROBLEMS
19.1
What arc th e states of N 0 a nd NL for th e sa turated
enhancement-only loaded NMOS inverter for each
of th e vrc critical points Vm1, VnL, V1L, V111, and
v~•I·
19.2
19.3
19.4
For the NMOS in verter with sa tura ted enhancement-only load shown in Figure P19.2, gmphica lly
de termine th e critical voltages Vu 11 , VOi_, V1L, V111 ,
and Vt-,,1. Use V 1 = 1 V and k' = 20 µ.A!V2 for both
Nu and NL. Sketch th e VTC and determin e th e
noise marg ins. (Ignore th e body-bias of NL.)
For th e NMOS inverte r with sa turated en hance ment-onl y load shown in Figure Pl 9.2, a11alytically
determine th e critical vo ltages Vm 1, Vm, V1L, V11 1,
and V.,,1• Use V 1 = 1 V a nd k' = 20 µ.A/V" for both
N 0 and NL· Sketch th e VTC and de term ine th e
noise margins. (Ignore th e body-bias of NL.)
For the NMOS in ve rte r with saturated en hance ment-o nly load shown in Figure P19.4, a11alytically
determi ne th e critica l voltages V011 , Vrn_, V1u and
V111 . Use V 1 = 1 V a nd k' = 20 µ.A ~ for both N 0
and N1.. Sketch th e VTC and determin e th e noise
V00 = 5 V
VNOT
20µm N
2µm 0
FIGURE P19.4
margins. Co nsider th e body-bias of NL. Use Y1. =
0.4 V 11" and 2</J,.L = 0.6 V.
= 20µ.m/4µ.m .
= 20µ.m/4µ.m.
19.4 for (W/L) 0 = 20µ.m/4µ.m.
19.2 fo r (W/L) 0 = 100µ.m/2µ.m.
19.3 for (W/L) u = 100µ.m/2µ.m.
19.4 for (W/L) 0 = 100µ.m/2µ.m.
19.2 for (W/L)L = 1.
19.5
Repea t Problem 19.2 for (W/L) 0
19.6
Repeat Proble m 19.3 fo r (W/L)u
19.7
Repeat Problem
19.8
Repeat Problem
19.9
Repeat Problem
19.10
Repeat Problem
19.11
Repea t Problem
19.12
Repea t P ro blem 19.3 for (W/L)1.
19.13
Repeat Problem 19.4 for (W/L)L
= 1.
= 1.
= 5µ.m/10µ.m.
19.15 Repeat Problem 19.3 for (W/L)1. = 5µ.m/10µ.m.
19.16 Repea t Problem 19.4 for (W/L)L = 5µ.m/10µ.m.
FIGURE P19.2
19.14
Re peat Problem 19.2 fo r (W/L)L
19.17
Find the s tati c power dissipated in th e NMOS inverter of P roblem 19.3.
19.18
Find th e s ta ti c powe r dissipa ted in the NMOS inverter of Problem 19.4.
Chapter 19
Problems
273
19.19
Find the static power dissipated in the NMOS inverter of Problem 19.6.
19.23
Find the static power dissipated in the NMOS inverter of Problem 19.12.
19.20
Find the static power dissipated in the NMOS inverter of Problem 19. 7.
19.24
Find the static power dissipated in the NMOS inverter of Problem 19.13.
19.21
Find the static power dissipated in the NMOS inverter of Problem 19.9.
19.25
Find the static power dissipated in the NMOS inverter of Problem 19.15.
19.22
Find the static power dissipated in the NMOS inverter of Problem 19.10.
19.26
Find the static power dissipated in the NMOS inverter of Problem 19.16.
20
LINEAR
ENHANCEMENTONLY LOADED
NMOS INVERTER
In this chapter, the operation of the linear e11ha11ceme11t-only loaded NMOS inverter is described. This
inverter has the advantage of increased VoH up to
the supply voltage value V1m. However, this inverter
also has a disadvantage that two separate DC supplies are required (or two bias resistors which is
worse). Hence, this case is not of practical import but
is included for completeness.
Hence, as a result
Vo11
=
Voo
I o,o (SAT) = In, 1 (LIN)
or
The output high voltage of an enhancement-only
loaded NMOS inverter can be raised to Vno by using
a load that operates in the linear region. This is accomplished by applying a separate, larger voltage
source to the gate of NLt as shown in Figure 20.1a.
To operate in the linear region VeD,L must be greater
than VT,L. Thus, the gate voltage should satisfy
-- kL (VCS,L - VT,L )VDS,I.
[
-
v
2
- OS,L
- ]
2
Substituting Vcs,o = V1N, V05 ,0 = VoUT, Vcs,L = Vee
- VoL·T, and VDs,L = VDD - VmJT yields the VTC for
this case. Solution ofVoUT as a function ofV,N shows
that the output has a negative slope in this region of
operation and this is left as a homework problem.
\!\Then VDs,o drops to Vcs,o - VT,o, N 0 enters
the linear region of operation. The VTC of the linear
enhancement-only loaded NMOS inverter has the
form shown in Figure 20.2b and is explained in detail
in the next section,
Again, the analysis shown here indicates a high
output for a low input and a low output for a high
input. The logical NOT function is thus also realized
by this circuit. The following two sections demonstrate graphical and analytical techniques for finding
the voltage transfer characteristic of the NMOS inverter with linear enhancement-only load.
Vi)[) + Vr,L
The circuit configuration in Figure 20.1a is therefore
a linear enhancement-only loaded NMOS inverter.
The input is at the gate of N 0 and V1N = Ves,o• The
output is at the drain of N 0 and Vrnrr = Vns,o =
Vee
Ves,L = Voo - Vos,L•
For V1N < Vr, 0 , N 0 is cutoff and does not conduct a drain current. The load NL, however, is still in
the linear region of operation. The output is then
VouT = VDD - VDS,L· With ID,L(LIN) = ID,o(OFF) =
0 and Vos,L = 0 is obtained by solving
Io,dLIN) = kL[ Wes,L - VuWos,L -
Voo - Vos,L
As V1N is increased beyond VT,o, both N 0 , and
NL, begin to conduct (equal) drain current. N 0 is operating in the saturation region of operation, since
VDs,o 2: Vcs,o - Vr,u• The form of the VTC at this
point is found by equating the drain currents of N 0
and Ni_ as follows:
20.1 OPERATION OF LINEAR
ENHANCEMENT-ONLY LOADED
NMOS INVERTER
Vee>
=
V~s,L] = 0
274
20.1
VDD
Yoo
Yoo
Q
8
s .
4
~""~•J-~
V
111-7B WON
¼
fsl-b
G
IN~
V
as,o
L
V~
o
Yoo
L~rr,
I
L1 I~ BW" N
~,2~.
+
V
VDS.O
{~
~
IN +
V
os.o
I__
I
load NMOS has a
body bias of Vs•.L =
Your= VNar
WL N
4L
Your
+
WON
Ln0
0
VDS,O
(b)
Linear Enhancement-only Loaded NMOS Inverter: (a) Source-body connected load, (b) Load with
Your
A
0 VOL 1
B
IslJ
(a)
FIGURE 20.1
body-bias
275
Operation of Linear Enhancement-Only Loaded NMOS Inverter
2
3
4
VoH=5
(V)
Vour = Vns.o =
VDD - VDS,L (V)
VIN= 1 V
(a)
FIGURE 20.2 Graphical Determination of Linear
Enhancement-only Loaded NMOS Inverter Voltage
Transfer Characteristic: (a) Enhancement-only NMOS ID
versus DDs family of curves with superimposed linear
Vm<V)
(b)
enhancement-only NMOS load curve, (b) Voltage
transfer characteristic obtained from curve intersections
of (a)
276
Chapter 20/Linear Enhancement-Only Loaded NMOS Irwerter
20.2 GRAPHICAL DETERMINATION
OF LINEAR ENHANCEMENT-ONLY
LOADED NMOS INVERTER VTC
As with the saturated enhancement-only load, the
drain current of N,, is equal to the drain current of
N 0 . With Vos,L = VoD - Vns,o and Ves,1. = Vee V0s,o, Io,L can be expressed as a function of VDs,o as
follows:
Io,L(LIN)
, I,,,
KLL lVes,L
., ,.,
Viis.J
- V1;L)Vos,1. - -
2
-J
ki[ Wee - Vos,o - VT,L)Wvv - Vvs,o)
_ (Vnv - VDs,0)2]
2
This expression can be plotted versus VDs,o and is
the equation for the output load curve. Figure 20.2a
shows a family of 10 , 0 versus V Ds,o curves with Vcs.o
as a parameter and the NL output load curve is superimposed. Like the saturated enhancement-only
load, the curve for the linear enhancement-only load
is non-linear.
Ordered pairs of (Vc;s,o, VDs,o) are read from the
intersection of the non-linear curve with the family
of curves. These are, in turn, mapped onto the VDs,o
vs Vcs.o coordinate axes in Figure 20.2b. The voltage
transfer characteristic is the resulting curve through
these mapped points.
It was seen with the resistor and saturation enhancement-only loads that the output does not
reach Oas the input is increased. This is also the case
with the linear enhancement load. Assuming this inverter is driven by a similar gate, as in Figure 20.3,
the highest input possible is V11.JMAX) = V011 =
VDD· Following the Vcs,o = VDD cu1ve in Figure 20.2a
to its intersection with the output load line gives the
output low voltage on the Vns,o axis.
The state of N 0 can be determined for each critical point from this graphical analysis. As already
stated, N 0 is cutoff for V011 . For Vn, and V".'' N 0 is
in the saturation region of operation. For V,H and
V0 1., Nu is in the linear region of operation. NL is
always in the linear region of operation for the linear
enhancement-only load. These states are summarized in Table 20.1
TABLE 20.1 States of Transistors for Linear
Enhancement-Only Loaded NMOS Inverter
Critical Point
Output No
Cutoff
Saturation
Saturation
Linear
Linear
Vu11
V11.
V\I
V111
V,,L
V'00
V'oo
C
f
LJ ,
I
I~
WLN'
·r;:L
D,o-- I
D,l.•1' ~ V'our~-V
I,
l~W'
V'm
I~
,
I
Vos.a
driving gate
FIGURE 20.3
r:
OL
+
,
N'0 V'os,o
load gate
Cascaded Linear Enhancement-only Loaded NMOS Inverters for Vm. Illustration
Linear
Linear
Linear
Linear
Linear
20.3
Calculation of vrc Critical Points for Linear Enhancement-Only Loaded NMOS lnverter
or
20.3 CALCULATION OF VTC
CRITICAL POINTS FOR LINEAR
ENHANCEMENT-ONLY LOADED
NMOS INVERTER
dln.o dV
dln.1
11 = - - dVouT
dV 11
·
dVouT
V011 was found in section 20.1 and is repeated here for
convenience
Output High Voltage
Solving for dVmrrldV 1N
to -1 yields
For V1N = Vcs,o < Vr,o the inverting transistor N 0
is cutoff and no drain current conducts (in either
transistor). NL is, however, operating in the linear
region of operation. Vos.L can found by solving the
linear drain current expression for l 1u(LIN) = 0 or
dVucrldVn. and equating
dio,o
dViL
dlo,L
dVour
v ;s,L ] =
Separating the derivatives, we have
dID,o
dV,1.
0
_ dlo.l
dVouT
ko(VIL - Vr,o) = -k1.[(-Vcc + 2Vo1n
+ Vu - Voo) + Woo - Vmn)l
From this, Vos,L = 0. Since VocT = VDD - VDs.L
Solving this equation gives a linear expression for V11.
in terms of Vour
Vo11 = Voo
=V L
1
The input low voltage is defined as the point on the
VTC below Vo1-1 where
Another expression relating V1L and VocrOL) is obtained by equating the drain currents of N 0 and NL:
-1
lo.o(SAT) = 11),L(LIN)
At the input low voltage N 0 and NL are in the saturation and linear regions of operation, respectively.
Substituting Vcs.o = V1L, Vcs.1. = Vee - Vour, and
VDs. 1_ = VoD - Vocr into the drain current equations
gives
ko (VIL - Vr,1)~" = k1_ [ Wee
2
_ V
2
Io.i(LIN) = k1. [ Wc.s.L - Vr.LWos,L -
-
v ;s,L ]
Vour - V1,l)W1m - Vow)
_ Won - Vour)2]
-
Vol/7 - Vr.,)Woo
) _ Woo - Vour?]
OUT
= VoL
For the output low voltage, N 0 and NL are both in
the linear region of operation. Assuming this inverter
is driven by a similar gate in the output high state,
as in Figure 20.3, V1N = V0 1-1 = V DD· Substituting this,
VDs,o = VouT, Vcs,L = Voo - Vm;r, and VDs,L = VDD
- Vm;r into the linear drain current expressions
gives
2
With ID,o = ID, 0 (V 1N) and Io.L = 10 ,L(Vour), equating
differentials of the drain currents yields
dln.0W1L) = dli),LWour)
2
Solving these two equations simultaneously yields
V1L and its corresponding output Vm:AIL).
Output Low Voltage
and
kl[ Wee
-1
Substituting these derivatives gives
2
Input Low Voltage
=
= VoH
l1J.L(LIN) = kl [ Wcs.1. - VT.LWos,L -
277
Io,o(LIN) = kc.{ Wcs,o - Vr,oWos.o -
V~rn]
278
Chapter 20/Linear Enhancement-Only Loaded NMOS ln\'crter
and
o
Vf)s,L]
kL [ (Ves,L - VT,L ) Vbs,1, - - 2
and
k1,[ Wee - VOL - Vr,L)Woo - Vo1,)
- Wo[)
~
lo,1(LIN)
Vail]
k1,[Wcs,L - Vu)Vos,L - V;s,L]
kL[ Wee - Vow - Vr,L)WoD - Vour)
The output low voltage is again found by equating the drain currents of the inwrtine ;mo load transistors:
lo,o(LIN) = lo,L(LIN)
[
k 0 (V 0 o - Vr,dVoL -
With Io,o = ID,O(VIN, VocT) and ID,L = Io,L(Vour),
equating differentials of the drain currents gives
Vz)L]
dlo,uW111, Vour) = dlo,1,Wour)
k1,[ Wee - VoL - VT,L)Woo - VOL)
~
'JI
dV111
c_ o,o dV111
dlo,L
+ r,'JI o,o dVouT = - dVouT
r7V0 ur
2
dVouT
dVnv
vz
OL
+ [-koWoo -
=
dVouT
dV111
=
Vw) - kLWcc - VT,L)]V01,
+ k1, [ (Vee - VT,L)Voo - -Vbo]
= 0
2
aio,o
_ _ _a_V_11_1_ _
_d_Io_,l_, _ _r7_Io_,c_,
dVouT
aVouT
-1
Rearranging, we have
aio,o
BVi11
dlo,L
dVouT
aIo,[
aVouT
--=---+--
Finally, Vm is sufficiently small to neglect the V~11,
term, resulting in
k1, [ Wee - Vu)Voo - -Vfio]
-
2
VoL = - - - - - - - - - - - - koWno - VT,O)
dVOLrr
Solving for dV0UT/dV1N = dV0 lJT/dV,r1 and equating
to -1 yields
Vo1Y]
Rearranging terms gives a quadratic in Vm
ko + k1,
j
\27
' OU/ I
2
2
_ Wov
11
(1/
\ ' UU
+ k1,Wcc - Vu)
The dI 1n/dVrn.:T term is negligible in comparison
with other terms, and thus
BI 0 ,0
av111
Bl 0 , 0
avouT
Substituting the derivatives yields
Input High Voltage= Vm
koVour = ko[Wn, - Vr,o) - Vourl
The input high voltage is defined as the point on the
VTC beyond VO1,, where
dVour
dVIN
and solving for Your gives
-1
At the input high voltage, N 0 and NL are both in the
linear region of operation. Substituting Vcs,o = V,J\;,
Yos,o = VouT, Vcs,L = Vee - YouT, and Yos,L = Yoo
- VoUT into the drain current equations yields
V OUT (JH)
_ Vn1 - Vr,o
2
-
This is the output voltage corresponding to ViH• To
solve for Vn~, the drain currents of the two transistors
are equated to obtain
20.3
Calculation of vrc Critical Points for Linear Enhancement-Only Loaded NMOS Inverter
and is obviously true. Substituting Ycs,o = VM, VDs,o
= VM, Ycs,L = Yee - VM, and VDS,L = v l ) l ) - VM
into the drain current equations gives
ID.o(LIN) = In., (LIN)
ko
[ (Vi11 -
Vzx/Tj
v,,oWouT - -2-
Io,o(SAT) =
= kL[ Wee - VouT - VT.L)Wov - Vour)
_ W DD - VouTf
279
j
ko
2
?
Wcs,o - VT,0)-
= ko (VM
2
V T,O )2
2
and
or
k
0
2
[(v _v )(v//, -2 v,.o) _~2 (Vi11 -2 VT,0)
/If
lo,L(LIN) = kL [ Wcs,L - VT,LWos,L -
2
]
v ~s,L
j
1,0
= kL [
(v - Vin CG
V _
( DD
= kL[ Wee - VM - VT.L)Woo
VT,O -
2
Vi11 -
VM)
vT,L)
_ Wvo; VM)2]
VT,O)
2
_12 (vDD _Vn, -2 Vr,o)
2
]
VM is now obtained by equating the drain currents
as follows:
] 0,0
After considerable algebra (rearranging, collecting
like terms), a quadratic in (V1H - VT_o) is obtained as
follows:
(SAT) = ]D,L (LIN)
or
ko (VM
2
VT,O )?-
= kL[ Wee - VM - vT,L)WoD - VM)
Woo; VM)2]
Expanding and collecting like terms leads (eventually) to the quadratic
Using the quadratic formula the solution for V 1H is
easily obtained.
Midpoint Voltage= VM
For the midpoint voltage at which V 1N = VoUT = VM,
N 0 and NL are in the saturated and linear regions of
operation, respectively. For N 0 , this is realized by
testing the inequality
Vos,o
2::
Vcs,o - V T,o
which upon substitutingVcs,o = VDs,o = VM reduces
to
(
ko - kL) ,
VM + [kLWec - VT,L) - k 0 Vv]VM
2
VbD]
kL
- kLWcc - VT,LWoo + - + [ -ko VL
2
2
=0
The solution is then easily obtained using the quadratic formula.
Example 20.1 Linear Enhancement-Only
Loaded NMOS Inverter VTC
Find the VTC critical points for a linear enhancement
only loaded NMOS inverter. Use V DD = 5 V, Vcc =
10 V, 0N/L)o = (10µ,m/5µ.m), and 0N/L)L =
280
Chapter 20/Linear Enhancement-Only Loaded NMOS Inverter
(5µm/20µm). Use k'
for each transistor.
= 20 µ,AN 2 and V10 = 1.1 V
V 11 = 1.61 or 0.590 V
Solution (Device Transconductance Parameters) The transconductance parameters for each
transistor are calculated first, as follows:
,(W)
L
k ,(W)
T
ko = k
O
= (20µ,) (10µ,)
5µ, = 40
kl
L
= (20µ,)
=
Finally, solving this reduced quadratic yields
/1,
A
v2
(
5µ,) = 5 µ, v2
A
20µ,
This gives a ratio of k 0 /k 1 = 8.
Solution (Output High and Low Voltage) Vm 1
and VOL are now obtained by substituting directly
into the derived expressions yielding
Vm1 = 5 V
and
Since V1L must be greater than Vr,o = 1.1 V, the valid
solution for V 1L is therefore 1.61 V.
The output voltage at V11 _ is obtained by substituting into the above expression for Vrn_;1 (IL) yielding
VourUL)
+ 17.7
= -8(1.61)
= 4.82
V
Solution (Input High Voltage) Next, V1H is found
by first solving the quadratic in V111 - Vr, 0 . The coefficients for this quctdratic are calculctted as follo·ws:
A
_ 3k0
Ill -
kl _ 3(40µ,) - (5µ,) _
8
- 14 .4 /1,
-
8
BIll -- k L Vee - Vu -- (5 /1,) (10) - (1.1) -- 22 · 3 /1,
2
2
and
I
Vzm - Wee - v,,1.)V[)l) ]
C111 = kLL_2_
(5µ,){ [(10) - (1.1)](5) - (:;"}
Vm = (40µ,)[(5) - (1.1)] + (5µ,)[(10) - (1.1)]
= (5µ,){
(Sr - [(10) -
(1.1)](5)}
= -160µ,
= 0.798 V
Utilizing the quadratic equation, we have
Solution (Input Low Voltage) V1L is found by simultaneously solving the linear and quadratic
expressions developed. Substitution into the linear
expression yields
V111 - Vr.o
-B111 ± \/Bf11 - 4A111C111
2A111
-------4(14.4µ,)(-160µ,)
- (22. 3 µ,) ±: \/(22.3µ,) 2
(5µ,)
ViL = (1.1) + -(-) [-Vour + (10) - (1.1)]
2(14.4µ,)
40µ,
- Vour + 2 21
8
.
Solving for Vour(IL) yields
Vau,(IL) = -8Vn + 17.7
Substituting into the quadratic expression gives
(40µ,) (V
2
//,
where the positive 2.65 Vis the value of interest.V 111
is therefore
Vi 11
= 2.65
+ V,,o
= 2.65
+ (1.1)
= 3.75
V
The output voltage at V 1H is
75
VourUH) = (3 - ) ; (1.l) = 1.33 V
- 1.1)2
= (5µ,{ (-8.8 + 8Vn)(-12.7 + 8Vn)
- (-12.7; 8V1L?]
and collecting like terms, we have
(140µ,)VTL.
= 2.65 or -4.20 V
+ (-308µ,)ViL + (133µ,) = 0
Solution (Midpoint Voltage) The midpoint voltage is also obtained by solving a quadratic. The coefficients are calculated as
A,\1 =
k0 + k1
2
=
(40µ,)
+ (5µ,)
2
= 2.25µ,
= BM = kLWce - Vu) - koVr,o
= (5µ)[(10) -
(1.1)] - (40µ)(1.1) = 0.5µ
20.4
Body Bias Considerations for Linear Enhancement-Only Loaded NMOS Inverter
,:md
Output High Voltage
koV}o
kLVY,n
- - k1(Vcc - V1,1)Vnu + - 2
2
(40µ,)(1.1)2 - (5µ,)[(10) - (1.1)](5)
2
(5µ,)(5)2
+---
Vi\,1
VoH = Voo
Output Low Voltage = VoL
Using the quadratic equation yields
-BM ::!:
= VoH
The body bias of NL has no effect on the output high
voltage. Since the load is designed to operate in the
linear region, V0 s,L can decrease all the way to O V.
Therefore, V011 is still given by
-136µ,
2
281
VB~ - 4AMCM
== - - - - - - - - -
2AM
~-~------- (0 .5 µ,) ::±: \/(0.5µ,)2 - 4(22.5µ,)(-136µ,)
The numerical procedure for finding VoL considering
VsB,L is almost identical to the corresponding method
of the saturation enhancement-only load. The only
difference is that NL operates in the linear region of
operation. The procedure is as follows:
2(22.5µ,)
= 2.45 or -2.47
Hence, the solution for
V
•
v~., is the positive 2.45 V.
Guess a value for V0
about 5% of V0 o),
•
Determine VT.L for this output
vT,1(VsB,L
=
1.
(a good initial value is
Vos,o = Vo1J
= Vro,L + YL(\/~V_o_L_+_2_</J_r_,L - ~ )
20.4 BODY BIAS CONSIDERATIONS
FOR LINEAR ENHANCEMENT-ONLY
LOADED NMOS INVERTER
The treatment of the previous section for the linear
enhancement-only loaded NMOS inverter ignored
the body bias on the load transistor, N1,. This section
will present the procedures for calculating the VTC
critical points considering VsB,L· Figure 20.lb shows
an enhancement-only loaded NMOS inverter (with
the load configured to operate in the linear region of
operation) with the body common to both transistors. With the output of the inverter taken at the
source of the load, a body bias of Vsri,L = V os.o =
VouT is present for NL and should be taken into consideration for calculations that lead to more than a
first order approximation. With the body bias present, the threshold voltage of NL is given by
V1,tWsB,L = Vos,o = VouT)
= VTO,L + YL(v~V-s1-J,I-._+_2_</J_r-,L - ~ )
•
Solve for the (linear) drain current of NL with
this body bias and output voltage
ID,i(LIN) = k{ Wcs,L - VT.LWos,L - V~s,L]
= kL[ (Vee - Vm - VT.L)Woo - VcJL)
_ (VOD
~
Vo1Y]
•
Equate the drain current of NL to the (linear)
drain current of N 0
•
Solve for V1N
•
Repeat this procedure until V1N is within a
few percent of the VoH calculated in the last
sub-section (we have assumed that this gate
is driven by a similar gate in the output high
state, see Figure 20.4).
= Vrn,L + YL(YVos,o + 2</Jr,L - ~ )
= Vrn,L + YL(YVouT + 2</Jr,L - ~ )
The following sub-sections illustrate procedures for
analytically determining the voltage transfer characteristic critical points considering the body bias
of NL·
282
Chapter 20/Linear Enhancement-Only Loaded NMOS Inverter
V'GG
V'oo
'y
0
!:~:~
!
~~ I ~~
I'o.o=I'o.l-i;
+
IL_
~
Vm=low~:~
V'IN
Wo
Ln0 NO VDS,O
N',
V'om:VoL
L_,
:~
+
Vas,o • •
-::-
driving gate
FIGURE 20.4
load gate
Cascaded Linear Enhancement-only Loaded NMOS Inverters with Body Biases
Input High Voltage
= Vrn
The numerical method for finding VrH considering
the body bias VsB.L is also very similar to the corresponding method for the saturated enhancementonly load. Again, the difference being the load is in
the linear region of operation. The procedure is as
follows:
•
Guess a value for V 1H (a good initial guess for
V 111 is about 45% ofV00 )
•
Determine VouT(IH) from the expression
VOUT (IH)
= kL { [Vcc
- Vouy(IH) -
~T,d Woo -
Vouy([H)]
_ Woo - ~ouT(IH)J-}
• Equate the drain current of NL to the (linear)
drain current of N 0 :
Io.dLIN)
_ V111 - VT,O
-
2
which was derived in the previous section.
•
Determine the threshold voltage of NL for
this output
VT.LWsB,L
=
Vos.o
=
•
Solve for V1H
Vow·UH)]
~------
+ YL(YVoUT(IH) + 2<f>r.L
-~)
Vrn,L
•
• Repeat this procedure until the calculated V11.1
is within a few percent of the "guessed" V 11+
Solve for the (linear) drain current of the load.
As will be seen in Example 20.4, the body bias has
little effect on the output high voltage and the first
order approximation is generally acceptable.
•
Input Low Voltage= V1L
Vil. considering the body bias on the load transistor
entails guessing YcMr(IL) and solving for Y11 . using
two separate equations. The procedure is as follows:
Determine the (linear) drain current for N 1
using this value of Yu and VouT = V~1
2
I O,L (LIN)
=
• Guess a value for YoLrr(IL) [a good initial
guess for V0L'1 (IL) is about 95% of VDo)
• Evaluate Vr,L for Y0 ui
2
vDS,L
2
Vmn/
2
=
Iw,(SAT)
= ko W11 -
2
Vii =
Vr,o +
=
ko
2
Vr,o)
VT,O
(Ves,o - Vr,o)
•
ko
2
Wcs,o - Vr,0)2
Solve for VM
~
Calculate the VIC critical points for the linear enhancement only loaded NMOS inverter of Example
20.1 considering the body bias effect on NL. Use
YL = 0.45 V112 and 2¢ F,L = 0.6 V.
Solution (Output High Voltage)
V011 is not ef-
fected by the body bias and is still
from the previous section
• Repeat this procedure until the two values of
V11 _ are within a few percent of each other
=V
M
V0 u
=5
V
Solution (Output Low Voltage) The numerical
method for finding Vm is demonstrated in the following table:
= VM is
• Guess a value for VM
• Evaluate V1 ,L for an output of Your= VM
VuWsB,L = VDs,o = V,vr)
= Vro,L + ')'1.(v-v,\_1_+_2</J-1--·,1. -
• Repeat this procedure until the guessed value
of VM is within a few percent of the solved
value of V~,1-
Example 20.2 Linear Enhancement-Only
Loaded NMOS Inverter: Body Bias
Considerations
2
The midpoint voltage where V1N = Your
found by the following numerical process:
rv;;;
✓ -y;;;
2
kL
+ ko (-Vrnrr + Vee - Vr,1J
Midpoint Voltage
=
V M =VT,O +
• Solve for V1L using
Vi,=
Io,o(SAT)
l
• Equate the drain current of NL to that of N 0
and solve for Vu.
10 ,1 (UN)
- VM - Vr,1)(Vnu - VM)
l
k1[ Wee - VouT - Vr,L)WvD - Vour)
-
l
• Equate the drain current of N 0 (SAT) to the
drain current of NL
• Determine the (linear) drain current for NL
using Vour(IL) and Vu[Vsfl,L = Vour(IL)]
_ (VDD
[
v/JS,/
2
_Woo; VM)2l
-~]
= k L[ (VGS,L - V T,L )VOS,/ -
kI. (VCS,L - VT,J. )VDS,L -
k1.[ (Ve<~
= V0 u1(IL)
VT,1WsR,1. = VDs,o = VouT(IL)]
-----= Vrn,1 + YL[ VVourUL) + ¢F.L
I D,L (LIN)
283
Body Bias Considerations for Linear Enhancement-Only Loaded Nl\110S Inverter
20.4
V2</½)
V oL(guess) (V)
VT,L(V)
Io.L (µA)
v,N (V)
0.7
0.8
0.9
0.85
0.86
1.26
1.28
1.30
1.29
1.30
127
122
118
120
120
5.97
5.32
4.82
5.05
5.00
284
Chapter 20/Linear Enhancement-Only Loaded NMOS lnwrtcr
The guess value of V01_ = 0.86 V yields an input of
V 1N = 5 V which is the value of V0 1 ➔ determined
above.
Solution {Input Low Voltage) The numerical
method for finding VII_ is demonstrated in the following table:
20.5 POWER DISSIPATION OF
LINEAR ENHANCEMENT-ONLY
LOADEDNMOS
To determine the power dissipation of a linear enhancement-only loaded NMOS inverter, the DC
currents supplied by VDD for the high and low output
states are first obtained.
V OUT(IL) (V)
(guess)
VT,L(V)
Io.L (µA)
v,L (V)
v,L (V)
4.75
4.76
4.77
4.78
1.79
1.79
1.79
1.80
4.2
4,0
3.8
3.6
1.556
1.547
1.537
1.527
1.532
1.531
1.529
1.528
Output High Current
Supplied = I00 (OH)
In section 20.2 it was seen that N 0 is cutoff in the
output high state (see Table 20.1), With N 0 cutoff,
Ioo(OH) = Io,L(LIN) = In,o(OFF) = 0
The value of V 1L = 1.527 V is accurate to less than a
tenth of a percent. The corresponding output is
VouT(IL) = 4. 78 V.
Solution {Input High Voltage)
The numerical
method for finding V1H is tabulated below. Initial
guesses are shown in the left column and the resulting value in the right column.
V,H(guess) (V)
3,6
3.7
Vou1
(V)
1.25
1.3
VT.L (V)
Io,L (µA)
V,H (V)
1.36
1.37
103
101
3.79
3.70
Output Low Current = I00 (OL)
For the output low state, N 0 is in the linear region
of operation. For the terminal voltages of N 0 for this
state, the expressions of section 20.3 for non-bodybias considerations can be evaluated or the numerically determined values of the previous section may
be used. The current supplied for the output low
state is then obtained by substituting into the linear
drain current expression given by
Thus, V11_1 is 3.7 V.
Solution (Midpoint Voltage) Finally, VM is found
numerically in the following table.
VM (V)
(guess)
VT.L(V)
Io,L (µA)
VM (V)
2.4
2.5
2.6
2.7
1.53
1.54
1.56
1.57
61.7
58.8
55,7
52.7
2.86
2.82
2.77
2.72
Thus, with body bias VM is approximately 2.7 V and
these results differ by less than 10%. Neglecting the
source-to-body bias is acceptable for an approximate
solution.
Average DC Power
Dissipation = P00 (avg)
The average DC power dissipated is now found by
substituting into
Pon (avg) =
l 00 (0H)
+
2
loo(OL) V
no
Dynamic Power Dissipated= P00 (dyn)
As with resistor-loaded NMOS, a significant additional power dissipation for enhancement-only
:20.h
loc1ded NMOS logic circuits occurs during the
switching of logic stc1tes. This contribution tc1kes the
form
Pm)(riyn)
=
285
Linear Enhancemcnt-Onlv Loaded NMOS SPICE SimulJtion
CLvVz)l)
where CL is the total load cc1pacitc1nce c1t the output
of the gate and vis the frequency at which the gate
switches logic states.
Example 20.3 Power Dissipation of
Enhancement-Only Loaded NMOS
(a) Find the average DC power dissipated in the linear enhancement-only loaded NMOS inverter
of Exan1ple 20.2.
(b) Find the dynamic power dissipated for the same
gate. Let CL = 1.5 pF and v = 105 MHz.
Solution (a) For the output low state, the terminal
voltages of N 0 were found in Example 20.2 to be
Vcs.o = ViN(OL) = 5 V
c1nd
pric1te SPICE lc1belings. The SPICE input ClRcuit file
thc1t represents this circuit is JS follows:
Linear E-0 Loaded NMOS
Inverter
VIN 1 D PULSE< □ V 5V □ NS 2NS 2NS
+ SOONS 1US)
VDD 3 D SV
VGG 4 D 10V
-MODEL NMOSFET NMOS(VT0=1
+ KP=20U GAMMA=0-37 PHI=0-6
+ CBD=3-1E-15 CBS=3-1E-15)
MN◊ 2 1 DD NMOSFET W=10U L=SU
MNL 3 4 2 D NMOSFET W=SU L=20U
CL 2 D 1PF
-DC VIND 5 □ -1
-PLOT DC VDS<MNO)
-TRAN 2DNS 2-SUS
-PLOT TRAN V<VIN) VDS<MNO)
-END
The VTC and transient response obtained from simulating this circuit are shown in Figures 20.6a and b,
respectively.
The current dissipated in the output low state is
therefore
10
=
(40µ)
(O 86)2]
[ (5 - 1.1)(0.86) - -·2
!
= 119 µA
3
I 4111--------------i20UM
0 _§UI\II MNL
-
Thus, the average DC power dissipated is
I
J
_
(119µ)
_
I u0 (avg) - - - (5) - 298 µW
2
v-
Solution (b) The dynamic power dissipated is
1
2
Pm)(dy11) = (1.5p)(105M)(5) = 3.94 mW
~
0
~N
~
20.6 LINEAR ENHANCEMENT-ONLY
LOADED NMOS SPICE SIMULATION
Figure 20.5 shows a linear enhancement-only loaded
NMOS inverter with c1 capacitive load with appro-
fl
1
-
-
I
I
1
~
r
1
I
o 10UM
_i_su,,.-MNO CL
0
o
-=-
-:-
:
I
i:
:
.
1PF
I
I
!
~
FIGURE 20.5 Linear Enhancement-only Loaded
NMOS Inverter with Capacitive Load and Appropriate
SPICE Labelings
286
Chapter 20/Linear Enhancement-Only Loaded NMOS Inverter
VIN(V)
5--------4
Your (V)
3
5--1----
2
1- 4
O -t-----+--iL---1-,-~L__---1----_____. t(µs)
0
3
0.25
0.50
0.75
1.00
1.25
YourCV)
...
2
5-
43
0 -+----+------,----f------+------+-----------i. V mCV)
0
1
2
4
3
5
2
I
1 J.______..,
I
0 ,------,---+------+-------,f-------+----------i. t(µs)
0
0.25
0.50
0.75
(a)
FIGURE 20.6 Results of Section 20.6 Linear
Enhancement-only Loaded NMOS Inverter SPICE
1.00
1.25
(b)
Simulation: (a) Voltage transfer characteristic from .DC
sweep, (b) Transient response from .TRAN sweep
CHAPTERZ0PROBLEMS
20.1
20.2
20.3
V 00 =7V
What are the states of N 0 and NL for the linear
enhancement-only loaded NMOS inverter for each
of the VTC critical points Vm1, VOL, V11_, V 111,
and VM.
l
For the NMOS inverter with linear enhancementonly load shown in Figure P20.2, graphically determine the critical voltages Vrn 1, VoL, V,L, V 111 , and
V~,1. Let V1m = 5 V and Vee = 7 V. Use Vr = 1 V
and k' = 20 µA/V 2 for both N 0 and NL, Also, use
(IN/L) 0 = 20µ,m/2µ,m and (IN/L)L = 10µ,m/5µ,m,
Sketch the VTC and determine the noise margins,
(Ignore the body-bias of N,J
For the NMOS inverter with linear enhancementonly load shown in Figure P20,2, analytically determine the critical voltages VoH, VoL, Vn., V11 .i, and
V 00 =5V
I
IL
I
0
lOµm
,--, 5µm NL
I
I
~
I
1---0
FIGURE P20.2
VNCIT
Chapter 20
V, 1• Let V1)[) = 5 V and Vee = 7 V. Use V 1 = 1 V
and k' = 20 µ.A/V 2 for both N 0 and NL· Also, use
(W/L) 0 = 20µ.m/2µ.m and (W/L)L = 10µ.m/5µ.m.
Sketch the VTC and determine the noise margins.
(Ignore the body-bias of N 1 .)
20.4
For the NMOS inverter with linear enhancementonly load shown in Figure P20.4, analyticnlly determine the critical voltages Vrn 1, VoL, V11 _, V1H, and
V:vl· Let vl)D = 5 V and Vee = 7 V. Use Vr = 1 V
and k' = 20 µ.A/V 2 for both N 0 and N 1 . Also, use
(W/L) 0 = 20µ.m/2µ.m and (V\T/L)L = 10µ.m/5µ.m.
Sketch the VTC and determine the noise margins.
Considering the body-bias of N 1 . Use 'J'L = 0.4
V112 and 2</>u. = 0.6 V.
20.5
Repeat Problem 20.2 for (W/L) 0 = 20µ.m/4µ.m.
20.6
Repeat Problem 20.3 for (W/L) 0 = 20µ.m/4µ.m.
VNar
20µm N
2µm 0
FIGURE P20.4
Problems
287
20.7
Repeat Problem 20.4 for (W/L)() = 20µ.m/4µ.m.
20.8
Repeat Problem 20.2 for (W/L) 0 = 100µ.m/2µ.m.
20.9
Repeat Problem 20.3 for (W/L) 0 = 100µ.m/2µ.m.
20.10
Repeat Problem 20.4 for (W/L) 0 = 100µ.m/2µ.m.
20.11
Repeat Problem 20.2 for (W/L)L = 1.
20.12
Repeat Problem 20.3 for (W/L)t_ = 1.
20.13
Repeat Problem 20.4 for (W/L)t. = 1.
20.14
Repeat Problem 20.2 for (W/L)L = 5µ.m/10µ.m.
20.15
Repeat Problem 20.3 for (W/L)t. = 5µ.m/10µ.m.
20.16
Repeat Problem 20.4 for (W/L)L = 5µ.m/10µ.m.
20.17
Find the static power dissipated in the NMOS inverter of Problem 20.3.
20.18
Find the static power dissipated in the NMOS inverter of Problem 20.4.
20.19
Find the static power dissipated in the NMOS inverter of Problem 20.6.
20.20
Find the static power dissipated in the NMOS inverter of Problem 20.7.
20.21
Find the static power dissipated in the NMOS inverter of Problem 20.9.
20.22
Find the static power dissipated in the NMOS inverter of Problem 20.10.
20.23
Find the static power dissipated in the NMOS inverter of Problem 20.12.
20.24
Find the static power dissipated in the NMOS inverter of Problem 20.13.
20.25
Find the static power dissipated in the NMOS inverter of Problem 20.15.
20.26
Find the static power dissipated in the NMOS inverter of Problem 20.16.
21
ENHANCEMENTDEPLETION
LOADED NMOS
INVERTER
In this chapter, the operation of the NMOS inverter
with enhancement-depletion load is described. This is
linear enhancement-only loaded NMOS inverters,
where the load MOSFETs operate only in the satu rated or the linear mode, this type of load operates
in either the saturated or the linear modes of operation. With the gate and source connected, Vcs.L = 0.
Since the threshold voltage of this enhancement -depletion NMOS is negative, we have
an alternate form of the NMOS inverter that uses an
enhancement-depletion MOSFET load device with
gate and source terminals connected. This inverter
has the advantages ofV 0 1.1 = VDo without the second
Vcc supply, as well as a more abrupt VTC transition
region even though the W/L ratio for the output
MOSFET is small. Hence, this type of load is more
widely used in NMOS digital logic circuits than any
of the others. An additional implant is required to
form the channel in the load MOSFET but with advanced fabrication technology, this processing step
is easily accomplished .
Vcs, L = 0 > Vu = -IVu(E - D)I
Hence, the load MOSFET NL is always active. The
region of active operation for NL is determined by
the inequality
Vos. L 2: Vcs. , - VT.L = - VT,L = IVT.L(E - D)I
If this inequality is true, NL operates in saturation,
otherwise NL is in the linear region of operation. As
with the other NMOS inverters, the input is at the
gate of N 0 , V 1N = Vcs. o, the output is at th e drain
of N 0 , and VoUT = VDs,o = VDD - VDS,L·
For V, N < V1 ,0 , N 0 is cutoff and no drain current
conducts in either transistor. Since the drain current
Io, L is zero, NL (which is still active) must be in the
linear region of operation. V0 s. L is obtained by solving the linear drain current expression as follows :
21.1 OPERATION OF
ENHANCEMENT-DEPLETION
LOADED NMOS INVERTER
Figure 21 .la shows a NMOS inverter with an enhancement-depletion N-channel MOSFET as a load
device. Unlike the saturated enhancement-only and
-f
lo,L(LIN) = kL[ (Vcs, L - Vr,LWos,L - -V bs,- L]
2
Tips, Tricks, and Gimmicks
Threshold Voltage of EnhancementDepletion MOSFETs
=0
which gives VDs,L
The threshold voltage VT.N for enhancementdepletion N-channe l MOSFETs is negative :
VT,N(E - D) < 0
= 0. Thus,
Vo11 = Vno - Vos,L = Von
= Negative
Increasing V, N above VT,o initiates drain current
conduction in N 0 (and NL)· Since Vos,o 2: Vcs,o -
288
?.l.?.
289
Graphical Determination of Enhancement-Depletion Nlv!OS Inverter \/TC
YDD
load NMOS has a
body bias of YsnJ. =
Your= YNOT
()
G
~1 ~)~ ' ~
N,(E-D)
-0
Your
WON
k
O
y DS,O
0
(a)
FIGURE 21.1
(b)
Enhancement-depletion Loaded NMOS Inverter: (a) Source-body connected load, (b) With body-bias
VT.o, N 0 is in saturation. As the input is increased
further, the output begins to drop. The form of the
VTC, which is found by equating I1i. 0 (SAT) =
ID,L(LIN), is left as a homework problem. When the
output drops below VDLJ - VT,L, VDs.L becomes large
enough for NL to enter the saturation region of
operation.
Subsequent increasing of the input causes the
output to fall below Vcs,t. - VT,o, forcing N 0 into the
linear region of operation. This gives a VTC of the
form in Figure 21.2b. The following section elaborates further on the VTC and the various states of N 0
and N1,.
This initial qualitative analysis has shown that a
low input gives a high output and vice-versa. The
logical NOT function is again realized. The next two
sections present graphical and analytical methods for
finding the voltage transfer characteristic of an enhancement-depletion loaded NMOS inverter.
21.2 GRAPHICAL DETERMINATION
OF ENHANCEMENT-DEPLETION
NMOS INVERTER VTC
As with the other loaded NMOS inverters, the drain
currents of N 0 and NL are equal and 11),L(LIN) can
be expressed as a function of VDs,L as follows:
2
Io.i(LIN) = kL [ Wcs,L - VT.LWos,L -
-ki[
v ;s,i
l
Vr,1Woo - Vou-r)
Vou1fl
+ Woo 2
The saturation drain current of NL, expressed with
channel-length modulation parameter dependence,
is given by
Io,L (SAT )
= k1. Wcs,L -
2
k1
-_ 2
2
V r,Lf 1
"
Vu_)-(1
+ A1Vns.L)
+ AL Wnll - Vns,o)]
which has a minimal dependence on VDs.u since ,\ 1,
is typically small, in the range 0.01 to 0.1 v- 1 . Hence,
the drain current of Ni, is approximately constant
with respect to VDs,o when NL is operating in saturation.
Figure 21.2a shows an output MOSFET family of
ID,o versus VDs.o characteristics (with Vcs.o as a parameter). The N1, output load curve is also superimposed. The nearly horizontal portion of the load
curve for the two cases is where NL is in saturation.
The sloped portion of the load curve showing a large
dependence on VDs,o is where Ni, is in the linear
region of operation.
290
Chapter 21/Enhancement-Depletion Loaded NMOS Inverter
VOUT (V)
t
V oH=V DD
=5
A
------t:1--....
41
~
0 VOL 1
r'
------. -:-I
I
2
3
dA
4
5
Vm=3V
VIN=2V
V™♦ 1 V
VOUT = VDS,O =
VDD-VDS,L(V)
(a)
FIGURE 21.2 Graphical Determination of
Enhancement-depletion Loaded NMOS Inverter Voltage
Transfer Characteristic: (a) Enhancement-only NMOS ID
versus VDs family of curves with superimposed
enhancement-depletion NMOS load curve, (b) Voltage
transfer characcristic obtained from cutvc intersections
of (a)
To graphically determine the VTC ordered pairs
of 0/cs,o, V05 , 0 ) are read from the intersections of
the output load curve with the family of curves for
N 0 . These points are in turn mapped onto the VDs.o
versus Vcs,o coordinate axes as in Figure 21.2b. The
voltage transfer characteristic is the resulting curve
through these plotted points. The output low voltage, which does not reach 0, is the value of VDs.o
where the output load curve intersects the Vcs,o =
V oH = VDD characteristic.
The operating states of N 0 and NL for each critical point will now be determined by examination of
Figures 21.2a and b. For Vrn 1 (point A), N 0 is cutoff
and NL is operating in the linear region. For V11 ,, N 0
has entered the saturation region of operation and
N1, is still linear. For VM = V1:--: = V0 ur, N 0 is still
saturated and NL has entered the saturation region,
For the point V 1:--; = VrH, N 0 has gone into the linear
region and remains there beyond the Vm point E.
For both V1H and V0 u NL remains in saturation.
These states are summarized in Table 21.1.
TABLE 21.1 States of Transistors
for Enhancement-Depletion Loaded
NMOS Inverter
Critical Point
V01,
V1L
VM
VIH
VoL
Output No
Cutoff
Saturation
Saturation
Linear
Linear
Load NL
Linear
Linear
Saturation
Saturation
Saturation
21.3 CALCULATION OF VTC
CRITICAL POINTS FOR DEPLETION
LOADED NMOS INVERTER
V011 was found in section 21.1 and is repeated here for
convenience
Output High Voltage - VoH
For V1:--: = Vcs,o < V,,o the inverting
transistor N 0
is cutoff and no drain current conducts (in either
transistor). However, NL is operating in the linear
21.3
Calculation of VTC Critical Points for Depletion Loaded NMOS Inverter
region of operation. VDs.L is obtained by solving the
linear drain current expression for 10 .L(LIN) = 0 as
follows:
dVOLrr
dV1N
dVouT
dV1L
=
dlD,O
dVn.
dID,L
dVouT
-1
Separating the derivatives
din,o
dVIL
From this expression, Vns,L
VDS,L
=
0. Since Vmrr
= VDD
and substituting for these derivatives gives
ko(VIL - VT,o) = -ki[VT,L
Vou = Voo
Input Low Voltage= V1L
-1
At the input low voltage, N 0 and NL are in the saturation and linear regions of operation, respectively.
SubstitutingVcs,o = V1L, Vcs,L = 0, and VDs,L = VDD
- VocT into the drain current equations gives
+
(VDD - Vour)l
Rearranging yields
ko
VouTUL) = kL CVn - Vr,d + V T,L + V DD
The input low voltage is defined as the point on the
VTC below V0 H where
dVouT
dVIN
dID,L
dVouT
---
This expression represents the output corresponding
to V11 _. To obtain V1L, another equation is obtained
by equating the drain currents at V1L
or
Determining VDD - VouT from the previous expression yields
and
I1J,L(LIN) = k{ CVcs,L - VT,L)VDS,L - _v_;s_,L]
-kL[ VT,LCVoo - Vow)
+
CVDo - VoLrr?]
2
With ID,o = ID,oCViN) and Io,L = 10 ,L(Vom), equating
differentials of the drain currents yields
dio,oCVJL) = dio,LCVouT)
or
dIDo
dloL
, dV1L = d-V' dVouT
dvIL
OUT
Solving for dV0m/dV1N = dV 0 m/dV 1L and equating
to -1 gives
and substituting into the drain current expression,
we have
292
Chapter 21/Enhancement-Depletion Loaded NMOS Inverter
Collecting like terms of (V11
Vr,o), we have
-
ko + kz,) (V _ V )2 =
( 2
2kL
IL
T,O
all),() dV
aVn1
k1Y}1
2
T,0
v2 T,L -
k~
k k + k2
OL
v2
-
1 V T,Ll1
o1 vc::,
kL
ViL - Vr,o = Ykok1. + k~,
,
Input High Voltage
r7Vi 11
IVul
dVmrr
r7Vou-r
Setting dl 0 ,L/dV0 ur = 0 the equation reduces to
O L
CJ
= Vrn
koVouT
-1
dln,o
aViH
ilVouT
= ko[(Vm
- Vn,) - VouT]
or
Solving for VouT gives
At the input high voltage, N 0 and NL are in the linear
and saturation regions of operation, respectively.
Substituting Vcs,o = V,H, VDs,o = VouT, and Vcs,L
= 0 into the drain current equations yields
[
li,,o(LIN) = ko Wcs,o - Vr,oWos,o -
= ko [ (V111 - Vu,)Vour
al0 ,0
Substituting the derivatives yields
The input high voltage is defined as the point on the
VTC near Vm where
dVouT
dVIN
Vz\.,o]
Vouy(IH)
This is the output voltage corresponding to V,H- To
obtain V 1H, another equation is obtained by equating
the drain currents of the two transistors to yield
2
Vz>uT]
2
In,o(LIN) = h,,L(SAT)
or
VlxlT]
[
ko W111 - V T,o) VouT - - -
and
2
- k1_ v2
T,L
2
Substituting for VouT yields
ol
k l(V
Note that Io,L(SAT) is a constant here and thus dlo,d
dVoUT = 0. However, we will use Io,L = ID,L(VoUT)
which is the functional dependence, when back bias
of NL is accounted for. With ID,o = ID,o(V,N, Vour)
and ID,L = 10 ,1,(VouT), equating differentials of the
drain currents gives
111
_ V
T,o
)(Vu-1 - Vr,o)
2
_ ~ (Vi11
~ Vr,o
rJ
and rearranging, we have
3ko (VII I - V T,O )2 -- k1. v2T,L
8
dlo,o(V111, Vour) = dlo,L(Vow)
or
-1
Rearranging, we have
lk kk1. + k2 /VT,L I
V
dln,L _ _ illo,~
dVmrr
aVouT
r7loo = - __
dlo1,_, + __
r7fr10
_,_
,_
Finally, solving for V,L yields
VIL -- VT,O +
oVouT
dVouT
dVi11
T,l.
0
!~~i~g\t~ ~/u~r~~~~~t of both sides, remembering
V \ V T,L)
1
)2 - _k_1,_
k2
k +~
o
kL
+ -_-- dVow = -d-- dVour
Solving for dVouT/dVu, = dVOL,r/dV,H and equating
to -1 yields
and rearranging yields
V
dlf.),I.
VouT
al/),()
111
or
2
21.3
(Vu 1
V
-
r.u
C1lculation of VfC Critical Points for Depletion Loaded NMOS Inverter
The output low voltage is found by equating
drain currents of the two transistors as follows:
)2 - 4k1 v2
- ku T,L
3
li,. 0 (LIN) =
Taking the square root of both sides gives
&a
21Vnl &
l 0 .1(SAT)
or
IVul
Vm - Vr,o = 2
- kL v2
T,L
2
Finally, solving for Vil, yields
Viu =
V-r,o +
293
Collecting like terms gives a quadratic equation for
V0 1. as
Note that V11 _ and V,H are independent of V1m.
Output Low Voltage = VoL
In the output low state, N 0 and NL are in the linear
and saturation regions of operation, respectively. Assuming this inverter is driven by a similar gate in the
output high state, as in Figure 21.3, the input is V,N
= VoH = VDD· Substituting this, V0 s.o = VoL, and
Vcs.L = 0 into the drain current equations gives
In.o(LIN)
= ko [ CVcs.o -
= ko [Woo
vis.a]
Vr.o)Vos.o - - -
2
- vT,o)VoL -
Vt!L]
2
Since Vm is sufficiently small, the Vf1 L term can be
ignored. This yields
VOL
-
Midpoint Voltage
lw. (SAT ) -- k1 (V cs.L -
2
vr.L)2
=V
M
At the midpoint voltage, where V1N = VoL'T = VM,
N 0 and NL are both in the saturation region of operation. For N 0 , this is verified by considering the
inequality
VDS,O
and
k1.VtL
2koCVDo - Vr.o)
2:
VGS,O
Upon substitutingVcs.o
-- kL v2r.1.
2
VM
2:
VM - Vr, 0
W'LN'
L,L
L
FIGURE 21.3
VT,O
= VDs.o = V~.1, we obtain
V'oo
driving gate
-
load gate
Cascaded Enhancement-depletion Loaded NMOS Inverters for Vm Illustration
294
Chapter 21/Enhancement-Depletion Loaded NMOS Inverter
which is clearly satisfied. Substituting Vcs,o = Vt,, 1,
V 0 5 ,0 = V :vi, and Ycs,L = 0 into the saturation drain
current expressions gives
Solution (Critical Voltages) The critical points
can now be found by direct substitution into the derived expressions to obtain
V 011
V
= 15 V
= 13 +
IL
and
(
=
VM is now found by equating these currents to obtain
Vu 1
ko (VM - VT,O )2 -- kL
2
2
vzT,L
V OLIT(IH)
V
or
2 _
k1,
14.68 l'
=
VT,0 =
ff
Finally, solving for V M, we have
+ IVul
(20µ.)(- 3)
-
2
2(80µ.)[(15) - (1.3)]
= 8.21111V
Solution (Logic Swing) The logical swing is calculated by
IVT,LI
LS= V0 u - V0 1, = (15) - (82.lm)
ff
TW
Solution (Device Transconductance Parameters) The transconductance parameters for both
transistors must first be calculated as follows:
°:) =
=
14.92 V
The transition width is
Example 21.1 VTC Critical Points of
Depletion Loaded NMOS Inverter
Calculate the logic swing, transition width, and the
midpoint voltage for an enhancement-depletion
loaded NMOS inverter. Use V00 = 15 V, VTCi(E-0)
= 1.3 V, VTo(E-D) = -3.2 V, (W/L) 0 = (20µ.m/5µ.m),
and (W/L)L = (10µ.m/10µ.m). Use k' = 20 µ.AN 2 for
both transistors.
ko =
(20µ.)(25
kL
(20µ.)C~:) = 20 µ.
This gives the ratio k 0 /kL = 4.
(3.03) - (1.3)
= 0.865 V
2
VM = (1.3) + l-3\
Taking the square root of both sides yields
k'(~t =
= k'(~\ =
+ (-3.2) + (15)
2
(Vi11 - VT,o) - ko V T,L
VM = VT.o
2.02 V
= (1.3) + 2\-3.2\
OL -
-
(80µ.)2
= Io,L(SAT)
or
VM
(20µ.)l-3.21
\f (80µ.)(20µ.) +
(80µ.)
VmrrUL) = -(- ) [(2.02) - (1.3)]
20µ.
==
l 0 , 0 (SAT)
. )
80 µ. :
2
:2
= Vu 1
-
V1L
= (3.03) - (2.02) = 1.01 V
21.4 BODY BIAS CONSIDERATIONS
FOR ENHANCEMENT-DEPLETION
LOADED NMOS INVERTER
The analysis of the depletion loaded NMOS inverter
of the previous section neglected the body bias on
the load transistor NL. Figure 21.lb shows the depletion loaded NMOS inverter with a body common
to both transistors. The output of the circuit is taken
at the source of NL yielding a body bias of V 51u =
V os,o = VoL:T· With this body bias, threshold voltage
of NL is
V-uCVsB,L = Vos,o = Vom)
= vTo.L + YL(V~v-s1J-.1-._+_2_</J_F-.L - ~ )
= Vrn,1, +
YL(YVos,o + 2</Ju. - ~ )
= VTo,L + YL(YVouT + 2</JF,I. - ~ )
21.4
Body Bias Considerations for Enhancement-Depletion Loaded NMOS Inverter
The procedure for calculating the VTC critical points
considering non-zero V51u is now presented.
295
•
Equate the drain current of NL to the (linear)
drain current of N 0 :
•
Repeat this procedure until V1N is within a
few percent of the V0 H calculated in the last
sub-section (we have assumed this gate is
driven by a similar gate in the output high
state, see Figure 21.4).
Output High Voltage = VoH
The output high voltage is unaffected by the body
bias VsB,L and is still
Output Low Voltage=
VoL
The numerical method for finding V0 L is the same
as that for the saturated enhancement-only loaded
NMOS inverter. The procedure is as follows:
•
Guess a value for VoL (good initial guesses
are about 5% of V00 ).
•
Determine the threshold voltage of NL for
this output:
Vu(VsH,L
•
= Vos,o = Var.)
= Vrn,L + yJv'_V_oL_+_2_<P_F_,L - ~ )
Solve for the (saturation) drain current of N 1•
for this body bias:
10 ,r.(SAT)
k1,
=
2 Wcs,1,
=
2
kL
Input Low Voltage
=V
1L
The numerical method for finding V1L is the same as
that for the linear enhancement-loaded NMOS case
of the previous chapter and is not repeated here.
?
- Vu)-
(O -
Input High Voltage= Vrn
The similar numerical method for finding V111 is as
follows:
V'oo
W'LN'L
L,-L
·----0
vy[N
+
V' our = YoL
+
W' o ,
I
,
1--- ENO V DS,0
'
o
V'as,o
'--------------y- _ _ ,,)
driving gate
FIGURE 21.4
load gate
Cascaded Enhancement-depletion Loaded NMOS Inverters with Body Biases
296
•
Chapter 21/Enhancement-Depletion Loaded NMOS Inverter
Guess a value for V1H (good initial guesses for
V11-1 is the zero substrate bias value which is
approximately h0% of VDI)),
• Determine YouT(IH) from the expression
VouAIH) =
Vi11 -
Vro
2
·
which was obtained in the previous section.
• Determine the threshold voltage of N1, for
this output using
VT,l[VSB,L = Vos,o = Vouy(IH)]
Vm,L
~--~---
+ ')11,(YVouy(IH) + 2</Jr.L
-~)
• Solve for the (saturated) drain current of the
load
Midpoint Voltage - VM
The numerical procedure for finding VM is very similar to that for the saturated enhancement-only
loaded NMOS inverter. The procedure is as follows:
• Guess a value for VM (good initial guesses for
v~I are about 2.5 V).
• Determine the threshold voltage of NL for
this output using
Vns,c, = Vv1)
VTO,L + 'Y1(\i~V-M_+_2<P-,-,L - ~ )
• Calculate the (saturation) drain current of NL
for this threshold voltage as follows
k
k V2
I O,L -_ _f_:_(VCS,/, -VT,L) 2
-~
-
2
2
• Equate ID,L to the (saturated) drain current of
Nu to obtain
• Solve for VM:
• Equate the load drain current to the (linear)
drain current of N 0 as follows
I0 ,0 (LIN) = ko [ Wcs,o - Vr,o)Vos,o - -Vbs,o]
2
• Repeat this procedure until the solved VM is
within a few percent of the guessed V~ 1•
= ko [ (Vi11 - Vr,oWourUH) - VzxrrUH)]
2
• Solve for V111 to obtain
• Repeat this procedure until the solved V11-1 is
within a few percent of the "guessed" Vn-1•
Example 21.2 Enhancement-Depletion
Loaded NMOS Inverter: Body Bias
Considerations for VTC
Calculate the VTC critical points for the enhancement-depletion loaded NMOS inverter of Example
21.1 considering the body bias effect on NL. Use
112
')11, = 0.45 V
and 2¢ l',L = 0.6 V.
Solution (Output High Voltage)
fected by the body bias and is still
As will be seen in the following example, the body
bias of NL has little effect on ViH•
VoH
= 15 V
Vo1-1 is not ef-
21.5
Solution (Output Low Voltage) The numerical
method for finding VOL is demonstrated in the following table:
V 0dguess) (V)
VT,L (V)
Iv,L (µ,A)
VIN (V)
0.080
0.090
0.091
0.092
-3.20
-3.18
-3.17
-3.17
102
101
101
101
17.3
15.3
15.2
15.0
The guess value of VOL = 0.092 V yields an input of
V1N = 15 V, which is the value of VoH determined
above.
Solution (Input Low Voltage)
The numerical
method for finding V1L is demonstrated in the following table:
V ou10L) (V)
(guess)
VT.L (V)
lo,L (µ,A)
VIL (V)
VIL (V)
14.5
14.6
14.7
14.8
-1.80
-1.79
-1.79
-1.78
15.5
12.8
9,8
6.7
1.92
1.86
1.80
1.71
1.70
1.70
1.70
1.70
The value ofV1L = 1.70 Vis accurate within a percent.
The corresponding output is V0 u1 (IL) = 14.8 V.
Solution (Input High Voltage) The numerical
method for finding V1H is tabulated below. Initial
guesses are shown in the left column and the resulting value in the right column.
V1H(guess) (V)
VouT (V)
VT.L(V)
lo,L (µ,A)
V1H (V)
3.10
3.13
3.16
3.17
3.15
3.17
3.18
3.19
-2.68
-2.68
-2.67
-2.67
71.7
71.6
71.5
71.5
3.16
3.17
3.17
3.17
Thus, V1H is seen to be 3.17 V.
Solution (Midpoint Voltage) Finally, VM is found
numerically in the following table.
3.80
3.83
3.86
3.89
VT.L(V)
lv,L (µ,A)
-2.60
-2.60
-2.60
-2.60
67.8
67.7
67.5
67.3
Thus, Vl\,1 is approximately 3.89 V.
297
Enhancement-Depletion Loaded NMOS Power Dissipation
3.90
3.90
3.90
3.90
21.5 ENHANCEMENT-DEPLETION
LOADED NMOS POWER
DISSIPATION
To determine the power dissipation of an enhancement-depletion loaded NMOS inverter, the DC currents supplied by VDD for the high and low output
states are first obtained.
Output High Current
Supplied = I 00 (OH)
For the inverter of Figure 21.1, since N 0 is cutoff for
the output high state (see Table 21.1), we have
IDD(OH) = ID_L(LIN) = ID_o(OFF) = 0
Output Low Current = I 00 (OL)
For the output low state, N0 is in the linear region
of operation. To obtain the voltages of N 0 for this
state, the expressions of section 21.3 for non-bodybias considerations can be evaluated for an approximate solution, or the numerically determined values
of the previous section may be used for a more accurate solution. The current supplied for the output
low state can then be obtained by substituting these
voltages into the linear drain current expression
yielding
IDD(OL)
=
ID,L (SAT)
=
ID,o(LIN)
= ko[Wcs,o - Vr,o)VDs,o -
Vt'·
0
]
Average DC Power
Dissipation P00 (avg)
=
The average DC power dissipated is now obtained
by substituting into
p
(
) _ IDD(OH)
DD avg -
+ IDD(OL) V DD
2
IDD(IO)VDD
=---2
Dynamic Power Dissipated= P00 (dyn)
As with the other NMOS cases, a significant additional power dissipation for enhancement-only
298
Chapter 21/Enhancement-Dcplction Loaded NMOS Inverter
loaded NMOS logic circuits occurs during the
switching of logic states. This contribution takes the
form
Poo(dyn) = CLvV'fw
where CL is the total load capacitance at the output
of the gate and vis the frequency at which the gate
switches logic states.
Exampie 21.3 Power Dissipaiion of
Enhancement-Only Loaded NMOS
(a) Find the average DC power dissipated in the enhancement-depletion loaded NMOS inverter of
Example 21.2.
(b) Find the dynamic power dissipated for the same
gate. Let CL = 0.1 pF and v = 105 MHz.
Solution (a) For the output low state, the terminal
voltages of N 0 were found in Example 21.2 to be
FIGURE 21.5 Enhancement-depletion Loaded NMOS
Inverter with Capacitive Load and Appropriate SPICE
La be lings
Vcs,o = V1N(OL) = 15 V
and
appropriate SPICE labelings. The SPICE input CIRcuit file that represents this circuit is as follows:
VOL= 0.092 V
The current dissipated in the output low state is
therefore
21.6 ENHANCEMENT-DEPLETION
LOADED NMOS SPICE SIMULATION
E-D Loaded NMOS Inverter
VIN 1 D PULSE(OV 5V □ NS 2NS 2NS
+ SOONS 1US)
VDD 3 D DC 5V
,MODEL MEO NMOS(VT0=1 KP=20U
+ GAMMA=0-43 PHI= □ -6 CBD=3,1E+ 15 CBS=3-1E-15)
-MODEL MED NMOS(VT0=-2 KP=20U
+ GAMMA=D-43 PHI=0-6 CBD=3-1E+ 15 CBS=3-1E-15)
MO 2 1 0 D MEO W=20U L=5U
ML 3 2 2 D MED W=5U L=5U
CL 2 D 1PF
-DC VIND 5 0-1
-PLOT DC VDS(MO)
-TRAN 20NS 1-25US
-PLOT TRAN V(VIN) VDS(MO)
-END
Figure 21.5 shows an enhancement-depletion
loaded NMOS inverter with a capacitive load with
The VTC and transient response obtained from simulating this circuit are shown in Figure 21.6a and b.
10 = (80µ,) [ (15 - 1.3)(0.092) -
(O.o; 2)
2
]
= 100 µ,A
The average DC power dissipated is then
(100µ,)
(15)
2
Pn 0 (avg) = -
=
750 µ,W
Solution(b) The dynamic power dissipated is
P00 (dyn) = (0.lp)(105M)(15) 2 = 2.36 111W
ChJpter 21
299
Problems
VJN(V)
15
i
12
Your (V)
9-
A
i
6
15
312T
0
0
9-r
t(µs)
'
0.25
0.50
0.75
1.00
1.25
0.25
0.50
0.75
1.00
1.25
Ymrr(V)
61
15
12 - -
I
3I
9- -
I
oI
0
~► VJN(V)
3
6
9
12
6- -
15
3
t(µs)
0
0
(b)
(a)
FIGURE 21.6 Results of Section 21.6 Enhancementdepletion Loaded NMOS Inverter SPICE Simulation:
(a) Voltage transfer characteristic from .DC sweep,
(b) Transient response from .TRAN sweep
CHAPTER21PROBLEMS
21.1
What arc the states of N 0 and NL for the enhancement-depletion loaded NMOS inverter for each of
the VTC critical points V01 1, Vm, V1L, V111 , and VM·
21.2
For the NMOS inverter with enhancement-depletion load shown in Figure P21.2, graphically determine the critical voltages V011 , Vm, V1L, V111 , and
VM. Let VDD = 5 V and use k' = 20 µ,A/\/2 for both
N 0 and NL. Also, use Vr,o = 1 V, (W/L)u = 20µ,m/
5µ,m, Vu = -3 V, and (W/L)L = 10µ,m/5µ,m.
Sketch the VTC and determine the noise margins.
(Ignore the body-bias of N1.,)
21.3
For the NMOS inverter with enhancement-depletion load shown in Figure P21.2, analytically determine the critical voltages V011 , VoL, V1L, V111 , and
lOµm N
-5µm
L
VNCYr
•7risµm "
yr.
11
FIGURE P21.2
20µmN
300
Chapter 21/Enhancement-Depletion Loaded NMOS Inverter
V0,1• Let V 1m = 5 V. Use k' = 20 µA/V 2 for both
N 0 and NL. Also, use VT,o = 1 V, (W/L) 0 = 20µm/
5µm, Vu = -3 V, and (W/L)1, = 10µm/5µm.
Sketch the VI'C and determine the noise margins.
(Ignore the body-bias of NL,)
21.4
For the NMOS inverter with saturated enhancement-only load shown in Figure P21.4, analytically
determine the critical voltages VoH, Vrn., V11 ,, V1H,
and Vrv1. Let V00 = 5 V, Use k' = 20 µA/V 2 for both
lOµm N
5µm L
lo,o
V ,,
m
~
= l0,1.
i
_j11I
.. ··
7
FIGURE P21.4
N" and N1_. Also, use V 1,u = 1 V, (W/L)u = 20µm/
5µm, Vu = -3 V, and (W/L)1_ = 10µm/5µm.
Sketch the VI'C and determine the noise margins,
considering the body-bias of N1,. Use 'YL = 0.4
V112 and 2¢F,L = 0.6 V.
21.5
Repeat Problem 21.2 for VDo = 10 V.
21.6
Repeat Problem 21.3 for Vno = 10 V.
21.7
Repeat Problem 21.4 for VDo = 10 V.
21.8
Repeat Problem 21.2 for (W/L) 0 = 40J,Lm/5µm.
21.9
Repeat Problem 21.3 for (W/L)n = 40µm/5µm.
21.10
Repeat Problem 21.4 for (W/L)o = 40J.Lm/5µm.
21.11
Find the average static power dissipated for the
NMOS inverter of Problem 21.3.
21.12
Find the static power dissipated for the NMOS inverter of Problem 21.4.
21.13
Find the static power dissipated for the NMOS inverter of Problem 21.6.
21.14
Find the static power dissipated for the NMOS inverter of Problem 21. 7.
21.15
Find the static power dissipated for the NMOS inverter of Problem 21.9.
21.16
Find the static power dissipated for the NMOS inverter of Problem 21.10,
VNm:
20µmN
Sµm o
NMOS GATES
The previous four chapters described four NMOS
logic families and their implementation in inverter
form. Each family is based upon an N-channel output MOSFET with source terminal at ground, gate
terminal as inverter input, drain terminal as inverter
output and a load device placed between the inverter
output and voltage supply VDD· The load device was
either a resistor or the drain-to-source channel of
another N-channel MOSFET. While the analytical
solutions are mathematically complex, qualitative
descriptions are straightforward and the realization
of the logical NOT function for each load is easily
understood (as discussed in the first section of each
of these chapters). The present chapter is dedicated
to describing the design of multi-input NMOS logical gates such as NANDs, NORs, more complex
AND-OR-inverts (AOis), and other special function
logic gates. Each of these more complex logic gates
has a single load device that is between the logic gate
output and VDD in the same fashion as the NMOS
inverters. Furthermore, the single output transistor
N 0 is replaced with multiple N-channel MOSFETs
with their drain-source channels either in parallel
(NOR) or series (NAND) or both (AOis). The gate
terminal of each non-load N-channel MOSFET
serves as a separate logical gate input.
Y
Tips, Tricks, and Gimmicks
N-Channel MOSFET
Symbol Shorthand
In section 16.3, it is mentioned that a MOSFET
is a physically symmetric device. Hence, the
terminals at each end of the channel (the drain
and the source) can be interchanged (see Figure 16.5). Figure 22.1 shows the N-channel
MOSFET circuit symbol and cross-section that
are used to explore this source-drain symmetry. Indeed, the drain and source are not de-
301
fined until bias voltages are applied. The drain
is defined as the channel terminal with the
higher voltage and the source is the channel
terminal with the lower voltage.
In describing the schematic circuitry of
NMOS integrated circuits, it is convenient to
develop a shorthand circuit symbol. The core
implications to be represented in this shorthand symbol are the following:
1.
the physical symmetry explained above,
and
2.
all MOSFETs in a single NMOS integrated
circuit have the same substrate (this was
mentioned in each of the preceding NMOS
logic family chapters with the body bias
analysis of the load devices)
These two concepts are represented in the
shorthand symbol of Figure 22.2 for the enhancement-only N-channel MOSFET. The
dashed line representing the enhanced channel
in the standard symbol has been replaced with
a solid line. The body terminal has been removed and is assumed to be at ground, which
is the substrate potential of an NMOS integrated circuit.
There is also a shorthand symbol for the
enhancement-depletion N-channel MOSFET.
Figure 22.3 shows the regular symbol along
with the shorthand symbol. The shorthand
symbol indicates the implanted channel with a
thick line and the body terminal is again removed and assumed to be at ground.
These shorthand symbols will be used
throughout this chapter in the schematics of
the multi-input NMOS gates to be described.
This is the usual symbol convention for NMOS
(and CMOS) transistor circuits with multiple
N-channel MOSFETs. Note that the shorthand
symbols are much easier to draw and are extremely convenient in large circuits.
302
Chapter 22/NMOS Gates
drain or
source
9
_11_J
gate o-- -- -
1
:--------a body (P type substrate)
7
L- -
P substrate
N
source
or drain
(b)
(a)
FIGURE 22.1 N-channel Enhancement-only
MOSFETs are Physically Symmetric; the channel end at
the high er potential is the drain, and the channel end at
th e lower potential is the source: (a) Circuit symbol,
(b) Device cross section
drain or
source
drain or
source
,,,,,.
;>
source
or drain
body implied
at ground
~
N
source
or drain
(b)
(a)
enhancement channel is replaced with a solid line; body
terminal is removed and assumed at ground
FIGURE 22.2 N-channel Enhancement-only MOSFET
Symbol Shorthand: dashed line representing
drain or
source
drain or
source
body implied
at ground
~
;>
o--l
N
N -=6
source
or drain
(a)
FIGURE 22.3 N-channel Enhancement-depletion
MOSFET Symbol Shorthand: solid line representing
channel is replaced with a thick solid line (thus
source
or drain
(b)
differentiating it from the enhancement-only shorthand
symbol Figure 22.2b); body terminal is removed and
assumed at ground
22.1
generic pull-up device
NMOS NOR Gate
A~D
B~
~--~--~-<)
VA o-~j
{!NA 6"~~
s
303
-F
VNOR
parallel NMOS pull-down
c____.--~-------'
-:-
(a)
FIGURE 22.4
22.1
(b)
Two-input NMOS NOR Gate: (a) With generic pull-up load, (b) Circuit symbol
NMOS NOR GATE
NMOS NOR Gate Circuitry
The general NMOS inverter (with an output
N-channel MOSFET and a resistor or MOSFET load)
can be augmented to perform the logical NOR function by placing additional output NMOS transistors
in parallel with the output N-channel MOSFET. Figure 22.4a shows a two input NMOS NOR gate with
a generic load. This is the simplest case and the logic
circuit symbol is shown in Figure 22.4b. Both NMOS
transistors have their drain-to-source channels connected from the output to ground. Each of the output
N-channel MOSFETs should have the same channel
width W and length L to achieve the same value of
VoL regardless of which input is high (as explained
later).
Figure 22.5 shows the most practical of the
NMOS logic family NOR gates, the enhancementdepletion loaded NMOS NOR gate. It consists of two
output N-channel MOSFETs connected in parallel
and a single enhancement-depletion N-channel
MOSFET load.
where VL(OH) is the voltage across the load for the
output high state. For all NMOS logic families except
the saturated enhancement-only loaded NMOS,
VL(OH) = 0 V and VoH = Voo,
Output Low Voltage
= VoL
If any input is high, a highly conductive path from
the output to ground is formed by enhancement of
a drain-to-source channel. Therefore, any input high
results in an output low voltage. Thus, the logical
NOR function is realized by the generic loaded circuit of Figure 22.4a. The parallel output NMOS
structure is referred to as a parallel pull-down, since
it is constructed of several possible pull-down paths
from the output to ground.
Output High Voltage = VoH
If both inputs to the NMOS NOR gate of Figure
22.4a (or 22.5) are low, both output transistors (NA
and N8 ) will be cutoff. Thus, the output high voltage
is unchanged from that of the NMOS inverter with
VL(OH) and
-:-
FIGURE 22.5 Two-input Enhancement-depletion
Loaded NMOS NOR Gate
304
Chapter 22/NMOS Gates
The output low voltage for an NMOS inverter
was found to be inversely dependent upon the device
transconductance parameter k0 (and ultimately on
W 0 /L 0 ) of the output transistor. For example, in section 18.3, V01. for the resistor-loaded NMOS inverter
is obtained as
V0 1,(R loaded)
MOSfET with
given by
c1
device transconductance par.:imcter
k0
= k'(W11 + W 8 )
LA
L8
Since the output low voltage is inversely proportional
to k0 , the output low voltage will be reduced for an
NMOS NOR gate with two inputs high and thus
= - - - -Voo
---koRL(VDD - VT,o) + l
V0 L(two NOR inputs high) < V01 (inverter)
In section 21.3, the enhancement-depletion loaded
!'J~.10S inverter has an output lovv voltogc (neglect-
Input Low and High Voltages
ing the body bias) given by
= VIL
& Vrn
k1,Vi:L
V0 [,(E-D loaded) = k (
_ V )
2 o Voo
T,o
The input low and high voltages for the NMOS logic
family NOR gates are the same as those for the corresponding inverters.
As we shall see, the output low voltage for the
NMOS NOR gate is dependent upon the number of
input voltages that are high.
Additional Inputs
Single Input Voltage High
If a single input voltage is high, the situation is analogous to the single input inverter with a high input
voltage, and the drain current drawn by the corresponding output MOSFET is the same as that for the
inverter and is given by
Vm(single NOR input high) = V0 L(inverter)
More inputs can be added by simply including more
parallel output N-channel MOSFETs, as shown in
Figure 22.6. Since the output high voltage is not degraded by additional inputs and the output low voltage is actually improved by multiple inputs high,
there is no limit to the number of inputs an NMOS
NOR gate can have.
Both Input Voltages High
If two inputs are high, then both output MOSFETs
conduct drain current. If the input voltages are the
same and the process transconductance parameters
k' are the same for both output MOSFETs (as is the
case in typical NMOS circuits), then the output transistors can be considered to act as a single N-channel
Example 22.1 Output Low Voltage of NMOS
NOR Gate
Determine and compare the output low voltages for
the resistor loaded NMOS NOR gate in Figure 22.7
with one and two inputs high. Also, use k(1 =
q
I
11;~N,
v, 0
-1 [:~:
N,
~:-ii: :~-~~'- I[~·='.-·_ ·•· I~=--o
X,•
v_
FIGURE 22.6 Adding Inputs to an NMOS NOR Gate: add a NMOS transistor to the parallel pull-down for each
additional input
22.2
NMOS NAND Gate
305
Solution (Two Inputs High) With two inputs
high, the effective device transconductance for the
double NMOS is
( ,
WoB)
. ) = k/J (Wo1\
-- + -
k0 two mputs high
Loi\
Loa
= (20µ,)(10µ, + 10µ,)
5µ,
= soµ,
5µ,
A
v2
The output low voltage for two inputs high is then
FIGURE 22.7 Two-input Resistor Loaded NMOS
NOR Gate for Example 22.1
20 µ,AN 2, WA/LA = Wti/LG = 10µ,m/5µ,m, and VT =
1 V for both N-channel output MOSFETs.
Solution (Single Input High) The output NMOS
device transconductance is
k = k:{:j =
0
0
(20µ,)(~ : ) = 40
µ,;
Then, using the equation for the output low voltage
for the resistor-loaded NMOS inverter yields
Vm(R loaded) =
(5)
(4 0µ,)( 50k)(5 _ 1)
= 556 mV
This is the value for one input high.
+
1
V(x(two inputs high)
= (S0µ,)( 5 0k)71- 1) + 1
= 294 mV
Hence, the output low voltage for two inputs high is
slightly over half the output low voltage for a single
input high.
22.2
NMOS NAND GATE
NMOS NAND Gate Circuitry
NAND gates can also be easily constructed using
NMOS circuitry. Figure 22.Sa shows an NMOS
NAND gate with a generic load and two inputs
(where more than two inputs are also possible). The
9
I,•looil ~ I ;,
1
generic pull-up device
_)
~
A-""
VNAND
B--~F
series NMOS pull-down
(a)
FIGURE 22.8
Two-input NMOS NANO Gate: (a) With generic load, (b) Circuit symbol
(b)
306
Chapter 22/NMOS Gates
load NMOS NL and
Q
~
D
G
_,,.,,,.. stacked
B
~ NL(E-D)
S'
input
NMOS N 8 have
body bias of Vsa.L =
VoUT = VNor and
v••;Il = vS;Il = v 0 ,A,
respectively
D
v.
D
0--~
v o-~
B
V,
I ,~e w.
N
-r:;;-•
I'
41
I~
o----1 ~:N,
VA
B
I
s
i
(a)
(b)
FIGURE 22.9 Two-input Enhancement-depletion
Loaded NMOS NAND Gate: (a) Circuit drawn with
shorthand symbols, (b) Circuit drawn with MOSFET
body terminals included and depicting body biases
NAND function is realized in NMOS by placing the
drain-to-source channels of multiple NMOS output
transistors in series instead of parallel as in the
NMOS NOR gate. The gate terminal of each parallel
co.nnected N-channel output MOSFET is used as a
NAND logic gate input. Figure 22.86 shows the logic
symbol for this gate.
Figure 22.9a shows the most practical of the
NMOS family NAND gates, the enhancementdepletion loaded NMOS NAND gate. For the two
input case, two N-channel MOSFETs are connected
with their drain-to-source channels in series and a
single load device is used. Generally, all enhancement-only NMOS transistors in the input stack will
have the same channel width W and length L.
path to ground. Hence, regardless of the input state
of VB, since there is no conductive path from the output to ground, the NAND gate must be in the output
high state.
Output High Voltage
= Vott
An output high voltage is obtained from the NMOS
NAND gates of Figures 22.Sa and 22.9a for either
input being low. To demonstrate this, consider both
inputs in the input low state separately.
VA Low, NA Cutoff
If the bottom NMOS NA has a low gate terminal
voltage VA = Vcs,A = low, then NA will be cutoff and
the source terminal of NB will have no conductive
VB Low, NB Cutoff
We next examine the case of VA high and VB low.
With VA = Vcs,A in the input high state, NA will be
active and a highly conductive path from the source
of NB to ground exists. However, section 17.2 shows
that MOSFETs with very small drain currents (1 0 <
1 µA) also have small drain-to-source voltages
(V 05 < 10 mV). Since Io.A will be zero with NB cutoff
the source of NB is at a virtual ground. Thus, with NA
of Figure 22.9a active, NB and the load now act like
an inverter. If the input VB is in the input low state,
then NB is cutoff and no pull-down path exists from
the output to the virtual ground of Ys,B = Vo,A = 0 V.
Hence, an input low state for N 8 also results in an
output high state.
Thus, either input low results in an output high
state, with an output voltage unchanged from that
of the NMOS inverter given by
Vm1
= Voo -
VL(OH)
Note that both inputs low also yields the output high
state. Showing that the output low state results when
22.2
both inputs me high then verifies the logical NAND
function.
ko
Body Bias of Nn
Before analyzing the output low voltage case of the
NMOS NAND gate, note that the source voltage of
NB is in fact above ground by approximately the nondegraded output low voltage of the inverter. As a
result, there is a body bias present on N 8 as depicted
in Figure 22.96 (which shows the schematic of the
enhancement-depletion loaded NMOS NAND gate
with explicit body terminals and common substrate).
This always results in an increased threshold voltage
for NB given by
VT,ll(VSB,B
> O) =
VT,/\(VSB,1\
= O) + 1.
As a practical matter, the difference in threshold voltage will be negligible and this gate can be analyzed
ignoring this deviation.
Analysis of NMOS NAND Output Low Voltage
For the NMOS NOR gate, it was found that VoL for
a particular NMOS family is unchanged for a single
input high and smaller for multiple inputs high. For
the NMOS NAND gate, the output low voltage is
degraded (increased) from the inverter case resulting
from a contribution from each NMOS transistor in
the stacked pull-down configuration. This is the result
of the series drain-to-source channels contributing
to a physically longer pull-down path from the output to ground. A fairly accurate approximation is to
simply add the lengths of the channels since the
channel widths will generally be the same (WA W 8
= W 0 ) and the process transconductances will be the
same (kA = kB = k0 ). The output low voltage can
307
then be calculated using the expression derived for
the inverter and with a device transconductance of
Output Low State - VoL
The existence of the output low state for both inputs
high is now easily shown. Again, considering Figure
22.9a, with VA= Vcs.A high, NA is active and a highly
conductive path from the source of N 8 to ground
exists. Tirns, the source of NB is at virtual ground, as
already discussed. With V8 = Vcs.s + Vos.A high, a
highly conductive path from the output to the virtual
ground of Vs,B = VD.A = 0 exists. Hence, with both
inputs high, NA and N 8 are both active, a highly conductive path from the output to ground exists, and
the NAND gate is in the output low state. Thus, the
logic gate in Figure 22.9a realizes the logical NAND
operation.
NMOS NANO Gate
=
k~cA:°iJ
Since this lowers the device transconductance from
that of a single NMOS transistor and the output low
voltage is inversely dependent on k 0 , the output low
voltage for a NMOS NAND gate is greater than the
output low voltage of an inverter or
VoL (NANO)
>
V oL (inverter)
As a result, a greater channel width is generally
needed for both NA and Nn to compensate for this
degradation in performance. Because of this drawback, NMOS NOR gates are used in place of NMOS
NAND gates, wherever possible.
Input Low and High Voltages
& Vrn
= VIL
The input low and high voltages for the NMOS logic
family inverters are all dependent upon k0 (except
for V1L of the saturated enhancement-only loaded
inverter). The combined k0 used above to show an
increase in Vot. can also be used to show changes in
V1L and V,H for each of the logic families.
Adding More Inputs
NMOS NAND gates can accommodate more than
two inputs by simply adding more N-channel
MOSFETs to the stacked NMOS pull-down portion
of the NAND gate as shown in Figure 22.10. As a
practical matter, NMOS NAND gates with more
than three inputs are generally not used because
each additional input requires further increasing of
the channel width of each N-channel MOSFET in
the pull-down stack in order to maintain reasonable
Vm.
Example 22.2
NAND Gate
Output Low Voltage of NMOS
Determine the channel width of the output transistors NA and NB in the two input resistor loaded
NMOS NAND gate of Figure 22.11. Design VoL to
be the same as that found for the NOR gate of Example 22.1 with only one input high. Use the same
values VDD = 5 V, RL = 50 kO, k' = 20 µAN 2, L =
308
Chapter 22/NMOS GJtes
FIGURE 22.11 Two-input Resistor Loaded NMOS
NAND Gate for Example 22.2
FIGURE 22.10 Adding Inputs to a NMOS NAND
Gate: add an NMOS transistor to the series pull-down
for each additional input.
5 1,Lm, and VT = 1 V as in Example 22.1 for both
MOSFETs.
Solution
The output low voltage for a resistor
loaded inverter from section 18.3 is
Substituting the combined transconductance k0
k 0(W0 /2L 0 ) and solving for W 0 yields
2L 0 ( ~ : :
Wo =
,
-
1) = - - - - - - -1]-
k0R1(VDD - VT)
= 20
2(5/.l{-(si-~,-n) -
(201,L)(S0k)[(S) - (1)]
/,l/11
This is twice the width of the parallel N-channel
MOSFETs in Example 22.1.
22.3
NMOS OR AND AND GATES
OR and AND gates are obtained using NMOS logic
families by simply connecting inverters to the out-
puts of NOR and NAND gates, respectively. Figures
22.12 and 22.13 show NMOS OR and AND gates
with generic loads. Note that the intermediate NOR
and NAND outputs can be used to drive logic inputs
other than their corresponding inverters. This is useful for applications requiring complementary logic
signals. Figures 22.12b and 22.136 show the two-input logic circuit symbols for these gates.
22.4 NMOS COMPLEX LOGIC
GATES (AOis AND OAis)
The previous sections in this chapter showed that
parallel combinations of N-channel MOSFETs from
output to ground provide a NORing of inputs, with
the possibility of inverting the NOR to obtain OR.
Series NMOS transistors from output to ground provide NANDing of inputs, with AND obtained with
an additional inverter. Complex AND-OR-invert
logic gates can be constructed by connecting NMOS
transistors in series and parallel combinations within
the same circuit. Figure 22.14a shows such a gate.
Input ANDing Branches
Two parallel branches of two series NMOS transistors are shown in Figure 22.14a. If both inputs of a
given branch are high simultaneously, then a highly
conductive path from the output to ground exists.
That is, a pull-down path exists through NA and N 13
if V,\ AND V11 are high. Alternatively, a pull-down
22.3
rn
'
··················
V,.
t'
NMOS OR and AND Gates
TL ...... · · · · · · · · · · · · · · · · · · · · · · · •· · · · · · · · ·
t~N~ Y~ -1 c·~N& ... Yt--f {:N,
....
J
1
Au(a)
B
F=A+B
···· F=A+B
(b)
FIGURE 22.12 NMOS OR/Nor Gate: (a) NOR ied inverter, (b) Two·input circuit symbol indicating both OR and
NOR iunctions arc available
(a)
(b)
FIGURE 22.13 NMOS AND/NANO Gate: (a) NANO icd inverter, (b) Circuit symbol indicating both AND and
NAt'\JD functions arc available
309
310
Chapter 22/NMOS Gates
0
A
D
YSN"
v.~
vA
o--a
,r-
Ve
NA
7
VAOI = VAVB + VeVD
A
B
D----l___)
° j ~Ne
I
~
VAANDV.
'---~
VeANDV0
(a)
FIGURE 22.14
F=AB +CD
C
11
(b)
Four-input NMOS AND-OR-invert Gate: (a) Circuit schematic with generic pull-up load, (b) Logic
schematic
path exists through Ne and N 0 if Ve AND VD are
both high.
The AND-OR-invert node can also be used to drive
other gates to provide complementary logic signals
when needed.
Output is NO Ring of the ANDings
Section 22.1 shows that parallel N-channel
MOSFETs can be used to provide a NO Ring of input
voltages, and an analogous situation is present here.
The output of the gate shown in Figure 22.14a is the
NO Ring of the logic performed by each branch, VA
AND V8 for the left branch and Ve AND VO for the
right branch. Thus, this gate performs the logic function
VA01 = (VA AND Vii) NOR
= NOT[(VA AND V8 )
We AND V0)
OR We AND Vo)]
Recipe for Other Complex NMOS
Logic Gates
As shown in this and the previous sections, complex
logic functions can be realized using NMOS logic
families by using the following general NMOS circuit
design connections:
1.
ANDing of signals is performed by series NMOS
pull-down branches. That is, placing the drainto-source channels of multiple N-channel
MOSFETs in series from the output to ground
using the gate terminal of each NMOS transistor
as a signal input
2.
ORing of signals, including ORing of ANDed
signals, is performed by parallel placement of
branches between the output and ground
3.
If inverting of the ORing is not desired, an
inverter is connected to the output of the ANDOR-inverting logic circuitry (the NOTed ANDOR node can be used as a separate output to
drive other logic gates)
=AB+ CD
Non-Inveriing AND-OR Gaies
If an AND-OR gate without the complement is desired, an additional inverter is added to the output,
as was the case when obtaining OR and AND gates
from NOR and NAND gates. Figure 22.15a shows
an AND-OR gate that performs the logic function
VAo = (VA AND Vii) OR
=AB+ CD
We AND
Vo)
22.4
NMOS Complex Logic Gates (AOls and OA!s)
311
(a)
D
CBA-
i---,
F=AB+CD
F=AB+CD
(b)
FIGURE 22.15 NMOS Ai'\JD-OR Gate with
Enhancement-depletion Loads: (a) AOI fed inverter,
(b) Circuit symbol indicating both AO and AOI functions
Example 22.3 NMOS Complex
AND-OR-Invert Gate
MOSFET will be needed to accommodate the signal
V0 . These connections are shown in Figure 22.16b.
Design an enhancement-depletion loaded NMOS
logic gate that provides the two logic functions
Solution (ORing) The ORing of the signals is performed by placing the series ANDing branches and
the single transistor branch in parallel. The ANDOR-invert logic function is available at the common
top of the parallel branches. The inverting logical
function NOT[(VA AND V8 AND Ve) OR VD OR (VE
AND VF)] is performed by the circuitry outside of the
shaded box of Figure 22.16b and available at the output labeled VAOI·
F =ABC+ D + EF
and the complement
F =ABC+ D + EF
The logic symbol for such a gate is shown in Figure
22.16a.
Solution (ANDing Branches)
Two series
branches will be required to perform the logical
ANDing. One branch with three series N-channel
MOSFETs to perform VA AND Vil AND Ve and a
branch with two series NMOS transistors to perform
VE AND VF. A branch with a single N-channel
are available
Solution (Inverting of ADiing) To provide an
AND-ORing of the signals an additional inverter is
needed to complement the AND-OR-invert signal
provided by the parallel ORing branches. This is
shown in the shaded box of Figure 22.166. The logical function 0/A AND VB AND Ve) OR V0 OR (VE
AND VF) is available at the output labeled VAO·
312
Chapter 22/NMOS Gates
AB
C
D------<
E --
F-
F=ABC+D+EF
'--- F =ABC+ D + EF
(a)
Yun
V,.ANDV$ANDVc
(b)
FIGURE 22.16 Six-input Complex NMOS AND-OR-invert/AND-OR Gate of Example 22.3: (a) Circuit with
enhancement-depletion load, (b) Circuit symbol
More complex logic functions can be realized by
embedded parallel and series combinations of
NMOS transistors as shown in the following
example.
Example 22.4
Gate
NMOS Super Complex Logic
What logic function is performed by the NMOS circuit of Figure 22.17a?
Solution The NMOS circuit of Figure 22.17a shows
parallel combinations of N-channel MOSFETs
within the main series branches. Each parallel combination of NMOS transistors performs a logical ORing. Therefore, the parallel NJ\ and N 8 perform the
logic V,\ OR VB, Ne and ND perform the logic Ve OR
VD, and NF and Ne perform the logic Vr OR Ve. That
is, a low impedance conducting path exists between
the source and drain of each parallel combination for
one or the other (or both) inputs high.
In Figure 22.17a, the series combination of the
parallel NJ\ and NB and the parallel Ne and N 0 performs the logic (VJ\ OR VB) AND (Ve OR VD). Similarly, the logic performed by the branch containing
NE, Nr, and Ne performs the logic VE AND (VF OR
Ve;). The parallel combinations of the main branches
22.5
NMOS XNOR/XOR Logic Gates
313
Your
(a)
F
E~----1,...__.,,.
-- F =(A+ B)(C + D) + E(F + G)
D
c~
B
A(b)
FIGURE 22.17 Seven-input Super Complex NMOS Logic Gate of Example 22.4: (a) Circuit with an enhancementdepletion load, (b) Circuit symbol
then performs a NORing of the individual branch
logic states and VoUT is given by
Vour
= [(V;1 OR Va) AND We OR
Vo)]
NOR [V[ AND (VF OR Ve)]
As a practical matter, no path from the output to
ground should exceed conduction through three
N-channel MOSFETs. This is because Vm becomes
unacceptably degraded as discussed in section 22.2
on NAND gates.
= NOT([(V;1 OR V8 ) AND We OR V0 )]
OR [VE AND (VF OR Ve)]}
Hence, the logic function is
22.5
NMOS XNOR/XOR
LOGIC GATES
F = (A + B)(C + D) + E(F + G)
The circuit symbol for this gate is shown in Figure
22.176.
Exclusive NOR/OR gates are easily obtainable using
NMOS circuitry. Figure 22.18a shows an NMOS
XNOR/XOR with an enhancement-depletion load.
314
Chapter 22/NMOS Gates
Voo
:jQ~xoR
~
(a)
FIGURE 22.18
XNOR
(b)
Enhancement-depletion Loaded NMOS XNOR/XOR Gate
The MOSFETs labeled NxJ\ and Nx 13 perform the
XORing logical operation. Note that neither NXJ\ or
Nx13 have sources connected directly to ground. The
source of NXJ\ is connected to the input VB and the
source of Nx 8 is connected to the VA input. We shall
begin by verifying the XNOR output.
Both Inputs Low
With both inputs low, the gate-source voltage of
both NxA and Nx 8 are insufficient to turn either
NMOSFET on. With NXJ\ and NXB both cutoff, the
VXNoR output is high.
Both Inputs High
With both inputs high, the gate-source voltages of
both NxA and Nxll are again insufficient to turn either
on and the VXNoR output is again high.
VA = High and VB == Low
With VA high and V8 low, the gate voltage of NxA is
high relative to its source and NXJ\ is active. With NxA
active a highly conductive path exists between the
VxNoR output and the V13 input. Since V13 is low when
NxA is on, the conductive path from VxNOR through
the drain-to-source channel of NXJ\ is a pull-down
path and VxNoR is in the output low state.
VA = Low and Vn = High
With VA low and V8 high, a similar situation exists.
The gate voltage of NXB is high relative to its source
and NXB is active. A pull-down path from the VxNOR
output to the V,\ input exists and the VxNoR output
is again in the output low state.
With both inputs high or both inputs low, the
output Vx:--:oR of the gate of Figure 22.18a is in the
output high state. When a single input is high and
the other low, the output is low. Thus, the exclusive
NOR function is realized for the VxNoR output.
NMOS XOR Gate
The XOR logic function is obtained from NMOS circuitry by simply feeding the XNOR output into an
inverter stage as shown in the shaded block in Figure
22.18a. Figure 22.186 displays the logic symbol for
this gate.
Example 22.5 NMOS XNORIXOR
SPICE Simulation
Perform a SPICE simulation of the NMOS gate of
Figure 22.18a to verify the XNOR and XOR functions. Use VDD = 5 V and the MOSFET models used
in section 21.6.
Solution Figure 22.19 shows the XNOR/XOR gate
of Figure 22.18a with appropriate SPICE labelings.
The SPICE input CIRcuit file for this gate is as follows:
22.5
i--~~~T
Y
NMOS XNOR/XOR Logic Gates
315
4
DC 5V
n• O
4
31
1
►]!SM~ MNDLX
3
-::-
-----0
<l------~-1_.
'-~_o 10UMMNXA
I
,-
5
l5UM
2
VXOR
3
-::-
I':110UM
5UI\/I MNI
0
3
~---1--~---2----J
-::-
I
o 10UM MNX:B
1=;-isuM
11 -::-
VXNOR
-::-
FIGURE 22.19 Enhancement-depletion Loaded
NMOS XNOR/XOR Gate of Figure 22.18a with
Appropriate SPICE Labelings for Example 22.5 SPICE
Simulation
*Enhancement-Depletion Loaded
NMOS
*XNOR/XOR gate
VINA 1 D PULSE(OV 5V □ NS 2NS
+ 2NS 25ONS 5OONS)
VINB 2 D PULSE< □ V 5V □ NS 2NS
+ 2NS 5OONS 1US)
VDD 4 D DC 5V
ures 22.20. Examining these plots, the XNOR and
XOR logical functions are clearly realized.
-MODEL MEO NMOS(VTO=1-3 KP=2DU
GAMMA=D-43 PHI=O-6
CBD=3-1E-15 CBS=3-1E-15)
-MODEL MED NMOS<VTO=-3-2
+ KP=2OU + GAMMA=D-43 PHI= □ -6
+ CBD=3-1E-15 CBS=3-1E-15)
MNDLX 4 3 3 D MED W=1OU L=1OU
MNXA 3 1 2 D MEO W=1DU L=5U
MNXB 3 2 1 D MEO W=1OU L=SU
MNDLI 4 5 5 D MED W=1DU L=1OU
MNI 5 3 DD MEO W=1OU L=5U
-TRAN 1DNS 1.2us
-PLOT TRAN VS<MNDLX) VD<MNI)
-END
+
+
Y
Tips, Tricks, and Gimmicks
Saturated Enhancement-Only
Loaded NMOS Inverter
The following section on NMOS Schmitt triggers presents an NMOS logic gate that embodies a saturated enhancement-only loaded
NMOS inverter as a sub-circuit. For convenience, this circuit is repeated here in Figure
22.21a. The voltage transfer characteristic for
this inverter is shown in Figure 22.21b.
The output high voltage for this inverter,
used in the following analysis and is given by
Vou
= Voo - Vu(Vss,L = VouT)
where the threshold voltage including body
bias is
VT,L(Vsa,L = VouT)
The transient responses for VxNoR and YxoR obtained from this SPICE simulation are shown in Fig-
= v rn,L +
rJvVOL/T + 2</>F,L
-
~)
316
Chapter 22/NMOS Gates
VmlV)
T
5
4 -
Hysteresis and Schmitt Triggers
32
100
1----+-----1~--+---+--. t(µs)
0.25
0.50 0.75
1.00 1.25
VvmB(V)
5-----4
3
1-
-+--0
In the following section, a type of logic circuit
is described that has a different voltage transfer
characteristic for the output high-to-low and
low-to-/1igh transitions. Unlike the logic circuits
described previously, the output high-to-low
and low-to-high transitions occur at different
input voltages. This phenonwnon is known as
hysteresis and the voltage transfer characteristic exhibits a "hysteresis loop."
Trip Voltnges
2-O
Tips, Tricks, and Gimmicks
0.25
----+----+--+0.50
0.75
1.00
--+--
► t(µs)
1.25
V XNOR(V)
5---4-
Figure 22.22a shows a pair of input and inverting output waveforms that demonstrate
hysteresis. Examining these waveforms, it is
seen that the output experiences a high-to-low
transition only when a rising input voltage initiallv exceeds
32
1 0-+---+'-----+----+------,~--+------. t(µs)
0
0.25
0.50
0.75
1.00
1.25
Yxoa(V)
5-'
4-
such as at tin1e t 5 .
The voltages V1D and V1u are referred to as
trip voltages and in order for hysteresis to occur, the condition
321
0
0
Examples are shown at times t2 and tK in Figure
22.22a.
Furthermore, the output experiences a
low-to-high transition when a falling input initially drops below
0.25
I
I
I
I
0.50
0.75
1
I
1.00
t(µs)
1.25
is required.
FIGURE 22.20 Results of Example 22.5 SPICE
Simulation of Enhancement-depletion Loaded NMOS
XNOR/XOR Gate
22.6
NMOS SCHMITT TRIGGERS
This section presents an NMOS circuit that exhibits the
characteristic of hysteresis explained in the preceding
Tips, Tricks, and Gimmicks box.
Good for Cleaning up Noisy Signals
Considering Figure 22.22a again, note that at
times t1, t 1,, and t7, the input rises above V 1L: but
not above Vm and the output does not change
state. Likewise, at times t3 and t4 , the input falls
below Vm but not below V1u and the output
does not change. Therefore, observing that Vi:,
is extremely noisy, whereas Vrn.:T is not, we
obesrve that a circuit exhibiting hysteresis is excellent for cleaning up noisy signals. Even the
spikes that occur at times t 1, t6 , and t 7 are not
sufficient to change the output.
22.6
Voltage Transfer Characteristic of Inverter
with Hysteresis
Figure 22.226 displays the voltage transfer
characteristic for a digital logic inverter circuit
exhibiting hysteresis. This VTC indicates a
high-to-low output transition at an input voltage higher than that at which the output Iowto-high transition occurs. Note the familiar
hysteresis "loop."
NMOS Schmitt Triggers
317
subscript shall be discussed lTlO!Ttentarily. Note that
the feedback device N 1 and the stacked input
MOSFET N 0 have a common source. Since Nr- and
N 0 have a common source, they have the same body
bias effect on their respective threshold voltages.
The circuit symbol for the Schmitt inverter is
shown in Figure 22.236. The symbol is that of a normal inverter with a hysteresis loop indicated inside
the syn,bol.
Schmitt Triggers
Analysis
Circuits that exhibit hysteresis are referred to
as Schmitt Triggers.
The output voltage of the circuit of Figure 22.23a is
taken at the source of the load device NL and is
therefore
Circuit
Output High Voltage == V011
Figure 22.23a shows an NMOS Schmitt inverter.
The input of this circuit is connected to dual stacked
NMOS devices labeled N 1 and N 0 . As with other
transistor loaded NMOS digital circuits, the output
is taken from the source of the load NMOS. An enhancement-only NMOS device Nr- is used in a
source-follower configuration to feedback the output
voltage to the common point Ysw between the
stacked input devices. The significance of the "SEO"
With V1N low, both N 1 and N 0 are cutoff. Since ID,L
= ID,o = 0, the drain-to-source voltage of the active
NL is VDs.L = 0 and the output voltage is
Vour = Vnn - 0 =
Vi)/) =
Vrn1
Saturated Enhancement-Only Loaded NMOS
Inverter Sub-Circuit
Note that with VoL:T = VoD, the drain and gate of
NF are both at Vey = VD,F = Vm,- As long as VoL'T
Your (V)
Yoo·
load NMOS has a
body bias of Ysa.L =
Your= YNar
Na of Figure 22.23
turns on
Your
+
WON
Ln O
0
y DS,O
--+ --f-~- --+ --. Yn-,(Y)
Yrn
(a)
Vm
Yoo
(b)
FIGURE 22.21 Saturated Enhancement-only Loaded NMOS Inverter: (a) Circuit showing body bias of load device, (b)
Voltage transfer characteristic
318
Chapter 22/NMOS Gates
Vm(V)
input rises above V m
Vm
----input high-to-low tHp point--------~,
'
'
:
'
-~j------j--t,
t,
-
t,
YouiV)
--►
t.
·1
t
t,
input drops below V ru
----l
t,
(a)
-
j~► t
t,,
Votrr (V)
Output low-to-high transition
,,----- Output high-to-low transition
~
t
t
t
(b)
FIGURE 22.22 (a) Input and inverting output voltage
waveforms for a circuit exhibiting hysteresis, (b) Voltage
transfer characteristic of a circuit exhibiting hysteresis; in
both (a) and (b) the output high-to-low and low-to-high
transitions occur at a different input voltage
:?.:?..6
NMOS Schmitt Triggers
VOUT
IN
-G>o---
319
OUT
-:-
(a)
(c)
VOUT (V)
YoH
= V DD
ir---~------,
Output high-to-low transition
i
.i
i
..
' _.------- Output Iow-to-hih
g transition
Vru
(d)
FIGURE 22.23 NMOS Schmitt Inverter: (a) Circuit,
(b) Circuit symbol, (c) Voltage transfer characteristic
exhibiting hysteresis: output high-to-low transition
occurs at V10; output low-to-high transition occurs at V,u
= V00 and the input is low enough to keep N 0 in
the cutoff mode, NF and N 1 resemble the saturated
enhancement-only loaded NMOS inverter presented and analyzed in Chapter 19. The node labeled
Ysrn is the "output" of this "NMOS inverter subcircuit."
In the preceding Tips, Tricks, and Gimmicks box,
the output high voltage of the saturated enhancement-only loaded NMOS inverter was obtained. Revising that expression corresponding to Figure 22.23
yields
Vsw(OH) = Voo - VT,F(VSB,F)
where VsB,F = VOUT
320
Chapter 22/NMOS Gates
The output high voltage is then found by iterntion as discussed in section 19.4 and demonstrated
in Example 19.2.
As VrN is increased above VT and N 1 turns on, N 1
and Ni: continue to act as a saturated enhancementonly loaded NMOS inverter as long as N 0 remains
cutoff. Prior to N 0 entering active operation, the
voltage Ysw follows the voltage transfer characteristic of the saturated enhancement-only loaded
NMOS inverter shown in Figure 22.21b.
Output High-to-Low Trip Voitage
=
+
Vr,o(VsB - Vsw)
Find Vu, from
V1,1(Vs1u) = Vrn
+ 'Yr(YV;w + 2</Jr.r - \l2cp1,1)
Find V11) from
•
Vsi-:o = Vw
Find Vsw from
Vs1:o
This voltage is found by equating the drain currents
of Nr(LIN) and NF(SAT) as follows:
lv, 1(LIN)
•
=Vw
The input voltage at which N 0 turns on is given by
V,N
• Guess a value for Vs 1 u (a good initial guess
is about 30% of V11 11)
= Ia,F(SAT)
•
= Vm -
Vry
Repeat this procedure until the calculated
values of Vsrn is within a few percent of the
initial guessed value of Vsw
Output Low Voltage
or
Substituting Ycs, 1 = Vil), VDs, 1 = Ysrn, Ycs,F
- Vsrn, and VT,J = VTo gives
= Vim
k1 [ (VID - VnJ) Vsw - -V~w]
2
kr
=2
(V[)o - Vs10 - V.1,1.)2
where
Vu(Vss.r) = V To + y,( YVsw + 2</Jr,r - ~ )
Solving the equated drain current expression for Vm
yields
As V1:-,; is increased beyond Vil), the output drops
abruptly. \A/hen YouT is brought low enough, NF will
cutoff. At this point N 1, N 0 , and NL act as a two input
NAND gate with the inputs connected together. In
section 21.3, the output low voltage of an enhancement-depletion loaded NMOS inverter was approximated as
k1V2i.1
Vo1=-----2k_,;(V,1n - Vu,)
where the body bias of the load device was neglected. The transconductance k, is the "effective
transconductance" of the stacked N 1 and N 0 devices
which can be approximated as
k- = k' W,
:>
kr
Vsw
V,v = --'--- (Voo - Vsw - Vn-) 2 + - - + Vro
2kiVsw
2
The voltage V10 was stated as being the minimum
input voltage necessary to turn on N 0 . Therefore, the
expression
v,N = Vro =
VsEO
+
V T,O
must also be considered. Substituting VT,o
solving for YsEo gives
VsEo
=
= Vu, and
Vm - VT,f
Vw Iterative Process
From the preceding analysis, the trip voltage Vm is
found using the following iterative process:
2L 1
if the sizes of N 1 and N 0 are the same.
Output Low-to-High Trip Voltage
=Vw
In the output-low state, YuUT is low enough to cutoff
NF. With NF cutoff, the NMOS Schmitt inverter of
Figure 22.23a undergoing a high-to-low input transition acts without the influence of the feedback device. Thus, the output low-to-high transition has the
form of the enhancement-depletion NMOS inverter
voltage transfer characteristic presented in Figure
21.2b. The output low-to-high trip voltage can therefore be approximated as the input high voltage V1H
of the enhancement-depletion loaded NMOS inverter presented in section 21.3:
22.6
/.
-,- =
I~
3,cs
V, 11 = Vrn + 21Vu
Example 22.6 NMOS Schmitt Trigger
Trip Voltages
Find the trip voltages for the NMOS Schmitt trigger of Figure 22.23a with Vnn = 5 V. Use k' =
20 µ,AN 2, YF = 0.45 v 112, 2¢ F,F = o.6 v.
Solution (Output High-to-Low Trip Voltage VwJ
The device transconductance parameters for NF and
N 1\ are
=
k'
Wr
T;
=
321
V, 11
where ks is found from the expression given in the
previous sub-section.
k1
NMOS Schmitt Triggers
(50µ,)
A
(20µ,) ( µ,) = 200 µ, V 2
5
where the body bias effect on the load device was
ignored. (See section 21.4 for the numerical procedure used to calculate V,H considering the load device body bias.)
Design of NMOS Schmitt Trigger
Examining the numerical results used to calculate VID
in the previous example, VGs, 1 = Vm = 2.09 V and
Yns. 1 = Vsrn = 3.47. The input NMOS N 1 is therefore
in the linear mode of operation, since Vns, 1 < VGs, 1
- Vn, As a first order design approximation, we will
assume that N 1 is at the edge of saturation and its
drain current is therefore given by
_ k1
2
Io/EOS) Wcs,1 - VT)
2
Setting the edge of saturation N 1 drain current equal
to the saturation drain current of NF yields
The numerical method for finding V,n is demonstrated in the following table:
V 5 w(guess) (V)
Vu(V)
VID(V)
VsEo (V)
2.0
2.1
2.08
2.07
1.38
1.40
1.39
1.39
3.65
3.41
3.45
3.47
2.27
2.01
2.06
2.09
The guess values of V sw(guess) = 2.08 and 2.07 V
both yield calculated values of V sEo within 1% of the
guessed value. The output high-to-low trip voltage
is therefore in the range of 3.45 to 3.47 V, or
Vw = 3.46 V
Solution (Output Low-to-High Trip Voltage VwJ
The device transconductance parameter for NL is
and by substitution
k1
2 Wes.I
Substituting VGs, 1
VT gives
k1
2 Wm -
(10µ,)
ks
A
= (20µ,) 2 (Sµ,) = 20 µ, V 2
The output low-to-high trip voltage is now obtained
by direct substitution as
=
= kr
2
(
Vm and VGs.F
VT)
2 _
-
?
V1Y
Vcs,F -
=
V00
-
YID +
kr (
2
Voo - Vm)
2
Multiplying both sides of this expression by 2/kF and
taking the positive square root yields
If
Ww -
VT) = Voo - Vm
and collecting like terms, we have
(1 +
The effective device transconductance of the stacked
input N-channel MOSFETs is
?
- VT)-
If)
Vw = Voo +
Finally, solving for Vm gives
If
VT
322
Chapter 22/NMOS Gates
Thus, with the edge of saturation of N 1 approximation, V10 is a function of the ratio of k1/kF and ultimately a function of the ratio
and canceling k', we have
as will be shown in the next sub-section.
Design of Output High-to-Low == Vw
Solving the above expression for kifkF gives
k1 =
kF
('vDD Vio -
Vw)'
VT
2
Note that the output low-to-high voltage is dependent on the size ratio of the load NMOS and
input NMOS devices. The output high-to-low trip
voltage Vm was found to be dependent upon the size
ratio of N 1 and NF. Thus, the trip voltage Yiu and Vm
are designed independently of each other.
k' W1
L1
k' WF
LF
and cancelling k', we have
1
:
WF
= (Voo -
Vio)
2
Vw - VT
LF
This is a design relation for the NMOS Schmitt trigger. By substituting' the desired output high-to-low
trip voltage, supply voltage, and the enhancementonly NMOS threshold voltage, the ratio of sizes of
the input and feedback NMOS devices Ni and NF are
determined.
Design of Output Low-to-High Trip
Voltage== Vw
Solving the expression for Yiu in the previous section
for kiJks yields
Assuming that Ni and N 0 are the same size, ks
ki/2 = k0 /2 giving
=
Example 22.7 NMOS Schmitt Trigger Design
Design an NMOS Schmitt trigger to have trip voltages of Vm = 4 V and V1u = 2 V. Use V00 = 5 V,
VT,! = Yr,o = Vr,F = 1 V, Vr,L = -1 V, and k' =
20 J.LAN 2 . Also, use a minimum gate width of
W(min) = 5 J.Lm and a minimum gate length of L =
5 J.Lm for all MOSFETs.
Solution (Output Low-to-High Trip Voltages)
Subtituting values into the expression derived for Yiu
design gives
WdLL = ~ [(2) - (1)]
WFILF
2
2(-1)
2
3
8
Assuming the minimum size is used for the load device
The size of the N 1 and N 0 devices are therefore
W1 = W0 =
LI
LO
~
(5J.Ll11) = 13.3}.Lm
3 5J.Ll11
5J.Ll11
Solution (Output High-to-Low Trip Voltages)
Substituting values into the design expression for V1u
gives
22.7
2
(5) - (4)]
[ (4)
(1)
1
9
Thus, the size of the feedback NMOS needs to be 9
times the size of N 1 determined previously and thus
Wp =
Lp
22. 7
=
9(13.31mz)
5J.Lm
120J,Lm
5J.Lm
NMOS TRANSMISSION GATES
N-Channel MOSFETs as Conductive
Circuit Elements
Chapters 17 through 21 introduced NMOS inverter
circuits in which a N-channel MOSFET (labeled N 0 )
was placed between the output and ground. The circuit for such an inverter is shown in Figure 22.24a.
Gate Voltage High -,> Highly
Conductive Channel
When the input gate voltage of the NMOS device
N 0 is high, as in Figure 22.24a, the active NMOS
device provides a highly conductive channel between
the output and ground. In essence, the active NMOS
"transfers" the ground voltage to the output.
L
NMOS Transmission Gates
Gate Voltage Low
as Open Circuit
-,>
323
NMOS Acts
When the gate voltage of the NMOS device is low
as in Figure 22.24b, the output is separated from
ground by the equivalent open circuit of the cutoff
NMOS device.
NMOS Device Acts as a Switch
The output NMOS device N 0 of the NMOS inverter
circuits can be viewed as a switch with the gate voltage acting as the "ON/OFF toggle". When the gate
voltage is high as in Figure 22.24a, the NMOS switch
is on and the output is connected to ground. When
the gate voltage is low as in Figure 22.24b, the
NMOS switch is ojf and an open circuit exists between the output and ground.
NMOS Transmission Gate
The preceding qualitative analysis suggests that an
N-channel MOSFET can be used to conditionally
transfer a driving logic voltage from one side of an
NMOS channel to the other. Figure 22.25a displays
two NMOS inverters with a single N-channel
MOSFET NT placed between them. The first inverter
output is connected to one end of NT and the other
channel end of Nr is connected to the input of the
second inverter. The gate voltage of Nr is labeled VEN
and is an enable input.
t
generic pull-up device
I~ I
A ---0
D
;--()~
I
-()~
VIN = V DD
0---~1
[ N0
1/
~
active NMOS device
provide~
a
highly
conductive path between
VoUT and ground
(a)
FIGURE 22.24 In An NMOS Inverter, An N-channel
MOSFET Conditionally Provides a Conductive Path From
_J
V!NJ low o
I
L __ 7
N0
cutoff NMOS device
separates output and
ground by an open
✓ circuit
(b)
Output to Ground: (a) Active N 0 connects output to
ground, (b) Cutoff N 0 separates output from ground
324
Chapter 22/NMOS Gates
transmission gate NMOS device
V'our
(a)
active NMOS device provides a highly
conductive path between Vour and V'IN
V'oo
V'our= VIN
VEN= Yoo
voltage Vour is transfered to V'IN
(b)
FIGURE 22.25 (a) N -channel MOSFET used as a
transmission gate between two inverters: (b) With
VEN = V00, the highly conductive channel of NT
" transfers" Vm JT to v;N
Gate Voltage High - Highly
Conductive Channel
Gate Voltage Low - NMOS Acts
as Open Circuit
In Figure 22.256, the enable input voltage VEN is
high. As in Figure 22.24a, the highly conductive
channel of the active NT transfers the driving voltage
Vmrr to the input v;N· This results in VoUT = v,Nas
labeled.
Figure 22.25c shows the circuit configuration with
low. In this case, NT is cutoff and the input
v;N is isolated from VOUT by the cutoff NT. Thus, the
input terminal to Ne') is disconnected and v;N is float ing.
VEN
=
22.7
NMOS Transmission Cates
325
cutoff NMOS device seperates
Vour and V'IN by an open circuit
V'oo
V'our = undefined
V'IN is undriven and "floating"
(c)
FIGURE 22.25 (continued)
(c) With VEN = low, a cutoff N-r separates Vom and
NMOS Transmission (Pass) Gates
The circuit of Figure 22.25 demonstrates a simple application of NMOS switches. NMOS devices can be
placed between two nodes and the two nodes can
be conditionally connected by a gate enable voltage
VEN. NMOS switches are traditionally referred to as
transmission gates or pass gates.
v;N
this case, N1c is active and N-ri\J N18, and Nrn are
cutoff. The inverter le output voltage VouTC = VINc
is therefore transferred to the input of IMux• The voltage VINc is reinverted through IMux and the multiplexor output is VMux = VINc• Similar results are o_btained by bringing another enable voltage high with
all others low. Hence, this circuit clearly acts as a
multiplexor.
Multiplexor Realization with NMOS
Transmission Gates
Figure 22.26a shows a practical application of NMOS
transmission gates. Four input voltages VINAi VINB,
VINc, and VIND are fed into separate inverters Ii\J 113,
10 and I0 . Each inverter output is connected to a
separate NMOS transmission gate NTA, Nrn, N10 or
Nrn, The output side of the NMOS transmission
gates are all connected to the input of a~ invert~r
labeled IMux• This circuit acts as a multiplexor 1f
one and only one of the enabling inputs VENJ\J
V ENB, VENO or VEND is high and the other three are
low.
Figure 22.26b shows the situation where VENC is
high and the other three enable inputs are low. In
Example 22.8
Gate Array
NMOS Transmission
For the NMOS transmission gate array of Figure
22.27, what enabling conditions are necessary to
transfer each input to the output?
Solution Examining Figure 22.27, the input V1 is
transferred to the output when the enable lines VAl
Ve, and VF are high. V2 is transferred to the output
when V8 and V0 are high. VoUT = V3 when Ve., VE,
and VF are high. Vou-r = V4 when the VA, VB, and VE
enable lines are high. Finally, the V5 input is transferred to VoUT when Vc and VD are high.
326
Chapter 22/NMOS Gates
I,
V!NA
(>
·······I»····
VrNA
(aJ
output of I,: is transferred to tbe ~ of lu1.,-x
IA
.. · .. •···.
Vw,._C-
V=slow
(b)
FIGURE 22.26 NMOS Transmission Gates Used in a
Multiplexor: (a) NMOS multiplexor with four inputs, four
enable lines, and one output, (b) With VENc = Vrm and
the other three enable lines low, NTc "transfers" the
output of le to the input of IMux and VMux = V1Nc
Chapter 22
FIGURE 22.27
Problems
327
NMOS Transmission Gate Array of Example 22.8
CHAPTER22PROBLEMS
22.1
Draw a four input NMOS NOR gate with a saturated enhancement-only load.
22.2
Draw a five input linear enhancement-only loaded
NOR gate.
22.3
Design a three input enhancement-depletion
loaded NMOS NOR gate with a single input high
output low voltage of
22.4
Vm(single intput high) = 0.5 V
Use RL
22.5
V01 _(singlc input high) = 0.08 V
Use VDI> = 5 V, Yeo = 1 V for the output transistors, Vr,L = -1 V, and k' = 20 JLA/V 2 for all transistors. Use any reasonable channel length for the
output transistors.
VDD
Repeat Problem 22.3 for a resistor loaded NMOS
NOR gate with a single input high output low voltage of
= 100 kn
Calculate the output low voltage of the NMOS
NOR gate of Figure P22.5 with
(a) one input high
(b) two inputs high
(c) three inputs high
(d) four inputs high
(e) five inputs high
=5 V
?
I
~~N,
wi,,nN
Jµiii I
-::-
FIGURE P22.5
328
Chapter 22/NMOS Gates
L1
FIGURE P22.9
Use V1 , 0 = 1 V for each of the output transistors,
Vu = -1 V for the load transistor, and k' = 20
µAN 2 for all transistors,
22.6
Repeat Problem 22,5 fork' = 30 µA/V 2 •
22.7
Calculate the static power dissipated for each part
of Problem 22.5.
22.8
Repeat Problem 22.7 fork' = 30 µA/V 2 .
22.9
Calculate the output low voltage of the NMOS
NOR gate of Figure P22.9 with
(a) one input high
(b) two inputs high
(c) three inputs high
(d) four inputs high
(e) five inputs high
Use V1 = 1 V and k = 20 µA/V 2 for all MOSFETs.
22.10
22.11
Repeat Problem 22.9 fork = 30 µA/V 2 .
Draw a two input saturated enhancement-only
loaded NMOS NAND gate.
FIGURE P22.13
22.12
Draw a three input linear enhancement-only
loaded NMOS NAND gate.
22.13
Calculate the output low voltage for the NMOS
NAND gate of Figure P22.13. Use V1 , 0 = 1 V for
each stacked pull-down MOSFET, Vu= -1 V for
the loaded MOSFET, and k' = 20 µA/V 2 for all
transistors. Also, use (W/L) 0 = lOµm/Sµm for
each stacked NMOS and (W/L)L = 5µ,m/Sµm for
the load NMOS.
22.14
Repeat Problem 22.13 fork'
22.15
Calculate the static power dissipation for the
NAND gate of Problem 22.13.
= 30 µA/V 2 •
Calculate the output low voltage for the NMOS
NAND gate of Figure P22.16. Use Vr = 1 V and k'
= 20 µA/V 2 for all transistors. Also, (W/L) 0
10µm/5µm and (W/L)L = 5µ,m/Sµm.
22.17 Repeat Problem 22.16 fork' = 30 µA/V 2 •
22.16
22.18
Design a two input enhancement-depletion loaded
FIGURE P22.16
Chwpter 22
Problems
329
Yam=?
_ _ _ ________j____~------~1-----o
I
FIGURE PZZ.21
FIGURE PZZ.23
NMOS NAND gate with an output low voltage of
Vm = 0.05 V. Use Vr.o = 1 V for the output transistors, V 1.L = -1 V, and k' = 20 µ,A/V'- for all
transistors. Use any reasonable channel length for
the output transistors.
22.19
Repeat Problem 22.18 for a three input NAND gate
and an output low voltage of Vm = 0.1 V.
22.20
(a) Design a two-input enhancement-depiction
loaded NMOS AND gate to have an output
low voltage of V0 L = 0.09 V. Use V 1, 0 = 1 V
for the output transistors, Vu. = -1 V, and
k' = 20 µ,A/V 2 for all transistors. Use VDo = 5
V and any reasonable channel length for the
output transistors.
(b) Repeat part (a) for a three input AND gate. Is
there a difference?
22.21
What logic function is performed by the NMOS
FIGURE PZZ.24
complex logic gate in Figure P22.21? Draw the circuit symbol for this logic gate.
22.22
Modify the gate of Figure P22.21 to provide the
inversion of the function it currently performs.
Draw the circuit symbol for this logic gate.
22.23
What logic function is performed by the NMOS
complex logic gate in Figure P22.23? Draw the circuit symbol for this logic gate.
22.24
What logic function is performed by the NMOS
complex logic gate in Figure P22.24? Draw the circuit symbol for this logic gate.
22.25
Modify the logic circuit of Figure P22.21 to perform
the logic function
F =AB+ C
+ DE
Draw the circuit symbol for this logic gate.
330
Chapter 22/NMOS Gates
l~~Nu
I
:J1:t
I
-
I
I
I jcv,ITT,=?
I
-b
u,
FIGURE PZZ.31
22.26
Modify the logic circuit of Figure P22.23 to perform
the logic function
F =ABC+ DE+ F
Draw the circuit symbol for this logic gate.
22.27
complex logic circuit of Figure P22.31? Compare
with the logic gate of Figure 22.18 of section 22.5.
22.32
Repeat Problem 22.31 for the circut of Figure
P22.32.
22.33
Design an NMOS complex logic circuit that performs the logical function
Modify the logic circuit of Figure P22.24 to perform
the logic function
F = AB + CD + E + FGH
F =A+ BC+ DEF
and draw the circuit symbol for this logic gate. (Design for logic only, don't design the W/L ratios)
Draw the circuit symbol for this logic gate.
22.28
Modify the logic circuit of Figure P22.21 to perform
the logic functions
22.34
Design an NMOS complex logic circuit that performs the logical functions
F = AB + CEF + D + GH
F = ABC + D + EFG + H
and
and
F = AB + CEF + D + GH
F = ABC + D + EFG + H
Draw the circuit symbol for this logic gate.
22.29
Modify the logic circuit of Figure P22.23 to perform
the logic function
and draw the circuit symbol for this logic gate. (Design for logic only, don't design the W/L ratios)
22.35
F = ABC + DEF + GH + I
Design an NMOS complex logic circuit that performs the logical functions
F = ABC + DEF + GH + IJK
Draw the circuit symbol for this logic gate.
22.30
and
Modify the logic circuit of Figure P22.24 to perform
the logic functions
F = ABC + DEF + GH + IJK
F = AG + BCH + DE + FI + J
and draw the circuit symbol for this logic gate. (Design for logic only, don't design the W/L ratios)
and
F = AG + BCH + DE + FI + J
Draw the circuit symbol for this logic gate.
22.31
What logic function is performed by the NMOS
22.36
What logic function is performed by the digital
logic circuit of Figure P22.36?
22.37
What logic function is performed by the digital
logic circuit of Figure P22.37?
Chapter 22
Problems
331
VaUT=?
FIGURE P22.32
~----:9
viD
~·
u------iI
~-1I
VA
o~-1
f--------,
Nae
\
~ lj
N"
I
__r--~-----'
1
VoUT = ?
N0 A
t
FIGURE P22.36
VaUT =?
FIGURE P22.37
FIGURE P22.38
332
Chapter 22/NMOS Gates
22.38
What logic function is performed by the digital
logic circuit of Figure P22.38?
22.39
What logic function is performed by the digital circuit of Figure P22.39? Draw the circuit symbol for
this logic gate.
22.40
22.41
and
F=
Draw the circuit symbol for this logic gate.
22.42
What logic function is performed by the digital circuit of Figure P22.40? Draw the circuit symbol for
this logic gate.
F
Modify the circuit of Figure P22.39 so that it performs the logic functions
22.43
=
Modify the circuit of Figure P22.40 so that it performs the logic function
(AH + B)(C+ D + £) + (F + I+]) + (G + K)
and draw the circuit symbol for this logic gate.
F = (A + B)C + D(E + F) + (G + H)(J + J)
Design an NMOS complex logic circuit that performs the logical functions
F = (A + B)(C + D)(E + f) + G(H + J)(J + K)
FIGURE PZZ.39
I
FIGURE PZZ.40
(A + B)C + D(E + F) + (G + H)(J +])
Chapter 22
Problems
and
F=
(A
+ B)(C + D)(E + F) + G(H + I)(] + K)
Draw the circuit symbol for this logic gate. (Design
for logic only, don't design the W/L ratios)
22.44
F = (AB + CD)E + F + (G + H + I)(]K + L)
VA
I
O
Draw the circuit symbol for this logic gate. (Design
for logic only, don't design the W/L ratios)
22.45
c-~~V-=1
I[
Design an NMOS complex logic circuit that performs the logical function
NA2
Lj~
What logic function is performed by the NMOS
logic circuit of Figure P22.45? Is there any redundant logic in this circuit?
~LN,
FIGURE P22.46
FIGURE P22.45
FIGURE P22.47
~ - - - - -~r--0
~(NK
FIGURE P22.48
Your= ?
333
334
Chapter 22/NMOS Gates
0
~tN1
'------~~____J
~ !~No 'Lj
Lj
FIGURE P22.49
FIGURE P22.50
Chapter 22
Problems
335
-::-
FIGURE P22.51
v,r~-=-~
-::-
FIGURE P22.52
22.46
Repeat Problem 22.45 for the circuit of Figure
P22.46.
22.47
What logic function is performed by the NMOS
logic circuit of Figure P22.47? Compare with the
logic gate of Figure 22.18 of section 22.5.
22.48
What logic function is performed by the NMOS
complex logic circuit of Figure P22.48? Draw the
circuit symbol for this logic gate.
22.49
What logic function is performed by the NMOS
complex logic circuit of Figure P22.49? Draw the
circuit symbol for this logic gate.
22.50
Is there anything inherently wrong with the
NMOS logic circuit of Figure P22.50?
22.51
Repeat Problem 22.50 for the circuit of Figure
P22.51.
22.52
What logic function is performed by the NMOS
complex logic circuit of Figure P22.52?
23
CMOS INVERTER
Co111p/c111c11tnry MOS, or CMOS, is a logic family that
uses N-channe l and P-channel · MOSFETs in
matched or co111plc111('11tary pairs. In this fan1 ily, a
T
Tips, Tricks, and Gimmicks
P-Channel MOSFETs
P-channel MOSfET is used as J pull-up load device
for J N-chJnnel MOSFET pull -down device. As will
be seen in this chJpter, the NMOS transistor cJn just
as appropriately be viewed as a pull -down loJd de vice for the PMOS pull -up trnnsistor. Presently,
CMOS is the 111ost widely used digital circuit tech nology because it possesses the lowest power dissi pation Jnd the highest packing density in co111pari son with all the other logic families.
The low power dissipation of CMOS has made
battery powe red wrist watches and hand-held cJlculators possible, JS wel l as recently developed notebook computers. Virtually all 111odern microproces sors are manufactured using CMOS technology
including Intel's 80286, 80386, and 80486 and Motorola's 68010, 68020, 68030, and 68040. Earlier versions of Intel's 8086 and 8088 have been reprocessed
in CMOS technology.
This chapter introduces the CMOS logic family
in its inverter form. A qualitative description of the
CMOS inverter operation is presented along with a
discussion of the operational modes of each transistor during excursion of the voltage transfer characteristic. Graphical and analytical analyses of the voltage transfer characteristic are then given. Power
dissipation, transient response, and fan-out analyses
are then discussed. A SPICE simulation of the CMOS
inverter is presented to corroborate the results of the
analytical analyses. The chapter concludes with a
discussion of a parasitic operational state of the
CMOS inverter called latch -up and input protection
circuitry included on -chip at the input pins of CMOS
1Cs.
The equations gove rning th e operation of Pchannel MOSFETs (PMOS) will be required in
this chapter :.md are now listed.
Regio11s of Operation
The positive direction of 11> is out of the drain
for PMOS and VT.I' is negative for enhance ment-only PMOS. Also, since all terminal voltages arc reversed for PMOS, the subscripts on
th e voltages are reversed in the PMOS operc1tion equations (this also necessitates replacing
V1 _1, with - Vu,)
• Cutoff= VsG,I'
:S
-vii'
10 .l'(OFF)
•
=0
Linear= Vsc. 1, 2 -V 11 , and VsD.I'
:S
Vsc. 1'
+ V11·
•
Saturation = Vsc, 1,
Vsc.1·
+
2
-V 11 , and VsD. I'
2
V1r
or
Transconductance
23.1 OPERATION OF
COMPLEMENTARY MOS
(CMOS) INVERTER
Figure 23.1 a shows a MOS inverter configuration
with a N-channel MOSFET (NMOS) as the output
•
Device transconductance parameter =
•
Process transconductance parameter =
•
Hole 1110/Jilih;
m 2 /V · s
336
=µ,
1,
=
230 cm"/V · s = 0.023
23.1
Gate Capacitance per Unit Area
• Pennittivity of SiO2
cm= 3.45 X 10m
17
=
=
= 3.45 X 10- 13 Fl
FIJ.Lm = 3.45 X 10- 11 Fl
=t
0
337
Output High State = VoH
Eox
• Thickness of gate oxide
Operation of Complementary MOS (CMOS) Inverter
x
Threshold Voltage
In determining the voltage transfer characteristic for
the CMOS inverter, first consider an input of V 1N =
0. For the NMOS transistor, Vcs,N = V1N = 0 < VT,N
and N 0 is in cutoff with ID,N(OFF) = 0. The PMOS
has Vsc,r = VDD
V1N = VDD > -VT,P (since Vsc,r
is large) and VsD,P < V 00 + VT.P and thus P 0 is in
the (active) linear mode of operation. However, ID,r
= ID,N so the drain current of P 0 is also 0. Equating
ID,r(LIN) = 0 yields
• Enhancement-only= Vrn,r < 0
• Enhancement-depletion = Vrn,r > 0
• Body bias effect =
Vrl' = Vrn,l' - Yr(YVas,r + 2l4ir11I - ~ )
• Zero body-bias threshold voltage
Body-Effect Coefficient
= VTo.P
=
Vour = Voo = Vo11
\/~2-q_N_o_E_s;
Yr=
Output Low State
• Elementary charge = q = 1.60 X 10- 19 C
• Donor dopant concentration = N 0 [llcm 3]
• Pennittivity of Silicon = Es, = 1.04 X 10- 12
Flem
Channel-Length Modulation Parameter
with the solution VsD,r = 0. However, since VsD,r =
V DD - VouT, the output voltage is therefore
=
Ar [V- 1 ]
= VoL
For V 1N = VoH = VDD, N 0 is operating in the linear
mode and P 0 is cutoff. VDs,N is obtained by solving
ID,N(LlN) = ID,r(OFF) = 0 as follows:
I o,N = kN [(Vcs,N - VT,N) Vos,N
s,N]
Vi'i
2
= kN [ Woo - Vr,N)Vos,N - -Vi'isN]
-· = 0
2
with the solution VDs,N
= VDD is
= 0. Thus, the output for V1N
VoL = Vos,N = 0
transistor and a P-channel MOSFET (PMOS) as the
load device. The gates of both N 0 and P 0 are connected to the input, giving V1N = V cs,N = V DD Vsc,r• The drains of both MOSFETs are also connected, the output being taken at this common drain
terminal. Thus, VouT = VDs,N = VDD - VsD,P· This
NMOS-PMOS configuration is named Complementary MOS, or CMOS. The VTC for the CMOS inverter
is shown in Figure 23.lb and will be described in
detail.
Note that either MOSFET can be considered the
load for the other. Considering N 0 as the load of the
"PMOS inverter" configuration is just as proper as
considering P O as the load on the NMOS inverting
transistor. Hence, the operations of N 0 and P 0
"complement" each other.
Unlike the NMOS inverter configurations, the output of the CMOS inverter does reduce all the way to
0 V. Since the output can range from O up to V DD,
the output is said to be "rail to rail."
Transition Region
For intermediate voltage inputs, the operation is as
follows. When the input reaches V 1N = Vr,N, N 0
turns on and operates in saturation, since V DS,N ?:
Vcs,N - VT,N· Meanwhile, P 0 is operating in the linear region, since VsD,P ::; Vsc,r + VT,P· As V 1N increases above VT,N the output voltage begins to reduce. When VDs,N drops below Vcs,N - VT,N, No
enters the linear region of operation. When the output drops to -VT,P below the input (i.e. Vso,r?: Vsc,P
338
Chapter 23/CMOS Inverter
VOUT
(V)
•I
V
:Jw,p
l
4
I
OH= VDD-I-:----- ~ 1
o
=loN =loo
VOUT
I I
1~~N
0
(a)
(b)
FIGURE 23.1 CMOS Inverter: (a) Circuit with complementary NMOS and PMOS output MOSFETs, (b) Voltage
transfer characteristic
+ VT,P and VT,P is negative), P 0 operates in the saturation mode. The states of N 0 and P O for the critical
voltages are tabulated in Table 23.1. Note that for
V1N = VouT = VM, both MOSFETs are in the saturation region of operation.
P O is cutoff. Since IDD = Io,N = -10 ,P, the current
supplied by VDo for both output states is zero or
Ioo(OH) = Io,,v(OFF) = 0
and
Ioo(OL) = - 10 ,p(OFF) = 0
23.2
POWER DISSIPATION OF CMOS
Static Power Dissipation
= P00 (avg) = 0
Hence, there is no static power dissipation for the
CMOS inverter or
P00 (avg)
The previous section showed that in the output high
state, N 0 is cutoff. Similarly, in the output low state,
Ioo(OH) + Ioo(OL)
= - - - - - - - - Voo
2
(0)
+ (0)
= ----
2
Voo = 0
Actual leakage currents exist in the steady state, but
are in the range of attoamps (10- 18 A), or less, and
can be ignored for all practical purposes.
TABLE 23.1 States of Transistors
for CMOS Inverter
Critical Point
NMOSNo
PMOS P0
Dynamic Power Dissipation= P00 (dyn)
VoH
Cutoff
Saturation
Saturation
Linear
Linear
Linear
Linear
Saturation
Saturation
Cutoff
Table 23.1 shows that both MOSFETs are active in
the intermediate range between V1L < V1N < ViH•
Hence, power is dissipated during the switching between the two output states of the CMOS inverter.
Figure 23.2a shows the 10 versus V1N curve for the
VIL
VM
v!I,
VoL
23.3
Graphical Determination of CMOS Inverter VTC
p DD "
IDD
339
V DD CW)
IDo(max)- ---------------------
-----"-------+---------"---~-►
VIN(V)
(b)
(a)
FIGURE 23.2
(a) CMOS drain current, (b) CMOS static power dissipation
CMOS inverter. Figure 23.2b shows the PoD =
I00V0 0 versus VIN curve. The power dissipated in a
CMOS inverter is therefore equal to the dynamic
power dissipated, and has the same form as the dynamic power dissipated in NMOS inverters, given by
P 00 (CMOS) = Poo(dyn) = CLvV:bo
where CL is the load capacitance and v is the frequency of switching.
The extremely low power dissipation of CMOS
has made possible applications that could almost
never exist using any of the NMOS families discussed in the previous chapters.
23.3 GRAPHICAL DETERMINATION
OF CMOS INVERTER VTC
For the CMOS inverter, the drain current of N 0 must
equal the drain current of P0 under all static operating conditions. Graphical solution of the CMOS
inverter VTC is therefore possible but complicated by
the fact that these MOSFETs change operating state
as V1N and correspondingly VouT change. Hence, the
current-voltage expressions for N 0 and P 0 in the saturation and linear regions must be used. Rewriting
the expressions for the N-channel MOSFET substituting Vcs,N = VIN and Y0s,N = Vom, we have
_ kN
IoN(SAT) - '
Example 23.1 Power Dissipation
of CMOS Inverter
Determine the power dissipated in a CMOS inverter
with V00 = 5 V operating at 25 MHz and a load
capacitance of CL = 0.05 pF.
Solution By direct substitution
P 00 (CMOS)
= P00 (dyn) = (0.05p)(25M)(5) 2
= 31.25 flw
2
(VIN - VTN)
2
for YouT:? V1N - VTN and
for VouT s V1N - VTN· Rewriting the current-voltage
expressions for the P-channel MOSFET substituting
Vscy = Voo - V1N and Vso,r = Voo - Vour yields
340
Chapter 23/CM0S Inverter
VOUT (V)
r--,
t
iv.a,.= 5 v (VIN= ov)
V -5 P(LIN)
DD-
!N(OFF)
!
4_l_
I
I
I
31-
r•oc4
1
'
vM+
\
'
\
=2V) ,
Jii-----""---c:-'--~----vm=3V
~~.-,,,il:.w;....,,;.;....,;,,-A-.,,.....~---::VIN = 2.5 V
IH::--...-~......."l""!"'C~......~-~iiF--VIN=2V
,=....--1-~......,;;;...;.~£q1-.:..;.-'-I----Jl~-~1v
2
3
4
5
0
2-1
I
I
I
1+
I
P(OFF)
0 -'----+---+---+-----+-"""'"'--.N_(L.;.._IN)~0
1
2 VM 3
4
5'
VIN(V)
VoUT = Vos.N = VDD - VsD.P (V)
CMOS Voltage Transfer Characteristic
Determined from Graphical Solution of Figure 23.3.
FIGURE 23.3 10 versus Vos Current-voltage
Characteristics for N0 and PO with VTN = IVwl and
kN = k1,
FIGURE 23.4
for V0 o - VouT
ration and VIN = 2.5 V ( = V00 /2). Note that the
graphically determined output low voltage VOL is
zero and the graphically determined output high
voltage VOH = V0 0 . Hence, the graphical solution
gives exact values for these voltages.
2:
V00
-
VIN+ VTP and
lo,p(LIN) = k1{ Woo - VIN+ Vrp)Woo - VouT)
_ Woo - VouT)2]
2
for Voo - VouT < Voo - V1N + Vw,
Figure 23.3 displays the Io,N versus Vos.N
(= VouT) family of curves for N 0 as well as the Io,P
versus V 00 - Vso,P (= V0 UT) family of curves for P 0
obtained from the l 0 versus V0 s equations. The parameter in each case is VIN· The horizontal portion
of the curves for each of the two MOSFETs is the
saturation region. The steeper sloped portions of the
current-voltage characteristics represent the linear
regions of operation.
To graphically determine the VTC, ordered pairs
of (Vcs,N, V0 s,N) or (VIN, VoUT) are read from the
intersection of the Io,N and Io,P curves with the same
value of VIN· These points are in turn mapped onto
the VOUT versus VIN coordinate axes as in Figure 23.4.
The voltage transfer characteristic is the resulting
curve through these plotted points. Note that for
VIN = 2.5 V, the intersection of the two current-voltage curves is a line from VouT = 1.5 V to 3.5 V. This
is the region in which both MOSFETs are in satu-
23.4 CALCULATION OF VTC
CRITICAL POINTS FOR
CMOS INVERTER
Output High Voltage
= VoH
The output high voltage was found in section 23.1
and 23.2 to be the supply voltage and thus
VoH = Voo
Output Low Voltage
= VoL
The output low voltage was found in section 23.1 and
23.2 to be zero or at ground and thus
VOL= GND = 0
Input Low Voltage
=V
1L
At the input low voltage, the NMOS operates in the
saturation mode and the PMOS operates in the !in-
23.4
ear mode. Substituting Vcs.N = Vru Vsc.1' = VuD V11 _, and VSD.I' = V DD - V0UT into the saturated
N-channel and linear P-channel drain currents gives
Io,N(SAT) =
kN
2
InN(SAT)
k;
Wn - VTN)2
_ V
) _ (Vno - VoUT)2]
OUT
7
2
which is quadratic. The linear and quadratic equations must be solved simultaneously to obtain VrL
and the corresponding output voltage.
?
2
and
V~oy]
10 .r(LIN) = kr [ Wsc,P + VTr)Vso,r - - 2 -
= kr[ Woo - VIL + Vrr)Woo - VouT)
_ Woo - VouT)2]
2
With ID,N = ID,N(VrN) and IDY = ID,r(VrN, VouT),
equating the differentials of the NMOS and PMOS
drain currents yields
Input High Voltage = Vm
Solution of the input high voltage is similar to that
for the input low voltage. Here, the NMOS is operating in the linear mode and the PMOS operates in
the saturation mode. Substituting Vcs,N = V1H, VDs,N
= VouT, and V sc.r = VDD - V1H into the linear
N-channel and saturated P-channel drain current
expressions gives
Io,N(LIN)
= dlo,rWu_, VouT)
dlo,N V - aID,l' dV
aloy d
IL +
VOUT
d IL d Vu
av/I
aVouT
Solving for dV 0 vrldVrN
this to -1 yields
= dV 0 UT/dV1L and equating
dlo,N
aloy
-----
dVouT
dV1L
= lny(LIN)
= kr[ (VDD - VIL + Vn,)(Voo
Wcs,N - VTN)-
= kN (VIL - VTN)-
dlo,N(Vll)
341
Calculation of VTC Critical Points for CMOS Inverter
= kN [ (Vcs,N - VTN)Vos,N - -Vi:JsN]
-'
2
VzxIT]
-
)
= kN [ (VJH
VTN VouT - -
2
and
In,r(SAT) =
-1
kr
2 Wsc,P
+ Vn,)
2
alo.r
aVouT
With ID,N = ID,N(VIN, V0 u1 ) and ID,P = I0 ,l'(V1N),
equating drain current differentials yields
Rearranging yields
dlo,N - alo,l'
dViL
av/L
Substituting for the derivatives gives
kN(ViL - VfN) + kp(Voo - VouT)
= -kp[-(Voo - Vn +VT!')+ (Voo - VoUT)]
Solving for dVouT/dV1N = dVoUT/dVrH gives
Solving for VrL yields the linear expression
kN
+ V-rl' + kp VTN
V1L = - - - - - - - - - - ' - 2VouT - Voo
1 + kN
kr
The second equation relating V1L and VouT(IL) is obtained by equating drain currents of the NMOS and
PMOS as follows:
dlo,P - aID,N
dVouT
dVIH
=
dVi11
av/11
alo,N
aVouT
Rearranging yields
dlo,P - alo,N
Vu-1
aVn,
=
alo,N
aVouT
-1
342
Chapter 23/0vlOS Inverter
Substituting for the derivatives yields
Example 23.2
-kl'(VDo - V111 + V-,-p) - k,vVmrr
= - k,v[(V,11 - VTN) - Vuurl
Solving for V 111 gives a linear relation as follows:
k,v
V00 + Vrr + - (V-r,v + 2VOLrr)
kl'
Vi11 = - - - - - - - - - - - k,v
1 + -kl'
The second equation relating V1H and Vou-r(IH) is
obtained by equating drain currents of the NMOS
and PMOS as follows:
CMOS Inverter
Calculate the noise margins and midpoint voltage for
a CMOS inverter. Use Vrm = 5 V, k~ = 40 µ,AN 2,
Wr:--;IL:-:. = 4µ,rn/2µ,m, VTN = 1 V, k1
, = 16 µ,AN 2,
Wp/LI' = 8µ,m/2µ,m, and V11 , = - 1 V.
Solution (Transconductance Parameters) The
transconductance parameters for both transistors
must first be calculated yielding
k,v
= k~( ~ t = (40µ,)G:) = 80 µ,
:2
and
8
2µ,
kl' = k~(W) = (16µ,)( µ,) = 64 µ, A,
L r
V-
= 1.25.
This gives a ratio of k1,Jkp
Solution (Output High and Low Voltages) V 0 11
and V 0
1.
are found by a simple substitution with
V011 =
which is a quadratic relation. The linear and qua dratic equations 1T1ust be solved simultaneously to
obtain V 11-1 and the corresponding output voltage .
Midpoint Voltage= VM
At the midpoint voltage where V1N = VouT = V.1,,1,
both the NMOS and the PMOS operate in saturation. Substituting Vcs. r--: = V:vi and Vsc;. 1, = VuD VM gives the drain currents
5
V
and
VOL= 0
Solution (Input Low Voltage) V 1L is found by si multaneously solving the linear and quadratic expressions. Substitution into the linear expression
yields
(80µ,)
(1)
64µ,)
+ (-1) + -(-
2VourUL) - (5)
l
+ (80µ,)
(64µ,)
= 0.89VourUL)
- ....2...3-7-&
2,f: · '
and solving for V0 u1 (IL) gives
and
V0 w(IL)
= 1.125V,L +
2.375
Substitution into the quadratic expression resulting
from equating drain currents yields
(80µ,)
7
- - [V11 _- (l)J2
Equating drain currents and solving for
v~.1 yields
= (64µ,)
{
[(5) - v,L
+ (-l)l
[(5) - (1.125V11. + 2.375)]
_ [(5) - (1.125;,1. + 2.375)]2}
Reducing and collecting like terms gives
(8.5µ,)V7,.
+ (-212.9µ,)V,L + (-46 7.8µ,) = 0
23.5
Solving this reduced quadratic yields
VrL = 2.03 or -27.1 V
and thus V1L = 2.03 V.
Solution (Input High Voltage)
V1H is found by
first substituting into the linear relation to obtain
(5) + (-1) + ((SOµ,)) [1 + 2VourUH)]
64µ,
V/11 = -------'----'--'--------(1) + (80µ,)
(64µ,)
= 1.11 VomUH) + 2.33
The Symmetric CMOS Inverter
343
symmetric VTC is to obtain a symmetric transient
response, as will be seen in section 23. 7. Since the
nearly vertical portion of the VTC occurs at V1N =
VM, it is desired to have VM = V1m/2 for a symmetric
VTC. Examining the expression for VM derived in the
previous section, it is seen that VM = V00 /2 if ki--.: =
kp and VTN = -Vw. The input low and input high
voltages V1L and V1H are then also symmetric about
VM. This results in equal noise margins and the low
and high logic levels will have the same susceptibility
to noise.
Design of Symmetric CMOS Inverter
Solving for VmdIH) yields
VourUH) = 0.9V111 - 2.1
Next, substituting into the quadratic expression for
Va-i obtained from equating drain currents gives
(SOµ,){
lVH-i -
(l)](0.9Vu 1
-
2.1)
The complementary MOSFETs are designed in the
following manner in order to obtain the symmetric
CMOS inverter. First, the threshold voltages are
made equal in magnitude by using ion implantation.
Usually, both channels require a threshold adjust implant. Second, the requirements for kN = kp must be
considered. Equating the device transconductance
parameters, we have
1 - 2.1)2} _ (64µ,) [( )
(0.9Vu
- -- - - - - 5 - V + ( -1 )] 2
2
2
m
Collecting like terms yields
(7.6µ,)VTu
+ (167.2µ,Wur + (-520µ,) = o
and solving the reduced quadratic, we have
Vu 1 = 2.76 or -24.8 V
Hence, V111
The process transconductance parameter for each
N- and P-channel MOSFET is k~ = µ,NCox and k~ =
µ,pC 0 X/ respectively. Substituting these expressions
gives
= 2. 76 V.
Solution (Input Noise Margins) The noise margins are then calculated as
NM11
NML
=
=
Vo 11 - Vu 1 = (5) - (2. 76) = 2.24 V
VIL - VoL = (2.03) - (0) = 2.03 V
The midpoint voltage is found by direct substitution
(5)
+ (-1) + (1)
(SOµ,)
64
VM = - - - - - = = ~ (_ _µ,) = 2.42 V
(SOµ,)
1+
(64µ,)
23.5 THE SYMMETRIC
CMOS INVERTER
A valuable aspect of CMOS is that a symmetric VTC
is easily obtainable. One reason for designing with a
Usually, the gate oxide layers of the NMOS and
PMOS devices are grown simultaneously and hence
have the same thickness t x. Since the gate capacitance per unit area is C x = E xft x, simultaneous
growth of the oxide layers results in the same Cox·
Thus, the above equation reduces to
0
0
0
0
Typically, for the surface of silicon the electron
and hole mobilities are approximately fl-N(Si) =
580 cm/V · s and µ,p(Si) = 230 cm/V · s. Substituting
these values yields
(580) WLN = (230) Wp
N
Lp
344
Chapter 23/CMOS Inverter
<1nd reduces approximately to
Wr
Lr
r
.·
(80µ,)
2VuurCZL) - (::i) + (-1) + -(-) (1)
80µ,
= 2 _5 WN
l + (80µ.,)
(80µ.,)
LN
Hence, in order for kN = kp, Wp/Lr and W N/LN for
the complementary MOSFETs must be related by the
charge carrier mobility ratio of approximately 2.5.
=
VourUL) - 2.5
and solving for Vour(IL) gives
VourUL)
Example 23.3
Symmetric CMOS Inverter
(a) Design a syrnrnelric CMOS iuverter using the
values of VoD, VTN, Vm kr'.J, and k(, used in Example 23.l For the NMOS device, use a channel
width of W N = 4 µ.,m and channel lengths of
LN = Lr = 2 µ.,m for both transistors. Verify that
the midpoint voltage is half of VDD and V1L and
V1H are symmetric about VM.
(b) Also, verify that the gate oxide capacitances for
the NMOS and PMOS devices of Example 23.1
are equal.
Solution (a)
For symmetry, the P-channel
MOSFET should have a channel width of
WN
(4µ.,)
Wr = 2.5 Lr = 2.5 - ) (2µ.,) = 10 µ,111
LN
Substitution into the quadratic expression resulting
from equating drain currents yields
8
( ~µ,) [VIL - (1))2 = (80µ.,){ [(5) - Vu.+ (-1))[(5)
- CV1L + 2.5)] - [(5) -
(V;
)F}
+ 2·5
Reducing and collecting like terms gives
ov~_
+ (240µ.,)Vi1 - (510µ.,) = o
Solving this reduced quadratic yields
V11
= 2.125
V
+ (-1) + _((8_0µ.,_)) [1 + 2VourUH)]
Vi11 = - - - - - - -80µ,
-'------(1) + (80µ.,)
(5)
_ ,(W)
L _
A
N - (40µ.,) (4µ.,)
2µ., _- 80 µ., V"
(64µ.,)
and
= VourUH) + 2.5
Solving for Vuur(IH) yields
Note the device transconductance parameters are
equal.
Solution (Midpoint Voltage) The midpoint voltage for this inverter is
VM
2.5
Solution (Input High Voltage) V111 is found by
first substituting into the linear relation
2µ,
The device transconductance parameters are
kN - kN
= ViL +
=
(5) + (-1) + (1)
------==~(_8_0µ.,_)
~o~
1+
(80µ.,)
V otrrUH)
2.5 V
2.5
- (l)lCVi11 - 2.5) - CV111 - 2.5)2}
2
= (80µ.,) [(5) -
= Voo
2
2
Solution (Input Low Voltage) V1L is found by simultaneously solving the linear and quadratic expressions. Substitution into the linear exprssion
yields
V111 -
Next, substituting into the quadratic expression for
V,H obtained from equating drain currents gives
(80µ.,) { W111
=
=
V111
+ (-1)] 2
Collecting like terms yields
OVf11 + (240µ.,)Vi 11 + (-690µ.,)
Solving the reduced quadratic yields
V111
= 2.875 V
=
0
23.6
(16µ,-VA)
Yoo
0
!
s :
71
I
v.,,
2µm
I+
C,x(PMOS)
0
= IoN = loo
l'V=
-IC
I D
lop
4µm N0
FIGURE 23.5 Symmetric CMOS Inverter with
Wp/Lp = 2.5 W c-J/Lr--:
cm
230V·S
)
aF
=
696 - ,
µ,nr
23.6 THE MINIMUM SIZE
CMOS INVERTER
Solution (Symmetry Achieved) The input low
and high voltage differences from the midpoint voltage are
= 0.375 V
and
=
f-.lp
= (
As mentioned at the beginning of this section,
section 23.8 shows that designing the CMOS inverter for a symmetric VTC results in a symmetric
dynamic response also.
l
(2.5) - (2.125)
= -
The capacitances of the N- and P-channel MOSFETs
are in fact within a few percent of each other.
~ 2µm
V111 - V,v1
2
kf,
I f--j_ 1_(}J.l.m p
345
The Minimum Size CMOS Inverter
(2.875) - (2.5) = 0.375 V
With the midpoint voltage at VDl)2 and the input
low and high voltage equidistant from VM, the symn,etry of this CMOS inverter, sketched in Figure 23.5
is verified. This is no surprise, since the device transconductance parameters are equal (k1'! = kp = 80
µ,A/V 2) and the threshold voltages are equal in magnitude (V1 N = IVwl = 1 V).
Solution (b) In the derivation of design restrictions
for a symmetric CMOS inverter VTC, it was assumed
that the gate oxide capacitances of the MMOS and
PMOS device were equal. This can be proven for the
process transconductance parameters easily:
In the previous section, design restraints on the
CMOS inverter that provide a symmetric voltage
transfer characteristic and transient response are
presented. For CMOS inverters that do not have
large fan-outs and do not need to switch quickly,
minimum dimensions for the width and length of
both devices yield adequate performance. For such a
situation, the widths and lengths of the two devices
are taken as equal (Wp = Wr,.: and Lp = LN), The
following example indicates such a design.
Example 23.4 Minimum Size CMOS Inverter
Determine the noise margins for a CMOS inverter
with transistor channel width/length ratios of W N/LN
= Wp/Lp = 4µ,m/2µ,m. Use the parameters kt'.; =
40 µ,A/V 2 and k~ = 16 µ,A/V 2 and threshold voltage
VrN = 1 V and VTF = -1 V used in the previous
examples.
Solution (Device Transconductance Parameters) The device transconductances parameters are
first obtained as
( 40µ, ~)
=
C,(NMOS)
(
and
Cl/1 )
580V· s
696
kN = kN1 (W)
= (40µ,) (4µ,)
= 80 µ,----::;
A
L N
2µ,
v-
!1.£_
7
µ,nr
and
(16µ,) ( -4µ,)
2µ,
A
= 32 µ,-:,
v-
346
Chapter 23/CMOS Inverter
Note the device transconductance parameters are related by a factor of 2.5, the approximate ratio of electron/hole mobilities µ, 1) f.lp in the silicon surface.
Solution (Output High and Low Voltages) The
output high and low voltages are simply
and
v/\'ML
= VIL - Vo1. = (1.70) - (0) = 1.70 V
These noise margins are acceptable for CMOS applications not requiring symmetry in DC or transient
response.
Vou = 5 V
and
23.7 CMOS INVERTER
CAPACITANCES
Solution (Input LoiA11T and Hig.,_'1 lloltagcs) The
input low and high voltages are found by the methods of section 23.4 to be
ViL =
l.70 V
and
Vi11 = 2.43
V
Solution (Noise Margins) The noise margins are
therefore
VNMH = V0 u - V1u = (5) - (2.43) = 2.57 V
w,
As mentioned in section 16. 7 and shown in Figure
16.8, MOSFETs have parasitic capacitances between
each pair of terminals. Hence, at the input of a
CMOS inverter the capacitances for both MOSFETs
must be charged and discharged during switching of
the input logic state.
CMOS Inverter Input Capacitances
The input capacitances for a CMOS inverter are
shown in Figure 23.6a. The gate-to-drain, gate-to-
p
i:::;o
v™
c;,, = (CGD,N + CGS,N + COB,N) + (COD.P + CGS,P + COB.P)
= CoN + Co, "' (WN¼ + W,L,.)Cox
(a)
FIGURE 23.6 CMOS Inverter Capacitances: (a) Input
capacitances seen looking into CMOS inverter input,
(b)
(b) Output capacitances seen looking into CMOS
inverter output
23. 7
source, and gate-to-body capacitances of both the
NMOS and PMOS transistors must all be charged or
discharged through the input node of a CMOS inverter during the switching of the input logic state.
As discussed in section 16. 7, these capacitances overlap and can be estimated as the channel area multiplied by the gate oxide capacitance per unit area
c;". Thus,
for the N-channel MOSFET, and
for the P-channel MOSFET. As mentioned previously, the gate oxide capacitance per unit area c;" of
the NMOS and PMOS devices should be the same,
since the gate oxides of both transistors are fabricated at the same time. Hence, the effective input
capacitance of a CMOS inverter can be estimated as
the sum of gate capacitances of the NMOS and
PMOS transistors as follows:
CIN = Cc,N
+ Cc_;y = (WNLN + WpLp)C:,,
CMOS Inverter Output Capacitances
The capacitances at the output of a CMOS inverter
are shown in Figure 23.6b. These are the drain-tobody and gate-to-drain capacitances of both
MOSFETs. The gate-to-drain capacitances were
shown as contributing to the input capacitances in
Figure 23.6a. These capacitances are charged and
discharged through both the input and output nodes
of the inverter. The drain-to-body capacitance, however, is charged solely through the output terminal.
CMOS inverters. The inverter output capacitances
are indicated on the driving inverter and the input
capacitances are indicated on the load inverter. In
addition, a line capacitance associated with the n,etal
used to connect the output of the driving inverter to
the input of the load inverter is included.
Gate Capacitances of Load Inverter
Are Dominant
The input gate capacitances of the load inverter are
generally dominant over the output driving gate capacitances and the line capacitance of the connecting
node as indicated in Figure 23.76, where all other
capacitances are treated as open circuits. Analyses of
the dynamic response and fan-out of the CMOS inverter presented in the following sections will use
this estimation of load capacitance.
Example 23.5 CMOS Inverter
Input Capacitance
(a) Determine the input capacitance of the CMOS
inverter of Figure 23.5 (used in Example 23.3).
(b) Determine the input capacitance for a CMOS inverter with W;,-.i/LN = 100 µ.m/2µ.m and Wp/Lp
= 250µ.m/2µ.m.
Assume a gate oxide thickness of 500
C' • =
No Source-to-Body Capacitance
Common Node Capacitance of
Cascaded CMOS Inverters
Figure 23. 7a displays all the capacitances associated
with the common node between two cascaded
A.
Solution (Gate Oxide Capacitance per Unit
Area) The gate oxide capacitance per unit area for
an oxide thickness of 500 A is
( 3.45
It should be noted that the source-to-body capacitance of neither MOSFET has been mentioned in the
previous sub-sections. This is because the source and
body of both devices are connected to a common
node (ground or V00 ) and these parasitic capacitances are shorted out. Thus, the charge stored in
CsR,N and CsB,I' is zero.
34 7
CMOS Inverter Capacitances
"·'
Eox
(n
=
X
10- 11
£)
m
= - - - - -10- - = 690
(500 X 10- 111)
F
!!._
111 2
aF
690~.,
µ.nr
where 1 aF (attofarrad) is 10-rn F.
Solution (a) Estimating the inverter input capacitance as the sum of the MOSFET gate capacitances
gives
C1N
=
[(4µ.)(2µ.) + (10µ.)(2µ.)](690a/µ. 2)
=
19.3 JF
Solution (b) Again, estimating the inverter input
capacitance as the sum of the MOSFET gate capacitances gives
348
Chapter 23/CMOS Inverter
c,~1 =
=
[(100µ,)(2µ,)
483
+
(250µ,)(2µ,)](690a/µ, 2)
The magnitude of input capacitances obtained in
the previous example should be noted prior to reading the following sections. These magnitudes of input capacitances of CMOS inverters are on the order
of tens to hundreds of femtofarads. Indeed, an input
fF
This is approximately 0.5 pF.
V'oo
Your= V'IN
load inverter
driving inverter
(a)
V'oo
W',L'1C~
w NL NCOX
,
I
J
I
W'
I
Y
I
~N'
'l··
I - -:- LN
P'o
0
(b)
FIGURE 23. 7 Capacitances at Connection of Cascaded
CMOS Inverters: (a) Output capacitances of driving
inverter, input capacitances of load inverter, and
capacitances of connecting line, (b) Dominant load
capacitances are gate capacitances of load inverter's
NMOS and PMOS devices
:23.8
capacitance of 1 pF would only occur for a very large
inverter.
Also, some modern CMOS technologies allow
for oxide thicknesses of less than 200 A. CMOS inverters with gate oxides this small would have larger
input capacitances.
T
Abridged Integral Table
The following integral will be used in the analysis of the CMOS inverter transient response:
f
Capacitor Current-Voltage
Characteristic
The CMOS inverter dynamic or transient response presented in the following section requires knowledge of the current-voltage characteristic of capacitors indicated in Figure 23.8.
Recall that the current-voltage characteristic of
a capacitor is
dVc
dt
I-= C -
349
Tips, Tricks, and Gimmicks
Tips, Tricks, and Gimmicks
c
CMOS Inverter Dvnarnic Response
T
ax : bx 2
~ In C: bx)
Tips, Tricks, and Gimmicks
Difference Property of Logarithms
The following difference property of logarithms
will be used in the analysis of the CMOS inverter transient response:
In a - In b = In
a
b
If the voltage Vc across the capacitor as labeled
is increasing, then dV c/dt is positive and the
capacitor current le as labeled is positive, with
V c increasing ~
dVc
dt
> 0
⇒
le > 0
Similarly, if the voltage Ve across the capacitor
as labeled is decreasing, then dV cldt is negative
and the capacitor current le as labeled is negative. Thus,
dVc
Ve decreasing~ < 0
dt
⇒ le<
0
23.8 CMOS INVERTER
DYNAMIC RESPONSE
The analysis of the CMOS inverter dynamic or transient response is similar to that presented for the
NMOS logic family inverters of the previous chapters. Each load inverter contributes to the load capacitance of the driving inverter as shown in Figure
23.9a. The dynamic response is considered by analyzing the CMOS inverter with total load capacitance
Cu shown in Figure 23.9b. The dynamic response of
the CMOS inverter including the states of each
MOSFET for step changes in input will be studied
and expressions for time periods required for general
changes in output voltage are derived.
Output High-to-Low Transition
Ye increasing
➔ ~> 0 ⇒ le> 0
Vc decreasing
➔ ~ < 0 ⇒ le < 0
FIGURE 23.8
(reversed)
Charging and Discharging of a Capacitor
The transient characteristics of interest during the
output high-to-low transition are the fall time tr and
high-to-low propagation time tPHL· Figure 23.10a
shows a step-up input voltage stimulus and the resulting CMOS inverter output response with tr and
tPHL labeled. Prior to the input voltage swing (V1N
350
Chapter 23/CMOS Inverter
V'oo
t.l
I
I
w,
4
p
o
I
Your= V'm
;---0V'OUf!
V'oo
w·,Lr, I:
C'ap
..l
1
w·
Y,P'02
} I
V'mm
driving inverter
f
~
~
1
1
W NL NCox
all load inverters
contribute to the
capacitive load on
the driving inverter
C'tjN
,
~N'
RLN
I
1
-:-
V'oo
02
W'.L'P~OX
Iy
tjw,
I
C'ap }p
---.
P'o,
V'our,
C'j
ON
f
9 I
W'NL'NCOX
W'
~N'0 ,
N
-:;:load inverters
(a)
FIGURE 23.9
CMOS Inverter Driving Loads with
Capacitances Extracted: (a) Each load inverter contributes
a capacitance to the output of the driving inverter with
low), the inverter is in the output high state with N 0
cutoff and P 0 operating in the linear mode of operation. After switching of the input, Yscy = 0 cutting
off P0 and Ycs,N = VDD forcing N 0 into active operation.
Figure 23.106 displays this situation with a load
capacitance discharging through an active N-channel MOSFET (P 0 cutoff). KCL at the inverter output
node results in
total load capacitance equal to the sum of the
capacitances
l 0 ,,v(active) = [0 .l'(off)
le= -C dVoUT
L
dt
Solving for the time differential considering the
NMOS drain current a function of the output voltage
yields
23.8
351
CMOS Inverter Dynamic Response
,md
write KCL at
output node
Substituting these NMOS drain current expressions
into the above integrands gives
M
M(SAT) + M(LIN)
output load modelled
as a capacitance
(b)
FIGURE 23.9 (continued)
capacitance
The first of the integral terms is easily integrated
yielding
(b) Inverter driving a load
The time period ~t required for a given change in
output voltage during the output high-to-low transition is obtained by integrating both sides of this
expression to obtain
~t
= t2 -
M(SAT)
= r,w,,llr~V,) dt
t1
J11Wrnrr~V1)
= -CL
!i
v,
dVouT
Substituting the limits of integration gives
v, lo.N(VouT)
Note from Figure 23.10a, that the NMOS device
changes from the saturation to linear mode of operation during the high-to-low transition at VouT =
vl)l)
VTN, while VIN= v l ) l ) during this entire transition. The above integral must be solved for each
region of operation separately and thus the integral
is written as
v,,,,-v,N dV
~t = -C1
OUT
V1
10 .N(SAT)
v.
dVour
C1.
-vn,,-v,N lo,N(LIN)
li
!i
The NMOS drain currents for the two active modes
of operation, substituting Vcs,N = V1N = Vc)H = V 00
and VDs,N = VoL'T are
ILJ,N(SA T) =
kN
2
(VCS,N -
)?
VIN -
=
kN
2
(VDD
?
-
VTN)-
M(SAT)
= -2CL(VOLJ - VTN ~ V1)
kN(Vrm - VTN)-
The second integral term is obtained by utilizing the
indefinite integral given in the Tips, Tricks, and Gimmicks box preceding this section as follows:
viurl
VTN)VouT - dVouT
2
-
352
Chapter 23/CMOS Inverter
V,,,(V)
•
VoL=O
--~----I,,
t(ns)
Your(V)
./NMOS enters saturation mode
VoH= Yoo
i---------NMOS cutoff
•
PMOS li/
PMOS cutsoff
.-90%VOH
·
~ NMOS enters linear mode
·
========--=--=--~---,---~=-----~____.
1-r:;=i---_-_-_-_-_-_--:__---=-------;-t,
t(ns)
~t-~
(a)
load capacitance discharging
ID.N
= -C d~ttrr
(b)
FIGURE 23.10 CMOS Inverter Output High-to-low
Transition: (a) Step-up input and output response curves,
(b) Load capacitance discharges through active NMOS
transistor
23.8
Substituting the limits of integration yields
=
·
~
M(LIN)
CMOS Inverter Dvnamic Response
353
2CL(VTN + 0.9Von - Voo)
2
kN(Voo - Vm)
C1.
+
ln(2V00
-
kNCVoo-VrN
2VrN
0.1VmJ)
0.1Voo
2CL(VTN - 0.1VoD)
- In(
kNCVoo - Vrn)2
+ kNCVoo
Using the difference property of logarithms gives
M(LIN) =
)
-CL
ln(
V2
kN(Vno - VTN)
2Voo - 2VTN - V2
Sun1ming these terms gives an expression for the
time period required for a voltage change during the
output high-to-low transition as follows:
M = M(SA T) + M(LIN)
-2CLCVoo - VrN - V1)
kNCVno - VTN)2
+
-CL
kNCVoo - VTN
In(
V2
)
2Vno - 2Vm - V2
Rewriting to eliminate the negative sign in each term
Note that M in this expression is directly proportional to the load capacitance CL and inversely proportional to the NMOS device transconductance parameter kl':- Since kN = kr'.i(WN/L:--i), high-to-low
transition times of CMOS inverters are inversely proportional to the NMOS channel width/length ratio.
VTN) n
0.1 Von
Note that this expression is directly proportional to
the load capacitance and inversely proportional to
W:--i/L:--i for the NMOS transistor. By substitution and
factoring, we have
CL
tr= WNILN
[2(VTN - 0.1 VDD)
k~CVoo - Vmf
1
l (1.9VoD - 2Vm)]
0.1Vim
+ k~CVoo - VTN) n
Output Propagation High-to-Low Delay
Time= tPHL
The output propagation high-to-low delay time tp 1IL
is defined as the time difference between the input
at 50% of V1:--i.MAx to the output at 50% of Vrn-1- Since
a step input (instantaneous low-to-high switching of
the input) is used for this analysis, tPHI is the time
after switching that the output takes to drop from
Vm.1 to 50% of VoH· Substituting V 1 = VoH = V00
and V2 = 0.5V 0 r1 = 0.5V 0 lJ into the output high-tolow transition period expression M yields
tPHL
Output Fall Time
I (1.9Voo - 2Vrn)
CL
Voo
=
2CL(VIN + Voo - DD)
kNCVoo - Vm)2
CL
+----kN(VI)[) - v,N)
ln(2VDo - 2Vm - 0.5VDD)
0.5V1m
= t1
The output fall time tr is defined as the time difference needed for the output to fall from 90% to 10%
of the output high voltage. Thus, substituting V1 =
0.9V 0 H = 0.9V 00 and V 2 = 0.1VoH = 0.1V1)D into
the output high-to-low transition period expression
yields
As with tr, this expression is directly proportional to
the load capacitance and inversely proportional to
WN/LN.
354
Chapter 23/CMOS Inverter
Output Low-to-High Transition
Analysis of the output low-to-high transition is similar to that of the output high-to-low transition. The
transient characteristics of concern for the output
low-to-high transition are the rise time tr and the
low-to-high propagation delay tl'LH· Figure 23.11a
shows a step-down input voltage stimulus and the
resulting CMOS inverter output response with tr and
tpu I labeled. Before the input high-to-low swing, the
inverter is in the output low state with the NMOS
Jevice upetali11g ill the lilledr wode of uperalion aud
the PMOS device cutoff. After the switching of the
input, Ycs,N = 0 cutting off the N-channel MOSFET
and Ysc,P = VDo bringing the P-channel MOSFET
into active operation.
Figure 23.116 displays this situation with a load
capacitance charging through an active P-channel
MOSFET (N 0 cutoff). KCL at the output node gives
10 ,1,(active) = Io,N(off) + C1
dVouT _
d
t-
C dVou-r
L
dt
SubstitutingVsc;, 1, = V1m - V 1~ = V,m - Vex= VDD
and VSD.I' = VLJD - VoL:T into the active PMOS drain
current expressions gives
and
[D,i,(LIN)
=
kp [ (Vsc,1'
=
kp[ (Voo
+ Vrp)Vso,P - -Vio,P]
2
+ Vn,)(Voo - Vow·)
_ (VDD -
Vmnf]
2
Substituting these PMOS drain currents into the low
to high M integrands gives
M
=
M(SA T) + M(LIN)
Solving for the time differential considering the
PMOS drain current a function of the output voltage
yields
The time period M required for a change in output
voltage during the output low-to-high transition is
obtained by integrating both sides of this differential
expression to obtain
As with the N-channel MOSFET during the high-tolow output transition, the P-channel MOSFET
changes mode of operation during the output lowto-high transition. As the output voltage changes
from O to V00 , Figure 23.116 indicates that the
PMOS device changes to the linear mode when VoL:T
reaches -Vm while V 1~ = 0 V during this entire
transition. Thus, the low-to-high output transition
must also be obtained in each region of operation
separately and
The first term is easily integrated to obtain
M(SAT) =
Substituting the limits of integration gives
The second term is integrated by first noting that
and then utilizing the indefinite integral given in the
preceding Tips, Tricks, and Gimmicks box. Hence,
23.8
CMOS Inverter Dynamic Response
VIN(V)
YOH= VDD
~-----------'---------------------~-4 t(ns)
Ymrr(V)
YoH =Yoo
PMOS enters
linear mode
PMOS enters
saturation mode
I.
PMOS~!
---------•-
NMOS linear/
~
t, ___________,...,j
------~---_...
t(ns)
t.ui------..J
NMOS cutsoff
(a)
YDD
load capacitance charging
IDJ'= C dYour
dt
lk~~Yo_m__~~
;LVIN
IDJ'
I♦
,----------'
: NMOS:
: cutoff :
I
__________ I
(h)
FIGURE 23.11 CMOS Inverter Output Low-to-high
Transition: (a) Step-down input and output response
curves, (b) Load capacitance charges through PMOS
transistor
355
356
Chapter 23/CMOS In verter
.:,./ (U N) = C,
,;
f
,·".
Output Rise Time
dV
''"'
k,,
[
(V,.,, + \/ 11 ,) (V,.,, - \I, ,,,, l -
(II,.,, - \/,,,,,)' ]
2
== l,.
The output rise time is defined as the time difference
requ ired for the output to rise from 10% to 90% of
VOii· Substituting
= O.lVrn 1 = 0.1V,)IJ and
=
0.9V 0 H = 0.9V 1m into th e output low - to - high time
period expression gives the expression for th e rise
time as follows:
v~
= -
c,.
V,,,, - \/,,,,.,
In (
k,,(Vnn + V.,.,,)
,·,
V, iur)
\/pp -
V1111 + V,.,, -
2.
-2C1_(V11 , + 0.1 V00)
,·,,.
k"(V[)l) + Vn,f
t, =
Substituting th e limits of integration yields
v.,
+ 2V11 ,
1- - - -CL
- - - In (Vr,
-0-
+ 0.9Vnn)
VJ)/) - 0.9V00
k"(V,)/) + V11 ,)
t:.t(LIN)
- 2CL(Vn,
+ 0.1 V/Jn)
k"(VJJn +
+
V,rf-
CL
kp(VoD + Vrl')
ln(l.9V0 n + 2V11 ,)
0.1 Vnn
No te that t1 is d irectl y proportional to th e load ca pacitance and inve rse ly proportiona l to th e V\/ 1,/L 1,
ratio of the P -c hann e l MOSFET.
Output Propagation Low-to-High
Delay Time == tPL 11
CL
+ kr (VDD+ V1•,,) ln(2)
Using the difference property of logarithms gives
Summing these terms gives the expression for the
time period required for a vo ltage change during the
output low- to-high transition as follows:
t:.t = ~t(SAT)
The output low - to-high propagation delay tim e is
defined as the time d e lay between V 1:-,.: dropping to
50% of V,:--.:.M,'\X and VoLT reaching 50% of Vu 11 . Since
a step input (instantaneous high - to-low switching of
the input) is used for this analysis, the output lowto-high propagation d e la y is the time th e output
takes to rise from Y0 1. to 50% of Vrn 1. Substituting
v~ = VOL = 0 and V4 = 0.SVoH = o.sv,)I) into the
output low -to - hi g h transi tion period expression
gives the expression for t 1,u I as follows:
+ t:.t(LIN)
-2CL(Vrp
+ V3)
kp(Voo + V-rr)2
+ -- -CL
- - - I n (Voo + 2Vn, +
krWoo + Vn ,)
Voo - V4
V,)
Note that the expression for the CMOS inverter low to-high transition delay is directly proportional to th e
load capacitance and inversely proportional to th e
PMOS device tran sconductance parameter kr. Since
kr = k{,(Wr/Lp), ~t for low -to - high transitions is in versely proportional to the PMOS channel width/
length ratio.
In (
V0 0 + 2Vn, + 0.SV,m)
Voo - 0.SVnn
-2CLV-rr
Once again, note that tl'LH is directly proportiona l to
Ci. and inversely proportional to the PMOS channel
width/length ratio.
23.8
Symmetry of Dynamic Response
To achieve a symmetric dynamic response, the
CMOS inverter should be designed with the same
rules presented for designing for a symmetric VTC
presented in section 23.5. Namely, the threshold
voltage magnitudes should be equal (VTN = -VTP)
and the Wp/Lp ratio of the P-channel device should
be 2.5 times the W:--;/LN ratio of N-channel device.
The following example demonstrates this.
Example 23.6 Dynamic Response of
Symmetric CMOS Inverter
Calculate t 1, t 1,f!L, t" and tPLH for the syn,metric
CMOS inverter of Example 23.2. Use a load capacitance of CL = 0.1 pF.
Example 23.7 Dynamic Response of CMOS
Inverter with a Larger Supply Voltage
Repeat the previous example with a supply voltage
of VDD = 10 V.
Solution The output fall time, high-to-low propagation delay time, rise time, and low-to-high propagation delay times are all found by direct substitution
t
= 2(0.lp)[(l) - 0.1(10)]
(80µ,)[(10) - (1))2
t
+
23.2 were VrN = 1 V and Vn, = -1 V. The device
transconductance parameters were calculated to be
k;-,; = kp = 80 µ,AN 2 . Substituting directly into the
expressions derived in this section gives
+
2(0.lp)(l)
(80µ,)[(10) - (1)]2
tl'/Jl.
(0.lp)
(0.lp)
l (1.9(5) - 2(1))
(80µ,)[(5) - (1)] n
0.1(5)
+ (80µ)[(10) - (1)]
-2(0.lp)[(-1) + 0.1(10)]
(80µ,)[(10) + (-1)]2
t = ------'-------'--------
2(0.lp)(l)
= (80µ,)[ (5) - (1)]2
r
(0.lp)
(0.lp)
I (1.5(5) - 2(1))
+ (80µ,)[(5) - (1)] n
0.5(5)
(0.lp)
ln[l.9(5) + 2(-1)]
(80µ,)[(5) + (-1)]
0.1(5)
-2(0.lp)(-1)
(80µ,)[(lQ) + (-1)]2
----~--PU/ -
(0.lp)
l [1.5(10) + 2(-1)]
0.5(10)
+ (80µ,)[(10) + (-1)] n
Note that these dynamic response times arc all about
-2(0.lp)(-1)
(80µ,)[(5) + (-1)] 2
(0. lp)
1/3 of those calculated with VDD = 5 V.
I [1.5(5) + 2(-1)]
0.5(5)
+ (80µ,)[(5) + (-1)] n
= 403 ps
t
= 164 ps
= 924 ps
=
0.1(10)
= 394 ps
-2(0.lp)[(-1) + 0.1(5)]
t =--~----/
(80µ,)[(5) + (-1)]2
tl'L/1
I [1.9(10) + 2(-1)1
+ (80µ,)[(10) + (-1)] n
= 403 ps
+
I (1.5(10) - 2(1))
11
0.5(10)
= 164 ps
= 924 ps
tl'I/L
(0.lp)
ln(l.9(10) - 2(1))
(80µ,)[(10) - (1)]
0.1(10)
= 394 ps
(80µ,)[(5) - (1))2
t
35 7
Note that t, = t, and tpm = tpui, which verifies symmetry of the dynan,ic response. Hence, the design of
the CMOS inverter for a symmetric VTC also provides a syn1metric transient response.
Solution The threshold voltages used in Example
t = 2(0.lp)[(l) - 0.1(5)]
CMOS Inverter Drnamic Response
The previous example shows that one way to
improve the dynamic response of a CMOS circuit is
to simply increase the supply voltage.
358
Chapter 23/CMOS Inverter
Example 23 .8 Dynamic Response of
Minimum Size CMOS Inverter
Calculate tr, tp 11 L, t" and tpu I for the minimum size
CMOS inverter of Example 23.4. Use a load capacitance of CL = 0.1 pF.
Solution The threshold voltages used in Example
23.4 are VTN = 1 V and Vrr = -1 V. The device
transconductance parameters are calculated to be
kN = 80 µ,A/V 2 and kp = 32 µ,A/V 2 . Substituting
directly into the expressions derived in this section
gives
-2(0.lp)[0.1(5) - (1)]
t, =
(80µ,)[(5) - (1))2
T
Tips, Tricks, and Gimmicks
Propagation Delays Are Directly
Proportional to Load Capacitances
The expressions for the high - to-low and lowto - high propagation delays for the CMOS inverter derived in section 23 .8 are directly proportional to the load capacitances and are
repeated here for convenience.
tp/lf .
=
2VTN
[ kN(V[)/) - VTN)2
0 2VTN)] C1+ - - -1- - - In (1.5Vo
----"'"'--------'-.:..:.
kNCV00
+
- (0 .lp)
I (
0.1(5)
)
(80µ,)[(5) - (1)] n 1.9(5) - 2(1)
tPIIL
=
+
0.5 Voo
= [
kl'(Voo + Vn,)2
+
1
kl'CVoo
-(0.lp)
In(
0.5(5)
)
(80µ,)[(5) - (1)]
1.5(5) - 2(1)
VTN)
-2V7"
ti'/ .//
= 924 ps
2(0.lp)(l)
(80µ,)[(5) - (1)]2
-
+ Vrr)
ln(l.5V/Jo + 2VTr)]cl
0.5Voo
·
These expressions in the forms stated here will
be used in the CMOS fan -out analysis presented in the following section.
= 403 ps
t,.
-2(0.lp)[(-1) + 0.1(5)]
(32µ,)[(5) + (-1)] 2
23.9
l [1.9(5) + 2(-1)]
+ - - -(0.lp)
~---n
(32µ,)[(5)
+ (-1)]
0.1(5)
= 2.3111S
-2(0.lp)(-1)
(32µ,)[ (5) + (-1) ]2
(0.lp)
l [1.5(5) + 2(-1)]
0.5(5)
The BJT fan-out analyses presented in the TTL and
ECL chapters den10nstrate that fan-out of BJT logic
circuits is limited by how much current a driving logic
gate can source or sink from the inputs of connected
load gates during either the output low or high state.
As was the case with the NMOS logic families in the
previous chapters,
the Jan-out limitation of a CMOS gate is
a question of how much load capacitance
can be driven and still have acceptable
propagation delays
+ (32µ,)[(5) + (-1)] n
= 1.01
/lS
Since the NMOS device has the same size and
threshold voltage, the fall tiITie t1 and high-to -low
propagation delay tl'HL are the same as the values for
the symmetric CMOS inverter in Example 23.5. The
rise time t, and low-to-high propagation delay tn 11
are approximately 2.5 times longer than tr and tl'HL·
This is no surprise, since the NMOS pull-down transistor and PMOS pull-up transistor have the same
W/L ratios and not the factor of 2.5 which is the ratio
of the electron and hole mobilities in silicon µ,NI µ,p.
CMOS FAN-OUT
Solving the propagation delay expressions (given in
the Tips, Tricks, and Gi111111icks box preceding this section) for the load capacitance CL results in two expressions as follows:
c,.
l,,(MAX)
= - -- - - ----'-'--- ~ - - - -2V.,N
kN(Vn,, -
and
Vm) -
-
-
1
(1.SV,,n - 2Vm)
kNWnn - Vm)
O.:,V,,o
-----,+----In
r
23.9
c,
lp(MAX)
= -----------------2VTr
1
(1.5Vno + 2Vr,,)
----- +----In ----k,,(V"" + Vrr) 2
kp(Vnn + Vr,,)
0.5Vou
where tp(MAX) was substituted for tPHL and tPLH·
tp(MAX) is the desired maximum propagation delay.
That is, tp(MAX) is the maximum propagation delay
that will result in acceptable performance for a specific inverter. The maximum acceptable load capacitance is then the lesser of the two.
If the response time of given inverter (for a given
load capacitance) is too slow, increasing the size of
the complementary MOSFETs will increase the
switching speed.
CMOS Fan-Out
359
the load inverter is to be determined. The parameters
for the load inverter are augmented with a prime.
The input capacitance of the load gate is equal to the
sum of the gate capacitances, or
CL = (WNLN + w;,L;,)c~x
For a symmetric inverter, Wp/Lp = 2.5 X WN/LN and
assuming that the length of all MOSFETs is equal to
2 µ,m, yields,
C1, = 3.5WN(2µ,)Cx
Solving for WN and substituting yields
W' N -
CL
3.5(2µ,)Cox
(0.5p)
3.5(2µ,)(690a)
-----'--- = 103.5
µ,m
The width of Pc'i is therefore
Example 23.9 CMOS Inverter Driving
(Fan-Out) Capability
What is the maximum load capacitance and the maximum size symmetric inverter that can be driven by
the inverter of Example 23.3 and have propagation
delay times of no more than 2 ns?
Solution (Maximum Load Capacitance) Assume that the length of all MOSFETs is 2 µ,m. The
threshold voltages and device transconductances for
the CMOS inverter of Example 23.3 are VTN = 1 V,
VTP = -1 V, and kN = kp = 80 µ,A/V 2 . Substituting
directly into the above expressions using a 2 ns propagation delay yields
c,
.
(211)
=--------------------c2(1)
1 - - l11 [1.5(5)
- 2(1)]
-----+ -----(80µ,)[(5) - (1)12
(80µ,)[(5) - (1)]
0.5(5)
w;,
(2.5) (103.5 µ,) = 258 µ,m
Thus, the maximum sized symmetric load inverter
has dimensions of WN/LN = 103.5µ,m/2µ,m and
Wr,/LP = 258µ,m/2µ,m.
Fan-Out of Same Sized Gates
In this section, an expression for the maximum fanout of a gate driving identical gates is developed. It
is assumed that the driving gate and the identical
load gates are symmetric to simplify the analysis.
For a symmetric inverter, VTN = IVTPI and
Thus,
CIN = 3.5WNLNC~x
= 497 fF = 0.5 pF
and
c,.
=
(211)
= -------------------2(-1)
1
[1.5(5) + 2(-1)]
------+------In
(S0,u)[(5) + (-1)]2
(80,u)[(S) + (-1)]
0.5(5)
If a symmetric inverter is driving F identical symmetric inverters such as shown in Figure 23.13, forming the ratio CdkN1 where
= 497 fF = 0.5 pF
yields
Thus, the maximum capacitance that can be driven
by the inverter of Example 23.3 and maintain propagation delays of no more than 2 ns is approximately
½ pF.
Solution (Maximum Size Inverter with Input
Capacitance of Half Picofarad) Figure 23.12
displays the situation in which the maximum size of
Substituting this expression for CdkN into the expression for tPHL stated in the Tips, Tricks, and Gimmicks box and solving for F gives
360
Chapter 23/CMOS Inverter
V'oo
W',L'PCO.X
___JI .
1,r
I
L ....'.
. I
I ► w_,P - ~.5W NP'
0
I
LP - 2µm
i-----
COP
Your= Y'm
r
C'oN
II , ,
L--11~
W I NL'NCOX I
1-v;,N
= W__N_ N'o
l
T
~ ~ N
'111~
"-P,H.O
I
= 3.5W'/2µm)C0 x
I.____
~-
~
- - ~ - _J
v·
load inverter
driving inverter
FIGURE 23.12 Determination of Maximum Size of (Symmetric) Load Inverter that Can Be Driven with a Maximum
Desired Propagation Delay
Y
Tips, Tricks, and Gimmicks
Propagation Delays Are Also
Inversely Proportional to the Device
Transconductances
The expressions for the high-to-low and lowto-high propagation delays for the CMOS inverter derived in section 23.8 are inversely proportional to device transconductances of the
driving inverter transistors and are repeated
here for convenience.
2VTN
[ (Vl)[) - VTN)2
1 In\(1.5Vo
+
V0
tru1
-
VTN
Example 23.10 Fan-Out of Same Sized
CMOS Inverters
How many identical inverters can the inverter of Example 23.3 (Figure 23.5) drive and maintain a maxns? This situation is
imun1 propagation delay of
depicted in Figure 23.13.
1.5
0
-
2VTN)] -Ci_
kN
Solution Substituting directly into the above expression yields
0.5Voo
-2Vrr
= [
(Voo + VT1,)2
1
where tl'(MAX) is the maximum desired propagation
delay.
(0.058)(1.511)
F=-------'-------------
(1.SVDD 2VTP)] -CL
+
+ - - - - - I n _ __::_____
(VDD + Vn,)
0.5Voo
kp
These expressions will be used in the CMOS
fan-out analysis presented in the following
sub-section.
"{
2(1)
1
3.5(2µ.)· ((5) - (1)f + (5) - (1) In
[15(5) - 2(1)]}
0.5(5)
= 19 3
Thus, the inverter of Example 23.3 can drive 19 gates
identical to the inverter of Example 23.3 and still
maintain a propagation delay less than 1.5 ns.
:?.'.UO
361
CMOS Inverter SPICE Simulation
V'DD
?
I
V'DD
20µm'C~x
-➔ I
d
I
lQ!!mP'02
C'o
12µ"m
r}
·-~~-y------~_J
V'oun
--0-
driving inverter
C'tjN L
2
8µm C0 x
V'oo
4µmN'
R2µm
.J,.
02
20µm'~ox
I
C'or
I
d
lOµmP' _
I
2µm o,
} I
V'aur;
-~-----------z_;
C'tjo
_
l,
8µmcox
I
4µmN,
112µm
'7
o;
I
\.____
----------~~------
______ __}
F identically sized load inverters
FIGURE 23.13
CMOS Inverter Driving F Identically Sized Inverters
23.10 CMOS Inverter
SPICE Simulation
Figure 23.14 displays a CMOS inverter with a capacitive load with appropriate SPICE labelings. The
SPICE CIRcuit file that represents this circuit is as
follows:
CMOS Inverter
VIN 7 D PULSE (DV 5V D 1NS 1NS
+ SNS 10NS)
VDD 8 D DC 5V
-MODEL PMOSFET PMOS(VT0=-1V
+ KP=16U GAMMA= □ -4 PHI= □ .6
CBD=3-1E-15 CBS=3.1E-15)
2 7 8 8 PMOSFET W=10U L=2U
-MODEL NMOSFET NMOS(VT0=1V
+ KP=40U GAMMA= □ -37 PHI=D-6
+ CBD=3-1E-15 CBS=3-1E-15)
MN◊ 2 7 DD NMOSFET W=4U L=2U
CL 2 D 1PF
-DC VIND 5 □ -1
-PLOT DC VDS(MNO)
-PLOT DC ID<MNO)
-TRAN □ -1NS 1DNS
-PLOT TRAN VDS<MNO)
-PLOT TRAN ID(MNO)
-END
+
MP◊
362
Chapter 23/CMOS Inverter
1r
Tips, Tricks, and Gimmicks
Voltage Transfer Characteristic
Midpoint Voltage Is a Function
of kN/kp
The expression for the voltage transfer characteristic midpoint voltage was in section 23.4
and is a function of the ratio of the transconductance parameters kN/kp and is repeated
here:
VDD
V
-
+
Vyp
+
VTN
(k:,
------✓~kr
1+
M-
(k:,
✓ kr
FIGURE 23.14 CMOS Inverter with Capacitive Load
and Appropriate SPICE Labelings
The VTC obtained from simulating this circuit is
shown in Figure 23.15a. Note that the VTC is symmetric about V00 /2. Thus, using a PMOS with Wp/Lp
2.5 times that of the NMOS WN/LN does indeed result in the symmetry discussed in section 23.5.
The current supplied by VDD is shown in Figure
23.15b. Current dissipation is limited to the voltage
range VTN < V 1N < V 00 - IVTPI and has a peak at
VD 0 /2. This corresponds to the input voltage at
which the VTC has maximum slope.
Figure 23.15c shows the input stimulus and resulting output voltage across the capacitive load for
the TRANsient simulation performed. Note that the
fall time, high-to-low propagation delay time, rise
time, and low-to-high propagation delay time all
correspond approximately to the values calculated in
Example 23.6 for a CMOS inverter with the same size
capacitive load.
Figure 23.15d shows the sum of the static and
dynamic currents supplied by VDD for the same time
interval as in Figure 23.15c. Observe that a current is
supplied by V00 only during the low-to-high output
transition. This is the time that the load capacitance
is charged through the pull-up P-channel MOSFET
P 0 . The load capacitance is discharged through the
pull-down NMOS device (during the high-to-low
output transition) to ground and hence does not
contribute to the 100V00 power dissipation.
This expression will be used in the following
section to aid in the design of CMOS inverters.
1r
Tips, Tricks, and Gimmicks
Propagation Delays Are Inversely
Proportional to Transconductance
Parameters
The expressions for the high-to-low and lowto-high propagation delays for the CMOS inverter derived in section 23.8 are directly proportional to the load capacitances and are
repeated here for convenience.
tp/-/L
2VTN
= [
kN(VDD - VTN)2
+
tl'Lf/
\]cL
1
ln(1.5Voo - 2VTN
kN(VDD - VTN)
0.5VDD
)
-2Vyp
= [
kp(VoD + VTl,)2
+
1
kp(VDD
+
Vyp)
ln(1.5VDD + 2Vyp)]cL
0.5VDD
These expressions will be used in the design of
CMOS inverters in the following section.
:?.3,]()
Cl'v!OS Inverter SPICE Simubtion
363
Vm(V)
•
I
Your (V)
4
5----
5
!
i
4
3
4
2
3
t(ns)
0
0
2
2
4
6
8
2
4
6
8
10
8
10
10
Yaur<V)
1
5
- -f-- --+---1- -
0
0
1
2
3
'--► Vm(V)
4
5
4
3
(a)
2
loo (µA)
-+-------+ t(ns)
toot
(c)
Ioo(mA)
80 .
7
60t
6
5
4
4oT
I
20----l-
3
2
1-
J
►
Vm(V)
5
0
(b)
FIGURE 23.15 Section 23.10 CMOS Inverter SPICE
Simulation Results: (a) Voltage transfer characteristic
from .DC sweep, (b) Static current dissipation from .DC
00
2
4
-+6
-• t(ns)
(d)
sweep, (c) Transient response from .TRAN sweep,
(d) Sum of static and dynamic currents supplied by V1m
364
Chapter 23/CMOS Inverter
23.11
DESIGN OF CMOS INVERTERS
In the previous sections of this chapter, the details of
DC and transient analysis of CMOS inverters is described. In this section, the design of CMOS inverters
is presented. The design of a CMOS inverter involves
two main considerations:
1.
placement of the voltage transfer characteristic
midpoint, and
2.
load capacitance drive capability
Transient Design
The Tips, Tricks, and Gimmicks box preceding this
section shows that the expressions for the high-to low and low-to -high propagation delays are inversely proportional to the transconductance param eters for the NMOS and PMOS devices, respectively.
Solving these two expressions for k:--: and kr yields
kN =
[
Fro m thi s expression, no te that V," is clearly a func tion of th e ratios of the device transconductance pa rameters . As discussed in section 23.5, if Vw =
-V7 :,.:, th en VTC symmetry is achieved with k;. .i = k1,.
Furthermore, as discussed in section 23 .6, k:,.: = kp
requires Wp/L" = 2.5 x W N/Lr-,.: .
Design of a Symmetric CMOS Inverter
Considering the preceding paragraphs, the process
for designing a CMOS inverter th a t will have both a
symmetric voltage transfer characteristic and sym metric tran sient response (tl'H1. = tpu~) is as follows:
•
2VTN
[ Wl)o - VTN)2
+
2Vrn
Woo - VTN)2
+
Dete rmine the N -channel MOSFET device
transconductance parameter kN by substituting VoD, V-rN, CL, and the desired maxi mum
t1,H1. into
1
in(1.5Voo - 2vTN)] C1.
Woo - VTN)
O.SVoo
trllL
1
ln(l.SVDD - 2Vm)] ii_
WoD - Vm)
O.SVDD
t,,111
•
Assuming that the minimum gate length for
the N-channel MOSFET is used, solve for the
width of the NMOS device from
•
Assuming the minimum gate length for the
P-channel MOSFET is used, solve for the
width of th e PMOS device from
and
-2Vrr
[ Woo+ Vn,)2
00 + 2V7 ,,)] C1.
1 - - In (1.5V
+ ----=~----'~
--
Won + V,-r)
0.SVoo
t,,111.
These expressions for kN and kl' as a function of sup ply voltage, threshold voltage, load capacitance, and
desired propagation delay are used to design the
transient response of a CMOS inverter.
w,, =
k;_,
W N k~
DC Design
The DC design of a CMOS inverter involves the
placement of the voltage transfer characteristic midpoint voltage . The expression for the CMOS inverter
midpoint voltage given in the preceding Tips, Tricks,
and Gimmicks box is
Voo + VT,,+ Vm
1+
/4i
{4
Ii,
Example 23.11
Design of CMOS Inverters
Design a symmetric CMOS inverter that can drive a
capacitive load of CL = 25 pF with propagation delays of no more than tr = 2 ns. Use V 00 = 5 V,
V1:,.; = 1 V, Vw = -1 V, k~ = 40 µ,AN 2 , k(, =
16 µ,AN 2, and assume a minimum gate length of
L,,,; = 2 µ,m is used for both transistors. Round off
the transistor gate widths to micron accuracy.
11
Solution Substituting values into the time -depen dent expression for k:--: gives
23.11
2(1)
1
k\, = { [(5) - (1))2 + (5) - (1)
Design of CMOS Inverters
365
The inverter desig11ed in this example is shown in
Figure 23.16 along with an inverter design in the fol
lowing example.
(25p)
1.5(5) - 2(1)]} 0.5(5)
(211)
In-----
[
111A
= 4.03 -.,
Example 23.12
v-
The resulting NMOS gate width is then
WN
=
(4.03111)
(2µ) - (40µ)
=
201.5 µ111
The PMOS gate width is
(40µ)
Wr = (201.5µ) -(- ) = 503.75 µ,m
16µ
Rounding widths off to the nearest micron gives
202
2
j.L/11
504 µm
2 µm
and
j.L/11
Design of CMOS Inverters
Design a symmetric CMOS inverter that can drive
the input of the CMOS inverter of Example 23.11
with propagation delays of no more than tp = 2 ns.
Again, use VDD = 5 V, VrN = 1 V, Vrl' = -1 V,
k~ = 40 µAN 2 , k(, = 16 µAN 2, and assume a minimum gate length of L111 ; 11 = 2 µm for all MOSFETs.
Also, assume a gate capacitance per unit area of C 0 x
= 690 aF/ µm 2 and round the gate widths up to the
nearest micron.
Solution (Load Capacitance) The load capacitance to be driven is the input capacitance of the
inverter of Example 23.11, given by
Li.=4=Lnii.=2µ.m
L'ttzVl'::::.L,...=2µm
Wr=2.5WN
. W'~=-2,SW'-,.
V',,,,
25pF
Input
of
Example
load
inverter is
capacitance
on
Example 23-J2- inverter
inverter designed
in Example 23.12
FIGURE 23.16
inverter designed
in Example 23.11
CMOS Inverters Designed in Examples 23.11 and 23.12
366
Chapter 23/CMOS Inverter
k
= [(202µ,) (2µ,) +
= 974.3 JF
(504µ,) (2µ,))(690a/ µ, 2)
_ {
N
-
2(1)
[(5) - (1)]2
+
1
(5) - (1)
ln[l.5(5) - 2(1)]} (50p)
0.5(5)
(111)
Solution (Design of New Inverter) Substituting
values into the time-dependent expression for kN
gives
mA
= 16.1 v 2
2(1)
1
kN = { [(5) - (l)f + (5) - (1)
WN
=
(16.lm)
(1µ,) (100µ,)
=
161.1 µ,111
and the PMOS gate width is
(40µ,)
We
= (161.lµ,) -(- ) = 402.75 µ,m
16µ,
The MOSFET sizes for this inverter are therefore
WN = 161.1 µ,nz
LN
l µ,111
Fron, the gate width expression (WN = LminkN/kr'.i),
the resulting NMOS gate width is
and
Wp = 402.1 µ,m
Lp
l µ,m
Solution (b) The input capacitance of inverter designed in (a) is
CL
Similarly, the PMOS gate width is
= c; N = Cc,N + Cc,P = (WNLN + W~L~)Cx
= [(161.1µ,)(lµ,) + (402.lµ,)(lµ,)](1.739f/µ, 2 )
=
Rounding widths off to the nearest micron yields
WN
=
LN
8 µ,m
2 µ,m
and
WI'
Lp
=
20 µ,m
2 µ,111
The inverters of this and the previous example are
shown cascaded in Figure 23.16.
978
JF
Substituting values into the time-dependent expression for kN gives
k _ {
N -
+
2(1)
((5) - (1)] 2
1
(5) - (1)
ln[l.5(5) - 2(1)]} (978fp)
0.5(5)
(ln)
µ,A
= 315 v2
Example 23.13
Design of CMOS Inverters
UsingV 00 = 5 V, Vrn = 1 V, Vw = -1 V, kr'.i = 100
µ,A/V 2, kf = 40 µ,A/V 2, minimum gate lengths of
Lmin = 1 µ,m, and a gate capacitance per unit area of
1. 739 fF/ µ,m 2 design CMOS inverters with the following characteristics:
(a) CL
tp
= 50 pF with maximum propagation delay of
= 1 ns,
(b) Another CMOS inverter to drive the CMOS inverter of (a) with a maximum propagation delay
of tp = 1 ns.
Solution (a) Substituting values into the time-dependent expression for ki'-: yields
The resulting NMOS gate width is
(315µ,)
WN = (1µ,) (100µ,) = 3.2 µ,111
and the PMOS gate width is
(100µ,)
Wp = (3.2µ,) -(--) = 7.9 µ,m
40µ,
The MOSFET sizes for this inverter are therefore
WN = 3.2 µ,m
LN
1 µ,111
and
Wp = 7.9 µ,m
Lp
l µ,111
The inverters designed in (a) and (b) are shown in
Figure 23.17.
23.12
23.12
CMOS LATCH~UP
A parasitic problem associated with CMOS circuits
is referred to as latch up. This is a condition in which
a large sustained current can exist between V00 and
ground which can cause inappropriate operation and
often overheating with possible destruction of the
circuit.
Figure 23.18 displays the basic cross section of a
CMOS inverter with circuit connections. Note that
bipolar circuit elements are also shown in the crosssection that represent parasitic devices due to NPN
and PNP adjacent regions. The BJT Q1 on the right
is a vertical NPN, the BJTs in the middle Q2 and Q3
are lateral NPN and PNP BJTs, respectively and the
BJT Q 1 on the left is a lateral PNP, as indicated. In
Figure 23.18, the collector of Q3 is connected to the
base of Q2 and the collector of Q2 is connected to
the base of Q3 . Additionally, there is a similar con-
Vf)V
V'r,r,
V'
Input capacitance of
Example 23.13a inverter
is load . capacitance ··on
Example 23.Bb inverter
·····························-.yr·····
FIGURE 23.17
CMOS Inverter Design for Example 23.13
367
nection between Q 1 and Q,1. These parasitic BJTs are
then interconnected to the CMOS inverter.
Figure 23.19 displays the overall circuit diagram
in which parasitic shunt resistors have also been
added. If sufficient current can flow through these
resistors and if sufficient resistor magnitudes exist,
then the emitter-base junction of Q4 and Q2 as well
as Q 3 and Q 1 can become forward biased to Vm:(FA)
or V8 E(SAT). Once this occurs for the pair of BJTs Q,1
and Q2 or Q 3 and Qi, the base current of each
MOSFET is increased and this current is amplified
resulting in larger collector current and larger base
current for the other BJT in the pair. This is a regenerative process (a positive feedback process) which
results in a large current and this is the condition
called latch up.
To understand how the CMOS circuit can be induced into latch up, consider Figure 23.19. There are
two ways in which the latch up mechanism can oc-
"·······<:...... our
inverter designed
in Example 23.13b
CMOS Latch-Up
inverter designed
in Example 23.13a
368
Chapter 23/CMOS Inverter
Q,
)
I
\___ ~-------+-----------+-P~w~e~II-------
1
Q.
~N substrate
----------
FIGURE 23.18
Basic CMOS Cross Section with Parasitic BJTs
FIGURE 23.19
CMOS Inverter Circuit with Parasitic BJTs and Resistors
23.13
cur. First, for Vuui = 0 = VOi_, it is possible for the
combination of Q 4 and Q 2 to conduct a large current.
This possibility occurs because of the large voltage
difference between the power supply terminal and
the output terminal. If this voltage difference is sufficient to forward bias the base-emitter junction of
Q 2 and Q4 to Vl-lE(FA), then each of these transistors
is driven into either the forward active or saturation
mode of operation. Under these conditions, large
emitter and collector currents are possible, creating
the latch up condition. The second way in which
latch up can occur is when VoUT = VoD = Vrn 1. Then
a large voltage difference is produced from the output terminal to ground which may force Q 3 and Q 1
to conduct a large current producing a similar latch
up condition.
The latch up condition is avoided by intentionally reducing the BJT current amplification f3 factors,
as well as reducing the shunt resistance values. The
twin tub fabrication process described at the beginning of this chapter effectively provides these reductions.
23.13 ELECTRO-STATIC DISCHARGE
AND INPUT
CLAMPING SECTIONS
Electro-Static Discharge
CMOS circuitry is inherently prone to damage because of static charge that can build up on the gates
of the NMOS and PMOS devices at the input pins
of a CMOS integrated circuit. A voltage across the
Si0 2 layer of a MOSFET is directly dependent upon
the charge build up and gate capacitance, as follows:
Electro-Static Discharge and Input Clamping Sections
369
The electric field that can result from static charge
buildup is enormous and can be large enough to
cause breakdown of the dielectric. As a result, the
oxide layer will rupture, permanently shorting the
gate conductor to the channel causing permanent
damage to the MOSFET. This is referred to as electro-static discharge.
Causes of Static Charge Buildup
Static charge sufficient to breakdown the gate oxide
of input MOSFETs can be caused by simply touching
the pins of an integrated circuit package without protective gloves. Rubbing the leads together can also
cause an enormous static charge buildup. Special
handling and packing procedures are therefore necessary when dealing with CMOS integrated circuit
packages. Shipping packages which short all the
leads of the IC to each other prevent static charge
buildup.
A technique used to protect the internal circuitry
of a CMOS IC is input diode protection. The purpose of diode protective circuitry is to limit the range
of input voltages.
Metal Gate MOSFET Input Diode
Protection Circuitry
Figure 23.20 shows a protective circuit used with
metal gate MOSFET processes. The diode D11 prevents the input from swinging above V00 +
where the gate capacitance has magnitude
CMOS
circuitry
Since modern MOSFETs have an oxide thickness on
the order of t x = 200 A, the voltage resulting from
a static charge buildup can be as high as hundreds
of volts.
The electric field is related to this voltage across
the Si0 2 by
0
V:-11111w·
E=___Q_
tax
~ - - , ~~~--- .-/
.
________.....,
diode protection circuitry
FIGURE 23.20 Diode Input Protection Circuitry for
Metal-gate CMOS
370
Chapter 23/CMOS Inverter
VDD
VDD
0
f
I
*
t
D,
D,
VPIN
RroLY
r,
CMOS
CMOS
circuitry
11/
1~;
circuitry
DL
-::-
(a)
(b)
FIGURE 23.21 Diode Input Protection Circuitry for Silicon Gate CMOS: (a) Circuitry, (b) D1. is layed out as a basecollector connected BJT diode
VDH(ON). Likewise, the diode DL prevents the input
from swinging below -VDL(ON) (similar to the input
clamping diodes of TIL logic families). The input resistor R1, which is typically 250 fl, limits current flow
during a high voltage static discharge and prevents
a large input voltage from being directly applied to
the gates of the input MOSFETs. The diode DD is a
distributed PN junction resulting from the diffusion
fabrication of R1 and doesn't contribute to the input
protection.
For normal operation (0 s Vu-..: s VDD), the input
diodes have no effect because they are reverse biased
and never turned on. Furthermore, the protective diodes are designed to have very large breakdown
voltages, thus preventing conduction when reverse
biased.
Silicon Gate MOSFET Input Diode
Protection Circuitry
Figure 23.21a displays the input diode protective circuitry used for silicon gate MOSFET processes. Since
the resistor R1,my is a polysilicon resistor, a distributed diode DD present in the metal gate MOSFET
process is avoided. The diodes DH and DL serve the
same purpose as in the metal gate MOSFET protective circuitry.
Figure 23.21b displays the circuitry actually used
in typical silicon gate MOSFET processes. The diode
D1. is a BJT with the base and collector connected.
This protective circuitry is connected between the IC
input pad (which is bonded to the external pin) and
the input of the CMOS circuitry.
CHAPTER23PROBLEMS
23.1
23.2
23.3
What are the states of N 0 and P0 for the CMOS
inverter for each of the VTC critic<1l points V011 ,
VoL, V1L, vlf-{, and v~·I·
For the CMOS inverter shown in Figure P23.2,
graphically determine the critical voltages V011,
VoL, V11,, V111, and VM. Let VDD = 5 V, VT.N = IVryl
= 1 V, W:--/LN = 5, Wp/LI' = 2.5, and k;'.; = k(, =
20 µA/v2.
For the CMOS inverter shown in Figure P23.2, analytically determine the critical voltages Vmi, VoL,
V1L, V1H, and v~I- Let VDD = 5 V, VT,N = IVT,PI =
1 V, WN/LN = 5, Wp/Lp = 2.5, and k(i = k{, =
20 µ,A/V 2 . Sketch the VTC and determine the noise
margins.
23.4
Repeat Problem 23.2 for V1m = 10 V,
23.5
Repeat Problem 23.3 for VDD = 10 V,
23.6
Repeat Problem 23.2 for VDo = 7 V.
23.7
Repeat Problem 23.3 for VDn = 7 V.
23.8
Repeat Problem 23.2 for WN/LN = 1.5 and W1,/Lp
= 7.5.
Chapter 23
Problems
371
Would such a circuit configuration be useful7 (Hint:
Sketch the VTC from - 2 to 7 V using VDI) = 5 V,
V 1.N = -1 V, and Vr.1' = 1 V.) (Hint 2: Run a SPICE
simulation and sec if the MOSFETs cutoff.)
23.9
Repeat Problem 23.3 for W 1.)Lr--: = 1.5 and W1,/LI'
= 7.5.
23.10
Repeat Problem 23.2 for WN/LN = 2 and W"/Lp
= 6.
23.11
Repeat Problem 23.3 for Wr-.:/LN = 2 and Wp/L 1,
= 6.
23.12
Repeat Problem 23.2 for a minimum sized CMOS
inverter with k~ = 20 µA/V 2 , k(, = 8 µ,A/V 2, and
WN/LN = W1,/Lp = 1.5.
23.13
Repeat Problem 23.3 for a minimum sized CMOS
inverter with k~ = 20 µ,A/V 2, k(, = 8 µ,A/V 2, and
Wr-.:/LN = Wp/Lp = 1.5.
MP◊
23.14
What ratio of Wr/L" should be used for a CMOS
inverter with k~ = 20 µ,A/V 2, k{, = 12 µ,A/V 2, and
W N/Lr-.: = 2 to give a symmetric VTC 7
and simulate the CMOS inverter of Example 23.1.
Compare the simulation results with the analytical
results of Example 23.1.
23.15
Repeat Problem 23.14 for W:,JLr-.: = 3.
23.16
Repeat Problem 23.14 for Wr-.:/LN = 4.
23.17
Repeat Problem 23.14 fork~= 20 µ,A/V 2 and k{, =
8 µ,A/V 2 .
23.23
Modify the N- and P-channel MOSFET element
lines (not the model statements) of the SPICE simulation of section 23.8 to
MN◊
23.19
Resimulate the SPICE circuit of section 23.5 for a
capacitive load of
CL 2 D 1DPF
MN◊
Would there be any advantage in using enhancement-depletion
N-channel
and
P-channel
MOSFETs in a CMOS pair, as in Figure P23.21?
2 7 8 8 PMOSFET W=4U L=2U
2 7 DD NMOSFET W=4U L=2U
and simulate the minimum size CMOS inverter of
Example 23.3. Compare the simulation results with
the analytical results of Example 23.3.
23.25
Calculate tr, tp 1IL, t., and tpu 1 for a CMOS inverter
with a capacitive load of 0.1 pF. Let V1m = 5 V,
Vr.N = JVul = 1 V, k~ = 40 µ,A/V 2, k(, = 16 µ,A/V 2,
WN/L" = 2, and Wp/L 1, = 5.
Resimulate the SPICE circuit of section 23.5 for a
capacitive and resistive load of
RL 2 D 1DMEGOHM
CL 2 D 1DPF
2 7 8 8 PMOSFET W=8U L=2U
2 7 DD NMOSFET W=4U L=2U
Modify the N- and P-channcl MOSFET clement
lines (not the model statements) of the SPICE simulation of section 23.8 to
MP◊
2
Repeat Problem 23.14 for kr'.J = 20 µ,A/V and k(, =
15 µ,A/V 2 •
23.21
Find the input low and high voltages for the CMOS
inverter of Example 23.2 and verify their symmetry
about the midpoint voltage.
23.24
23.18
23.20
23.22
23.26
Repeat Problem 23.25 with VnD = 10 V.
23.27
Repeat Problem 23.25 with WN/LN = 4 and Wp/Lp
= 10.
23.28
Repeat Problem 23.25 with Wr-.:/L" = 10µ,m/2µ,m
and Wp/Lp = 25µ,m/2µ,m.
v"'
FIGURE P23.2
FIGURE P23.21
372
Chapter 23/CMOS Inverter
23.29
Repeat Problem 23.25 with W,)L'-l
and W 1,/L" = 4µ,m/2µ,m.
= 4µ,m/2µ,m
23.30
Repeat Problem 23.25 with W:-,;/Lr--:
and W 1,/L" = 10µ,m/2µ,m.
= 10µ,m/2µ,m
23.31
Repeat Problem 23.25 with VDD = 10 V, Wr--:/LN =
10µ,m/2µ,m, and Wp/Lp = 10µ,m/2µ,m. Compare
with solution to Problem 23.30.
23.32
What is the maximum load capacitance that can be
driven by an inverter with VDD = 5 V, VT,N = IV1 ,PI
= 1 V, k~ = 40 µ,A/V 2, ki, = 16 µ,A/V 2, W:--:iLr--: =
4J.@l2J.tm, and W,/Lr = 101,im/2µ,m 7 Consider
propagation delays of no more than 2 ns.
23.33
Repeat Problem 23.32 using V1m = 10 V.
23.34
What is the maximum load capacitance that can be
driven by an inverter with VDD = 5 V, VT.N = IVryl
1 V, k~ = 40 ,u.A/V 2, k~ = 16 vA/V 2, W:)L,-: =
10µ,m/2µ,m, and Wp/L" = 25µ,m/2µ,m? Consider
propagation delays of no more than 2 ns.
=
23.35
Design a CMOS inverter that can drive a capacitive
load of CL = 10 pf with propagation delays of no
more than 5 ns. Use VDo = 5 V, VT,N = IVT,rl = 1
V, k:'.; = 40 µ,A/V 2, K[, = 16 µ,A/V 2, and minimum
gate length of Lmin = 2 µ,m.
23.36
Repeat Problem 23.35 using Vno = 10 V.
23.37
Repeat Problem 23.35 using a minimum gate
length of Lmin = 1 µ,m.
23.38
Design a CMOS inverter that can drive a capacitive
load of CL = 20 pf with propagation delays of no
more than 5 ns. Use VoD = 5 V, VT,N = IV-r,PI = 1
V, k,'.; = 40 µ,A/V 2 , ki, = 16 µ,A/V 2 , and minimum
gate length of Lmin = 1 µ,m.
CMOS
COMBINATIONAL
LOGIC GATES
The previous chapters introduced the CMOS logic
family and detailed the operation, analysis, and design of the CMOS inverter. This chapter presents the
structure of multi-input CMOS gates such as
NANDs, NORs, and more complex AND-ORinverts (AOis). As will be seen, ANDing of signals is
obtained by series drain-source combinations of
N-channel MOSFETs and parallel drain-source
combinations of the complementary P-channel
MOSFETs. ORing of signals is accomplished in
CMOS by parallel drain-source combinations of
NMOS transistors along with series drain-source
combinations of the complementary PMOS transistors. Special function CMOS gates such as tri-state
logic and high impedance Z-state gates, bi-directional transmission gates (switches), Schmitt inverters, and drivers are presented in Chapters 25, 26, and
27.
24.1 CMOS INVERTER PULL-UP
AND PULL-DOWN REVIEW
The previous chapter described the details of the
CMOS inverter shown in Figure 24.5 using the shorthand symbolism. A low input voltage turns on the
P-channel MOSFET and an output pull-up path to
Vlm is available through the PMOS drain-to-source
channel. A high input voltage turns on the N-channel MOSFET and the drain-to-source channel of the
NMOS device provides an output pull-down path to
ground. Note that when the input is low, the PMOS
device is active and the NMOS transistor is cutoff
and when the input is high, the NMOS transistor is
active, while the PMOS transistor is cutoff. Thus, for
the output high and low states, both devices are
never on simultaneously and output pull-up and
pull-down paths never conflict during operation of
the CMOS inverter.
373
1f
Tips, Tricks, and Gimmicks
N- and P-Channel MOSFET
Symbol Shorthand
N-channel MOSFET Symbol Shorthand
In section 16.3, it was shown that an N-channel MOSFET is a physically symmetric device
and either terminal at the end of the channel
can be considered the drain or the source depending upon the polarity of the drain-source
voltage (see Figure 16.5). In the Tips, Tricks, and
Gimmicks box at the beginning of Chapter 22,
a shorthand symbol for N-channel MOSFETs
that depicts this symmetry was described and
shown in Figure 22.2. It is also convenient to
use this shorthand symbolism in the present
chapter for CMOS logic circuits.
Figure 24.1 shows a cross-section of an
N-channel MOSFET as it would occur in a
CMOS process along with the circuit symbol.
Most often, CMOS integrated circuits use an
N-type substrate and NMOS devices in CMOS
integrated circuits are constructed inside
P-type wells as shown in Figure 24.lb. Because
of the symmetry, then-type regions at the ends
of the channel are not defined as drain and
source until a bias is applied. Upon application
of a drain-to-source bias, the drain is the terminal at higher potential and the source at
lower potential. The body region of the P-type
well of the N-channel MOSFET is connected
to ground. Figure 24.2 shows the N-channel
MOSFET symbol with the body terminal connected to ground and the shorthand symbol
used for N-channel MOSFETs in NMOS and
CMOS integrated circuits. As in the NMOS
Gates chapter, the body terminal is removed
and the body is assumed to be at ground. Also,
374
Chapte r 24/CM0S Combinational Logi c Cates
th e das hed line in th e ge neral circu it sym bo l
representing the enhancement channel is re placed with a solid line.
P-cliannel MOSFET Shorthand Symbol
A P-channel MOSFET is also represented with
a shorthand symbol. Figure 24.3 shows the
general PMOS circuit symbol and cross-section
as would be present in a CMOS integrated circuit. This device also exhibits symmetry and the
p- typ e regions at the e nds of th e cha nn el can
be either the drain or source. With a P-channel
MOSFET, the channel end at lower potential is
the drain and the source is the end at the
higher potential. The body of the PMOS tran sistor (the CMOS integrated circuit substrate)
is held at the source voltage VDD · Figure 24.4
shows the P - channel MOSFET circuit symbol
with the body connected to VDD, along with the
shorthand symbol used for a P -channel
MOSFET in CMOS integrated circuits. The
dashed line representing the enhancement
channel is again replaced with a solid line. The
body terminal is also removed but for PMOS
devices the body is assumed to be at V DD· To
distinguish from the NMOS shorthand symbol,
an inverting bubble is placed on the gate terminal of the PMOS shorthand symbol, as
shown in Figure 24.4 .
Figure 24.5 displays a CMOS inverter us ing the NMOS and PMOS shorthand circuit
symbols.
24 .2
CMOS NAND GATE
CMOS NAND Gate Circuit
Figure 24.6a shows a two-input CMOS NAND gate.
Ignore the W /L ratios for the present discussion . (The
symbol shorthand for each transistor is used with the
source and drain of each labeled for convenience .)
Output pull -up to VDD is provided by two P-channel
MOSFETs with their drain-to-source channels in
parallel. Two N-channel MOSFETs with their drain to-source channels in series provide output pulldown to ground. Tiie gate terminal of each PMOS
transistor is connected to the gate terminal of a sep arate N -channel MOSFET, with these device pair
connections serving as inputs to the CMOS NAND
gate circuit. Note that each input is accommodated
by a separate CMOS complementary pair. TI.e logical NAND output VNAND is taken at the node between the stacked NMOS pull - down devices and the
parallel PMOS pull-up devices. The truth table for
the logical NAND function shown in Table 24.1 is
verified by examining the state of the output for all
combinations of input states.
Output High State
First, we show that the output high state is obtained
for the CMOS NAND gate of Figure 24.6a for any
input low as follows:
Both Inputs Low
When both inputs are low, Vsc. r for both P-channel
MOSFETs is sufficient to bring both PMOS transis -
drain or
source
gate o--
--1:
J
1
body (p w,11)
N
source
or drain
(a)
FIGURE 24.1 N-channel Enhancement-only MOSFET
in a CMOS P-well Process is Physically Symmetric,
Channel End at High Potential is Drain, Lower Potential
Channel End is Source: (a) Circuit symbol, (b) Cross-
(b)
section: CMOS process uses an N-type substrate, NMOS
device is constructed inside a P-type well (P-well is
connected to ground)
24.2
CMOS NAND Gate
375
drain or
source
drain or
source
body implied
~ atground
)
0
0
source
or drain
source
or drain
(b)
(a)
FIGURE 24.2 N-channel Enhancement-only lv!OSFET
Symbol Shorthand: Dashed line representing
enhancement channel is replaced with a solid line; body
terminal is removed and assumed at ground: (a) Four
terminal circuit symbol, (b) Three terminal shorthand
symbol
source
or drain
f
gate o--
--1 i ~-
drain or
--D
l
gate
body (substrate)
p
drain or
source
(a)
(b)
FIGURE 24.3 P-channel Enhancement-only MOSFET
(in a CMOS process) is Physically Symmetric, Channel
End at Lower Potential is Drain, Higher Potential
~,
source
or drain
I
source
or drain
body implied
at Y00
Yoo
~
Ii
Channel End is Source: (a) Circuit symbol, (b) Crosssection
p
6
drain or
source
(a)
FIGURE 24.4 P-channel Enhancement-only MOSFET
Symbol Shorthand: Dashed line representing
enhancement channel is replaced with a solid line; body
terminal is removed and assumed at VDD; P-channel is
I
0
drain or
source
(b)
denoted by inverter bubble on gate channel line: (a) Four
terminal circuit symbol, (b) Three terminal shorthand
symbol
376
Chapter 24/CMOS Comb in a tion ,d Logic Gates
Yoo
r' PMOS source at higher voltage
M [sJ ◄------at
◄--- PMOS body V 00
______ _ _ __ _ PMOS drain at
I -,
0
lower voltage
VIN
-0
G
equ al to th e dra in current of Nil (and N A)· With Nn
cutoff for both inputs low, the sum of th e PMOS
drain currents is
VN~
NMOS drain at
higher voltage
D
.._ _ NMOS body at ground
I
NMOS source at lower voltage
------
With each drain current zero, the source-to -drain
voltages of bo th P-channel MOSFETs are VsD.I',\ =
VslJ,I',\ = 0 (as was found with the CMOS inverter)
and the output high voltage for the CMOS NAND
gate is
V011 (CMOS NANO) =
Vim
VA Low, Vu High
FIGURE 24.5 CMOS Inverter with NMOS and PMOS
Shortha nd Symbols
tors into active operation. Therefore, output pull-up
paths to V1)1) are provided by both P -channel
MOSFETs. Also, with VA and VTl input voltages low,
Vcs,A and Vcs. B are low enough to cutoff NA and N 11
and no output pull-down path is available. Thus, the
CMOS NAND gate of Figure 24.6a is in the output
high state for both inputs low.
Output High Voltage
= VoH
With a si ngle input low, an output pull - up path to
V1m exists through the drain-to-source channel of
the corresponding P-channel MOSFET (PA in this
case). If V,\ is low (less than V 1.:s:) then Vc.s.:s:A is in sufficient to turn on N,\· With N 1\ cutoff, no conduc tive path exis ts from ground to the source of NB.
H e nce, regardless of V13, no o utput pull -down path
to ground exists . Therefore, with V,, low and V11 high,
the NAND ga te of Figure 24.6a is still in th e ou tput
high state.
VA High, Vu Low
Examining th e circuit of the CMOS NAND gate of
Figure 24.6a, th e sum of th e PMOS drain currents is
As shown for the previous case, a single input low
places the corresponding PMOS transistor in active
Yoo
_I -
~ ~·i~
µmp A
--zjiin
~J
IOµmp
--zjiin B
}
p~,11,1 PMOS pull-up
!
---0
i
VNAND
D
v.
~~N.
stacked NMOS pull-down
~
VA
0
If
~NA
sl
J.'-----y-----/
CMOS pair A
-~
CMOS pairB
(a)
FIGURE 24.6
symbol
:LY-F
(b)
Two-input CMOS NANO Gate: (a) Schematic with W/L ratios specified in microns, (b) Logic circuit
24.2
CMOS NAND Gate
377
TABLE 24.1 States of Each N-Channel and P-Channel MOSFET and Presence of Output Pull-Up
and Pull-Down Paths in the Two Input CMOS NANO Gate of Figure 24.6a for All Combinations
of Low and High Inputs
VA
Vs
NA
Ns
PA
Ps
Pull-Up Path(s)
Pull-Down Path
YouT
low
low
high
high
low
high
low
high
off
off
on
on
off
on
off
on
on
on
off
off
on
off
on
off
PA, Pl/
pi\
Ps
none
none
none
none
NA and Ns**
high
high
high
low
*For VA and VB low, two output pull-up paths to VDD are present through PA and PB
**For VA and VB high, a single output pull-down path to ground through NA and NB is present
operation and provides an output pull-up path to
VDo through the drain-to-source channel of the active P-channel MOSFET (P 11 in this case). With VA
high, Yes.NA is sufficient to put NA in active operation
and a highly conductive path from ground to the
source of NB exists. With V8 low, Vcs.NB is insufficient
to turn on N 13 • With NB cutoff, no output pull-down
path to ground is available. Hence, with an output
pull-up path to V00 present and no output pulldown path to ground, the NAND gate is in the
output high state.
Note that with NA active and N 8 cutoff, the drain
current through NA and NB is lo.NA = lo.NB = 0. As
shown in section 17.2 and discussed in the CMOS
inverter chapter, an active MOSFET with zero drain
current has a drain-to-source voltage of O V. Hence,
it should be noted that with NA active and Nil cutoff,
the source of N 8 is at a virtual ground. This fact is of
dynamic consideration later in this section.
Summarizing, we note that if either or both inputs of the CMOS NAND gate of Figure 24.6a are
low, then this gate is in the output high state.
Output Low State
Both Inputs High
If both inputs of the CMOS NAND gate of Figure
24.6a are high, NA and NB are both active. This results in an output pull-down path to ground through
the series drain-to-source channels of N,\ and Nli•
With both inputs high, the source-to-gate voltages
of both PA and P 8 are insufficient to bring them into
active operation. With PA and PB both cutoff, no output pull-up path to VDD is available. Hence, with
both inputs high, the NAND gate is in the output
low state.
Output Low Voltage
= VoL
Since the drain current of NA (and N 8 ) is equal to
the sum of the drain currents of PA and PB, with P,\
and PB cutoff, the drain currents of NA and Nii are
zero and
Since NA and N 8 are active with drain currents zero,
the drain-to-source voltages are also zero (as discussed in section 17.2). With VDs,NA = VDs,NB = 0,
the output low voltage is
VOL(CMOS NAND) = 0
NANO Function Realization
With the output high for any input low and the output low only for both inputs high, the truth table for
a two input NAND gate (shown in Table 24.1) is
verified. Hence, the logical NAND function is realized by the circuit of Figure 24.6a. The output state
of each MOSFET in the CMOS NAND gate of Figure
24.6a for the four combinations of low and high inputs is also tabulated in Table 24.1. The logic circuit
symbol for this gate is displayed in Figure 24.66.
Pull-Up and Pull-Down Paths
are Exclusive
For static operation (all inputs held constant at Vm
or V0H), an output pull-up path to VDo or an output
pull-down path to ground is always available. Also,
pull-up and pull-down paths are never available simultaneously. These two facts are also true for
CMOS inverters and as we shall see for CMOS NOR
gates and complex AOis, as well.
378
Chapter 24/CMOS Combinational Logic Gates
Example 24. i NAND Gate Used
as Enabling Inverter
Show that a two-input NAND gate can be used as
an inverter with an enable with one input serving as
the logical input and the other input used as an active
high enable input. At what state is the gate held
when the enable input is low (off)?
Solution Examining the NAND function truth table of Table 24.1, if the logic state A is held low, the
output of the gate is high regardless of the state of
B. If the A input is held high, then the output acts as
an inversion of the B logic state.
If a low output state is desired for the unenabled gate, the NAND output can be fed into an
inverter.
Ordering of Inputs
The previous example sheds light on the ordering of
inputs to the CMOS NAND gate of Figure 24.6a. If
the NAND gate is intended to be used as an enabling-inverter, the enable signal should be the input
to the NMOS device at the bottom of the stack and
the logical signal should be the input to the NMOS
device at the top of the stack. The reason for this is
because of the dynamic switching characteristics of
CMOS NAND gates. Enable signals will in general
switch less often than logic signals. Observing Figure
24. 7b, with the bottom NMOS device active, the
source of the top NMOS device is at virtual ground,
as discussed earlier in this section. The switching
speed of the NAND gate due to the logical input is
then the switching speed of the simpler inverter. If
the enabling input used the top NMOS transistor
and the enable signal is high, for the output to switch
due to a change in the logical input, the switching
speed is dependent upon the sum of the switching
speeds of both N-channel MOSFETs. This demonstrates that the input that switches least often should
be connected to the CMOS pair that has the bottom
of the stack N-channel MOSFET.
Channel Width/Length Ratios
In section 23.5, it was shown that the PMOS Wp/Lp
ratio should be approximately 2.5 times the NMOS
Wt--.!/L:-,; ratio to achieve a symmetric voltage transfer
characteristic for the CMOS inverter. As mentioned,
this is due to the relative mobilities of electrons and
holes in the channels of N- and P-channel silicon
MOSFETs, where
/J-N
=
(in silicon)
2.5µ,p
For a two-input CMOS NAND gate, the output pulldown path is through the drain-to-source channels
of two NMOS devices in the NMOS stack. The out-
f
1---0 v
NANO
logic s t a t e ~ -
I
enable
(a)
FIGURE 24. 7
\
--1
source of Nm
at virtual ground
for Vmhigh
(b)
NANO Gate Used as an Enabling Inverter; Output is held high regardless of V1:-i for VE1': low
24.3
put pull-down path to ground for a CMOS NAND
gate is therefore twice the physical length of that in
a CMOS inverter. To accommodate for this in design,
the channel widths of the NMOS devices are chosen
to be double those of the inverter. Hence, for a two
input CMOS NAND gate, the PMOS Wr/Lp ratio is
2.5/2 = 1.25 times that of the NMOS WN/LN ratio.
Thus,
2 Wr = 2.5 WN
Lr
LN
(two input CMOS NANO)
More inputs can be added to the CMOS NAND gate
of Figure 24.6a by including an additional PMOS device in the parallel PMOS pull-up and an additional
NMOS device in the NMOS series pull-down for
each additional input. The gate terminals of the
added NMOS and PMOS complementary transistors
are connected and used as other NAND gate inputs
as shown in Figure 24.8. Since the output high and
low voltages are not degraded by additional inputs
(as was the case for Vm in NMOS NAND gates), the
i Wp
Lp
= 2.5 WN
LN
(i input CMOS NANO)
The factor i results from the increased widening of
the NMOS transistor channel, which is necessary because of the increased length of the output pulldown path to ground through multiple NMOS transistor channels.
24.3
CMOS NOR GATE
CMOS NOR Gate Circuit
The previous section shows that the NAND function
can be realized with CMOS transistor pairs by plac-
parallel PMOS pull-up
stacked NMOS pull-down
\.._~ y~____J
\..__----y _ _,_)
CMOS pair A
CMOS pairB
379
number of inputs to a CMOS NAND gate is limited
by switching speed considerations.
As discussed in the previous sub-section, the
drain-to-source channel width of the N-channcl
MOSFETs in the NMOS pull-down stack must be
adjusted for the additional pull-down path length.
Each additional input requires further widening of
the NMOS channels. For an i input CMOS NAND
gate, the PMOS Wp/Lp ratio is related to the NMOS
WN/LN ratio by
Note that the W/L ratios for the MOSFETs of the
CMOS NAND gate in Figure 24.6a match this ratio.
Adding More Inputs
Ci'v!OS NOR Gate
CMOS pair i
FIGURE 24.8 Adding Inputs to a CMOS NAND: Add a PMOS transistor to the parallel pull-up and an NMOS
transistor to the stacked pull-down for each additional input
380
Chapter 24/CMOS Combinational Logic Cates
t· =
(2)2.5-r:
i
stacked PMOS pull-up
parallel NMOS pull-down
\__
.~
CMOS pairB
(a)
FIGURE 24.9
symbol
(b)
Two-input CMOS NOR Cate with W/L Ratios in Microns (µm): (a) Circuit schematic, (b) Circuit
ing the P-channel MOSFETs in a parallel pull-up
configuration and the N-channel MOSFETs in a
stacked series pull-down configuration. The logical
NOR function can also be obtained with CMOS pairs
but with the PMOS devices in a stacked series pullup configuration and the NMOS devices in a parallel
pull-down configuration as shown in Figure 24.9a.
(Disregard the W/L ratios for the present discussion.)
As with the NANO gate, each input is accommodated by a separate CMOS pair with the gate terminals of the NMOS and complementary PMOS device connected and serving as one input terminal.
The output is taken from the node between the parallel NMOS pull-down branch and the stacked
PMOS pull-up branch. The pull-up configuration
has the drain-to-source channels of the PMOS transistors in series between the output and V1m. The
pull-down section has the drain-to-source channels
of the NMOS devices in parallel between the output
and ground.
Output Low State
The output low state for the CMOS NOR gate of
Figure 24.9a is obtained for any input high.
Both Inputs High
With both inputs high, Yes.:---: for both NMOS devices
is sufficient to bring them into active operation. Output pull-down paths to ground are then available
through the drain-to-source channels of both Nchannel MOSFETs. With the VA input voltage high,
Vsc;y,\ is insufficient to turn on PA and no output
pull-up path to V1m is available. The CMOS NOR
gate of Figure 24.9a is therefore in the output low
state for both inputs high ..
Output High Voltage
= VoL
Examining the CMOS NOR gate of Figure 24.9a it is
easily seen that the sum of the NMOS drain currents
is equal to the drain current of P 8 (and P,\). With P 8
cutoff, the sum of the NMOS drain currents is
lo.Ni\
+ Io.Nil
=
lo,l'H(off) = 0
With zero drain currents the drain-to-source voltages of the active N-channel MOSFETs are VDs.N,\ =
VDs.:---: 13 = 0 (as was the case with the CMOS inverter
and NANO gate) and the output low voltage of the
CMOS NOR gate is
V 0 L(CMOS NOR)
=
0
24.3
VA High, VB Low
With a single input high, an output pull-down path
to ground is available through the drain-to-source
channel of the corresponding NMOS transistor (NA
in this case). With VA high (greater than VDD - IVul)
then Vsc,I'A is insufficient to turn on P;\· With P1\
cutoff no output pull-up path to VDI) is present.
Therefore, the CMOS NOR gate of Figure 24.9a is in
the output low state for V,\ high and VB low.
VA Low, VB High
Since a single input high places the corresponding
N-channel MOSFET in active operation, an output
pull-down path to ground is provided through the
drain-to-source channel of the corresponding
N-channel MOSFET. With VA low, Vsc,Ni\ is sufficient to bring P,\ into active operation. Therefore, a
highly conductive path between VDD and the source
of PB exists. However, with VB high, PB is cutoff and
no output pull-up path is available. With an output
pull-down path to ground and no output pull-up
path, the CMOS NOR gate is in the output low state.
It should be noted that with PA active and PB
cutoff, the drain current of PA is IoyA = Io.I'll = 0.
The source-to-drain voltage of PA is therefore VSD.PA
= 0. The source of P 8 is thus said to be at a virtual
VIJD·
Output High State
Both Inputs Low
When both inputs of the CMOS NOR gate of Figure
24.9a are low, both NA and NB are cutoff and no
output pull-down path is available. With VA low, PA
is active and the source of Fri is at a virtual VDD as
discussed above. With VB also low, PB is then brought
CMOS NOR Gate
381
into active operation and a pull-up path to VDI) is
available through the series drain-to-source chan ·
nels of PA and PB. Hence, with both inputs low, an
output pull-up path to V 0 0 is available and there is
no output pull-down path to ground. Thus, the
CMOS NOR gate of Figure 24.9a is in the output
high state.
Output High Voltage
It was previously mentioned that the PMOS drain
current of P 8 (and P J is equal to the sum of the
NMOS drain currents. With NA and NB both cutoff,
the drain currents of PB and PA are zero or
Io,PB
=
Io,!'/\
= Io.NA (off) + Io,NB(off) = 0
Since PA and Fil are in active operation and their
drain currents are zero, the source-to-drain voltages
are also zero. With VsD,PA = V50 y 8 = 0, the output
high voltage for the CMOS NOR gate is
VclH(CMOS NOR)
= V oo
NOR Function Realization
With the output high state occurring only for both
inputs low and the output low state occurring for any
input high, the circuit of Figure 24.9a realizes the
NOR function truth table (shown in Table 24.2). The
state of each MOSFET for this CMOS NOR gate for
all combinations of low and high inputs is also tabulated in Table 24.2.
Pull-Up and Pull-Down Paths
are Exclusive
As with the CMOS inverter and NAND gate, for
static operation of the CMOS NOR gate (all inputs
TABLE 24.2 States of Each N-Channel and P-Channel MOSFET and Presence of Output Pull-Up
and Pull-Down Paths in the Two Input CMOS NOR Gate of Figure 24.9a for All Combinations
of Low and High Inputs
VA
VB
low
low
high
high
low
high
low
high
NA
NB
PA
Ps
Pull-Up Path
Pull-Down Path(s)
off
off
on
on
off
on
off
on
on
on
off
off
on
off
on
off
P,, and Pti*
none
none
none
none
NR
*For V,\ and VB low a single output pull-up path to VnD through PA and Pu is present
**For V" and VB high two output pull-down paths to ground are present through NA and N 8
N"
N,v NR**
VouT
high
low
low
low
382
Chapter 24/CMOS Combinational Logic Gates
stacked PMOS pull-up
V,
)
-----0
VNOR
1
parallel NMOS pull-down
)
~
CMOS pair A
'---~~
I'--...,~______.)
CMOS pairB
CMOS pair i
FIGURE 24.10 Adding Inputs to a CMOS NOR Gate:
Add a PMOS transistor to the series stacked pull-up and
an NMOS transistor to the parallel pull-down for each
additional input
held constant at Vex or V0 H), an output pull-up path
to VDD or output pull-down path to ground is always
available. Also, a pull-up path and il pull-down pilth
are never present simultaneously.
existing P-channel MOSFETs in the stacked pull-up.
Since the output high and low voltages for a CMOS
NOR gate are not degraded by adding more inputs,
the number of inputs is limited by switching speed
considerations.
Ordering of Inputs
While any input to a CMOS NOR gate is logically
equivalent, the input to the top of the stack PMOS
transistor should be the input which switches least
often. Conversely, the input to the bottom of the
stack PMOS should be the input which switches
most often. This provides the fastest switching of
output states for the NOR gate.
Adding More Inputs
More inputs are added to CMOS NOR gates by sin,ply including additional CMOS pairs in the NOR
gate circuit as shown in Figure 24.10. Each additional
NMOS device has its drain-to-source channel placed
in parallel with the other NMOS transistors in the
parallel pull-down. Additional PMOS devices have
their drain-to-source channels placed in series with
Channel Width/Length Ratios
For the two-input CMOS NOR gate, the output pullup path to VDD is through the drain-to-source channels of two series P-channel MOSFETs. Since the
output pull-up path is physically longer for the
CMOS NOR gate compared to the CMOS inverter,
the channels of the PMOS devices must be widened
to accommodate for this. If the width of the PMOS
transistors is not increased to accommodate for the
increased pull-up path length, the voltage transfer
characteristic will not be symmetric. For a CMOS inverter the PMOS W 1,/L 1, ratio is 2.5 times that of
the NMOS WN/LN ratio (due to the relative mobility
µ,NI µ., 1, = 2.5 for silicon). Hence, for a two-input
CMOS NOR gate the PMOS and NMOS channel
widths should have a ratio
24.3
WI'= 2(2.5) WN
LI'
LN
= 5 WN
(2 input CMOS NOR)
LN
Note that the W/L ratios for the two input CMOS
NOR gate of Figure 24.9a match this ratio.
For a general i input CMOS NOR gate, the
PMOS and NMOS channel widths should have a
ratio
(i
input CMOS NOR)
Disadvantages of CMOS NOR Gates
over CMOS NANO Gates
Examining the W/L ratios for the transistors in the
CMOS NAND gate of Figure 24.6a, the total area of
the NMOS and PMOS channels is seen to be
2WNLN
+ 2W1Lr = 2(8µ,)(2µ,) + 2(10J.L)(2µ,)
= 72µ,m 2
For the CMOS NOR gate of Figure 24.9a, the total
area of the NMOS and PMOS channels is seen to be
2WNLN
+ 2WpLp = 2(4µ,)(2µ,) + 2(20J.L)(2µ,)
= 96µ,nz 2
FIGURE 24.11
CMOS NOR Gate
383
Discounting the area required for the wiring of these
devices, CMOS NOR gates require approximately
1/s more silicon surface area than CMOS NAND
gates in CMOS integrated circuits. Hence, it is best
to use CMOS NAND gates over CMOS NOR gates,
whenever possible.
Example 24.2
NOR Gate
SPICE Simulation of CMOS
Simulate the two-input CMOS NOR gate of Figure
24.9 using SPICE to obtain the voltage transfer characteristic and verify the realization of the logical
NOR function.
Solution Figure 24.11 shows a two-input CMOS
NOR gate with appropriate SPICE labelings. The input CIRcuit file for this circuit is as follows:
CMOS Two-Input NOR Gate
VDD 5 D DC 5V
-MODEL NMOSFET NMOS(VTO=1
+ KP=4OU GAMMA= □ .37 PHI= □ -6
+ CBD=3-1E-15 CBS=3-1E-15)
-MODEL PMOSFET PMOS(VTO=-1
+ KP=16U GAMMA= □ -4 PHI= □ -6
Two-input CMOS NOR Gate with Appropriate SPICE Labelings
384
+
Chapter 24/CMOS CombinationJI Logic GJtcs
CBD=3,1E-15 CBS=3,1E-15)
MPA 4 1 5 5 PMOSFET W=20U L=2U
MPB 2 3 4 5 PMOSFET W=20U L=2U
MNB 2 3 D O NMOSFET W=4U L=2U
MNA 2 1 D O NM◊SFET W=4U L=2U
VINA 1 0 PULSE(OV 5V DD D 1DNS
+ 2DNS)
VINB 3 0 DC DV PULSE(OV 5V OD
+ 0 2DNS 40NS)
-DC VINA O 5 0-1
-PLOT DC V(4)
-TRAN 1NS 40NS
-PRINT TRAN V(VINA) V(VINB)
+ V(4)
-END
Note that VINE has a default DC value of O V so
that the .DC sweep over VINA will produce both
output logic states.
The result of the .DC sweep is the voltage transfer characteristic shown in Figure 24.12a. Note the
voltage transfer characteristic is slightly displaced
from the center. The results of the .TRAN time
sweep are shown in Figure 24.126. The logical NOR
function is easily recognized, the output is high when
both inputs are low and low for any input high. Note
that the output fall time is approximately equal to
the output rise time.
24.4
CMOS AND AND OR GATE
AND and OR gates in CMOS digital circuits are obtained by simply feeding the output of CMOS
NAND and NOR gates into CMOS inverters, as
shown in Figures 24.13 and 24.14, respectively. Note
the intermediate NAND and NOR outputs can be
used to drive logic gates other than their respective
inverters and thus applications requiring complementary logic signals are easily facilitated.
24.5 CMOS COMPLEX LOGIC GATES
(AOis AND OAis)
The previous sections show that ANDing of signals
is naturally performed with CMOS circuitry by series
connection of N-channel MOSFETs and parallel
connection of complementary P-channel MOSFETs.
Also, ORing of signzds is performed in CMOS circuitry by parallel connection of NMOS transistors
and series connection of the complementary PMOS
transistors. Combining NMOS devices in series con1binations with the corresponding PMOS devices in
parallel and other NMOS transistors in parnllel with
their corresponding PMOS transistors in series
within the sc1rne CMOS circuit, allows realizc1tion of
more complex logic functions such as AND-OR-inverts or AOis.
Modification of CMOS NOR Gate Block
Diagram to Perform AND-OR-Inverting
Before introducing a CMOS AND-OR-invert gate,
reexamine the two-input CMOS NOR gate of Figure
24.9a. As discussed, the NOR function is realized by
parallel combinations of NMOS transistors c1nd series combinations of the complementc11y PMOS
transistors. Figure 24.15 shows a block dic1grarn representing the parallel and series combinations of
N- and P-channel devices. This block dic1grc1rn represents the logic function
Vow·
= V,.1 NOR Vn
If the blocks dedicated to accommodate VA are
modified to perform VA AND Vc c1nd the blocks
dedicated to V 8 are modified to perforrn V 8 AND
V 0, as in Figure 24.16, the logical function
VuuT = (V11 AND Ve·) NOR (Vii AND Vt,)
is performed. The circuitry needed to rec1lize VA
AND Vc is a series cornbirwtion of NMOS devices
for the block labeled NA AND Ne and c1 parallel
combination of complementary PMOS devices for
the block lc1beled PA AND Pc. Likewise, the blocks
!ctbeled N 8 AND N 0 and Pc AND P 0 are represented by series combinations of N-channel
MOSFETs and parallel combinations of complementc1ry P-channel MOSFETs, respectively. Figure 24.17a
shows the circuitry for such a gc1te. This is a CMOS
AND-OR-invert gc1te.
Input ANDing Sections
Examining the complex CMOS logic circuit of Figure
24.17a, two series NMOS brnnches appec1r between
the output and ground. Either of these can serve as
m1 output pull-down path to ground when the corresponding two inputs are high. That is, an output
pull--down path exists through N,, and Ne, if V,, and
?.4.5
385
CMOS Complex Logic Gates (AO!s and OAls)
Vrn,(V)
'
5
4-r
3-r
2-1
VOUT (V)
A
I
I
0
0
I
5-
5
10
I
I
I
I
v
t(ns)
~
t(ns)
15 20 35 30 35 40
VINB(V)
4
5
:j
4
3
Vffill,,;;(}V
2
1
0
o+--+0
1
vrn,(V)
2
3
(a)
4
5
0
I
I
.
I
I
I
I
5
10
15 20 35 30 35 40
5
10
15 20 35 30 35 40
I
I
VaUT(V)
54
32
0
t(ns)
0
(b)
FIGURE 24.12 SPICE Simulation Results of Example 24.2: (a) Voltage transfer characteristic, (b) Transient response
verifying realization of logical NOR function
386
Chapter 24/CMOS Combinational Logic Gates
q
LP
r~o
- - ~ VAND
[~No
A ( ,__~---,
LIt:
A
l
. __r--v
B=Q
N,
------------------0
F=AB
F=AB
VNAND
...L
(a)
(b)
FIGURE 24.13 CMOS AND/NAND Gate: (a) NAND fed inverter, (b) Circuit symbol indicating both AND and NAND
functions are available
Ve are both high. Alternately, an output pull-down
path exists through N 8 and N 0 , if VB and V 0 are both
high. Note that for the series combination of the
N-channel MOSFETs NA and N 0 there is the corresponding parallel combination of complementary
P-channel MOSFETs PA and Pc. Likewise, for the
series combinations of NMOS transistors N 8 and ND,
(a)
there is a corresponding parallel combination of
complementary PMOS transistors PB and P 0 .
Output is NORing of the ANDings
As discussed earlier in this section, parallel combinations of the NMOS pull-down paths and series
combinations of the complementary parallel PMOS
(b)
FIGURE 24.14 CMOS OR/NOR Gate: (a) NOR fed inverter, (b) Circuit symbol indicating both OR and NOR
functions are available
24.5
CMOS Complex Logic Gates (AOJs and OA!s)
387
Verification of AND-OR-Invert
Logic Function
Table 24.3 is a detailed truth table for the four-input
AOI circuit of Figure 24.17a. We shall now verify all
combinations of low and high inputs as listed in Table 24.3 along with the states of all N- and P-channel
MOSFETs. The ANDing of the individual pairs of inputs along with the expected output logic states are
also included in Table 24.3.
PMOS
pull-up
v.
(}----+---------<
Output Low State
NMOS
pull-down
VA AND Ve High
As discussed previously in this section, an output
pull-down path to ground exists through the channels of NA and Ne if VA and Vc are both high. With
VA and Vc high, PA and Pc are both cutoff and no
output pull-up path to V00 is available. Thus, the
circuit of Figure 24.17a is in the output low state for
VA AND Vc high. This verifies the output low state
specified in lines 13 through 16 of Table 24.3.
FIGURE 24.15 Block Diagram Representing Transistor
Configuration of Two-input CMOS NOR Gate
pairs provides an ORing of the ANDing of inputs.
As with all CMOS gates, the output is then naturally
complemented and the ORing is in essence a NORing and the logic gate of Figure 24.17a does indeed
realize the logic function
V8 AND V0 High
Similarly, NB and ND are active when V 8 and VD are
high and an active pull-down path to ground is available. With VB and VD high, PB and P 0 are cutoff and
no output pull-up path to VDo is present. Therefore,
the circuit of Figure 24.17a is also in the output low
state for VB AND VD high. Thus, the output low
VoUT = (VI\ AND Ve) NOR (VB AND Vn)
= NOT[(V/\ AND Ve) OR (VB AND V0 )]
=AC+ BO
VA (
)----,---f
__
Ve,)---~_,__,..._
__.
PMOS pull-up
v.o-,f---+------~--<
VD(}--+---+--------+-•
P. AND Po
'----,---'
F = (VA AND VJ NOR (V8 AND V 0 ) =AC+ BD
NMOS pull-down
FIGURE 24.16
Block Diagram Representing NOR.ing of Sub-logic Sections for an AND-OR-invert Logic Gate
388
Chapter 24/CMOS Combinational Logic Gates
lq~~P.
PMOS pull-up
I
I
_j, - -C- - - - - - - - - - - - v
VA
Bµm NA
VB
2µiii
o~-_,,
NMOS pull-down
[sµm
N
2µiii B
-I
-=~
CMOS pair A
~
~
CMOS pairC
CMOS pairB
~
CMOSpairD
(a)
- -F=AC+BD
(b)
FIGURE 24.17
Four-input CMOS AND-OR-invert: (a) Circuit schematic, (b) Logic schematic
states tabulated in lines 4, 8, and 12 and again line
16 of Table 24.3 are verified.
Output Low Voltage == V 0L
With PB and PD cutoff, the sum of the PMOS drain
currents ID,l'll(off) + ID,rD(off) is zero. Since the sum
of the NMOS drain currents of Ne and N 0 is equal
to the sum of the PMOS drain currents, these are
also zero. Hence,
ID,Nc(ON)
+ Io,NLJ(ON) = lo,PB(OFF) + Io,ro(OFF)
=O
Since zero drain current active MOSFETs have a
drain-to-source voltage of zero (as discussed in section 17.2), the NMOS transistors providing the out-
put pull-down path to ground both have VDs = 0.
Thus, the output low voltage for the complex AOI
logic gate of Figure 24.17a is the same as that for the
CMOS inverter, NAND, and NOR gates with
VOL= 0
This was the output low voltage found for the simpler CMOS NAND and NOR gates of the previous
sections. VoL is also zero for even more complex
CMOS logic gates.
Output High State
VA AND V8 Low
With VA and VB low, PA and Pri are active and an
output pull-up path to VDo is available through their
14.5
CMOS Complex Logic Gates (AO!s and 0/\ls)
389
TABLE 24.3 States of Each N-Channel and P-Channel MOSFET and Presence of Output Pull-Up
and Pull-Down Paths in the Four Input CMOS AND-OR-Invert Gate of Figure 24.17a
for All Combinations of Low and High Inputs
VA
AND
1
:z
3
4
5
6
7
8
l)
10
11
11
13
14
15
16
NA
No
PA
Pc
Ps
Vs
AND
Vo
Pull-Up
Path
PullDown
Path
Yrn;1
VA
Ve
Vs
Vo
Ne
Nu
Po
Ye
low
low
low
low
low
low
low
low
low
low
high
high
low
high
low
high
off
off
off
off
off
off
off
off
off
off
on
on
off
on
off
on
on
on
on
on
on
on
on
on
on
on
off
off
on
off
on
off
low
low
low
low
low
low
low
high
yes
yes
yes
no
no
no
no
yes
low
low
low
low
high
high
high
high
low
low
high
high
low
high
low
high
off
off
off
off
on
on
on
on
off
off
on
on
off
on
off
on
on
on
on
on
off
off
off
off
on
on
off
off
on
off
on
off
low
low
low
low
low
low
low
high
yes
yes
yes
no
no
no
no
yes
high
high
high
high
low
low
low
low
low
low
high
high
low
high
low
high
on
on
on
on
off
off
off
off
off
off
on
on
off
on
off
on
off
off
off
off
on
on
on
on
on
on
off
off
on
off
on
off
low
low
low
low
low
low
low
high
yes
yes
yes
no
no
no
no
yes
high
high
high
low
high
high
high
high
high
high
high
high
low
low
high
high
low
high
low
high
on
on
on
on
on
on
on
on
off
off
on
on
off
on
off
on
off
off
off
off
off
off
off
off
on
on
off
off
on
off
on
off
high
high
high
high
low
low
low
high
no
no
no
no
yes
yes
yes
yes
low
low
low
low
drain-to-source channels. Also, NA and Nil are cutoff
and no output pull-down path to ground is present.
Thus, the complex CMOS logic gate of Figure 24.17a
is in the output high state and lines 1, 2, 5, and 6 of
Table 24.3 are verified.
VA AND VvLow
P,\ and PD are active for VA and VD low and an output
pull-up path to VnD is available through their drainto-source channels. NA and Nn are simultaneously
cutoff and no output pull-down path to ground exists. Thus, the CMOS logic gate of Figure 24.17a is
in the output high state and lines 1, 3, 5, and 7 of
Table 24.3 are verified.
Ve AND V8 Low and Ve: AND Vv Low
An analogous situation results from either Vc and V11
low verifying lines 1, 2, 9, and 10 of Table 24.3. Lines
1, 3, 9, and 11 of Table 24.3 are verified in the same
manner for Ve and Vu low.
Output High Voltage
=V
0u
With Ne and Nil cutoff, the sum of the NMOS drain
currents is zero. With the output pull-up path to V1)l)
VAlll
high
high
high
low
high
high
high
low
provided through the two complementary PMOS
devices and equal drain currents of the cutoff NMOS
devices given by
Io,Nc(ON)
+
ID,No(ON)
= ID,PB(OFF) + Io,PD(OFF)
=0
The drain-to-source voltages of the (active) pull-up
PMOS transistors are Vus.r; = 0. Thus, as with the
CMOS inverter, NAND, and NOR gates, the output
high voltage is
Pull-Up and Pull-Down Paths
are Exclusive
As demonstrated with the CMOS inverter of the previous chapter and the CMOS NAND and NOR gates
of the previous sections, static operation (all inputs
held constant at Vm and/or V0 H) of the CMOS
AND-OR-invert gate of Figure 24.17a always provides either an output pull-up path to VDD or an output pull-down path to ground. As with the
previously discussed CMOS logic gates, output pull-
390
Chapter 24/CMOS Combinational Logic Gates
up and pull -down paths are never simultaneously
available.
be twice that of the inverter in Example 23.2. Keeping
the same channel length yields
w;\' I
Channel Width/Length Ratios
The channel width/length ratios of the NMOS and
PMOS transistors in a complex CMOS logic gate
must be scaled. This accommodates for the relative
mobilities of electrons and holes in silicon
!-LN
=
2.5µ,p
(in silicon)
and the relative lengths of the output pull - up paths
to V00 and pull-down paths to ground. The widths
of the N-channel MOSFETs are simply those found
for the inverter with the same desired VTC multiplied
by the maximum number of NMOS transistors required for an output pull -down path to ground. That
is, for the complex CMOS AOI gate of Figure 24.17a,
the longest output pull-down path to ground is
through the drain-to-source channels of two NMOS
transistors. The WN/LN ratio should therefore be
twice that found in a CMOS inverter with the same
desired VTC.
The widths of the PMOS channels are scaled in
a similar fashion. Wp/Lr should be equal to that
found in an inverter with the same desired VTC multiplied by the maximum number of PMOS transistors
required for an output pull-up path to V00 . Exam ining the CMOS gate of Figure 24.17a, the longest
pull-up path from the output to V00 is through the
drain-to-source channel of two PMOS devices. The
Wp/Lp ratio should therefore be twice that found in
a CMOS inverter with the same desired VTC.
The following example demonstrates sizing of
MOSFETs for the complex CMOS AOI circuit of Figure 24.17a.
LN
=2
1101
wNI
LN ;,,,,,.,.,,.,
= 2 (4µ,) =
(2µ,)
8µ,111
2µ,m
Also mentioned, the longest pull-up path to V00 is
through two PMOS drain-to-source channels. The
Wp/L 1, ratio should also be twice that of the inverter
in Example 23.2. Keeping the same PMOS channel
length yields
wl'I
Li,
=
, \0/
2
Wpl
Lr
=
i11 v crtcr
2
(10µ,) = 20µ,m
(2µ,)
2µ,lll
Non-Inverting AND-OR Gates
Non-inverting AND-OR gates are obtained in
CMOS in the same fashion as NMOS AND and OR
gates. Namely, by connecting an inve rter at the out ~
put. Figure 24.18a shows the CMOS AND -OR-invert gate of Figure 24.17a with a CMOS inverter connected to th e output. This new circuit performs the
logic function
Vmn
= CV11 AND Ve) OR (VB AND V0)
=AC+ BO
Thus, the inverted AOI output node can be used to
drive gates other than the cascaded inverter to provide compleITtentary logic signals.
Recipe for Other Complex CMOS
Logic Gates
Additional multi - input complex logic gates can be
constructed using CMOS obeying the following general design connections:
1.
ANDing of signals is performed by series stacked
combinations of NMOS transistors with coITtplementing PMOS transistors in parallel.
Example 24.3 Size of MOSFETs in a
Complex CMOS Logic Circuit
2.
Design the channel widths and lengths of the com plex CMOS logic circuit of Figure 24.17a so that it
has the same VTC of the CMOS inverter of Example
23.2 (shown in Figure 23.3).
ORing of signals is accomplished by parallel connection of NMOS devices with the comple menting PMOS devices stacked in series.
3.
The gate termina l of each NMOS transistor is
tied to the gate terminal of the complementing
PMOS transistor and used as a signal input.
4.
ORing of ANDed signals is realized by parallel
connection of the series NMOS devices and series connection of the complementing parallel
PMOS devices.
Solution As mentioned in this section, the longest
output pull-down path to ground found in the
CMOS logic gate of Figure 24.17a is through two
NMOS channels. The WN/LN ratio should therefore
24.5
CMOS Complex Logic Gates (AOls and OAis)
8µmN
2µm D
vBo----l-i
8µmN
2µm
B
----1
391
4µmN
2µiii
0
l
\_
- ~
secondary inversion
-:-
(a)
A-
F=AC+BD
C
- F=AC+BD
B
D
(b)
FIGURE 24.18
Four-input CMOS AND-OR gate: (a) Circuit with cascaded inverter, (b) Logic schematic
5.
ANDing of ORed signals is realized by series
connection of the parallel NMOS devices and
parallel connection of the complementing series
PMOS devices.
6.
If a non-inverting AND-OR signal is desired,
connect the output of the AND-OR-inverting
circuitry to an inverter (the NOTed AND-OR
node can be used to drive other logic gates).
7.
A practical limitation for most CMOS digital integrated circuits is that no output pull-down
path to ground or output pull-up path to VDD
should exceed traversing four MOSFETs.
8.
The channel widths and lengths should be scaled
as described earlier in this section.
When designing complex CMOS logic circuits, it
is recommended that a corresponding truth table be
verified for all combinations of low and high inputs.
An output pull-up path to VDD or output pull-down
path to ground must be available for every combination of inputs and pull-up and pull-down paths
should never be present simultaneously. Sketching
block diagrams of the sub-logic sections provides a
useful preliminary step in designing of complex
CMOS logic circuits.
One final note should be made about the output
voltage range. As with the CMOS inverter, NAND
gate, and NOR gate, the output voltage operates railto-rail. That is, the output voltage varies from Vm =
ground = 0 to V0 11 = VDD·
Example 24.4 Complex CMOS
OR-AND-Invert Logic Gate
Design a five-input complex CMOS logic gate that
provides the logic functions
392
Chapter 24/CMOS Combinational Logic Gates
F
=
(A
+
B)(C
+
D)E
F
=
(A
+
B)(C
+
D)E
NMOS transistors. The blocks labeled PA OR Pi, and
Pc OR P0 should be replaced by series combinations
of PMOS transistors.
and
Solution (Input E) The input for signal VE is connected to a single N-channel MOSFET in place of
the block labeled NE and single P-channel MOSFET
in place of the block labeled PE.
(Channel W/L ratios are calculated in the following
example.)
Solution (Block Diagram) To design the five-input inverting logic section, note that the desired logic
function is a NANDing of two ORings and an individual si1mal
or
u
v();\/
Solution (Inverting) To provide the OR-ANDing
of the non-inverting logic desired, a CMOS inverter
should be connected to the output of the 1nulti--input
complex CMOS logic gate.
Figure 24.196 shows the CMOS circuit that provides the desired logic functions with each block of
Figure 24.19a replaced with the constituent MOSFET
representations and cascaded CMOS inverter to provide complementing of the initial logic function. As
mentioned, the input node to the cascaded inverter
may be used to drive other gates.
The truth table for this logic gate should be verified for all 25 = 32 combinations of low and high
inputs to verify proper logic realization. This is left
as a homework exercise in Problem 24.40.
= (V;1 + V,;)(Ve + Vo)VE
= (V1 , OR V8 ) NAND (Ve OR V0 ) NAND Vr
The overall NANDing of the sub-logic sections VA
OR V8 , Ve OR VD, and VE can be represented by the
block diagram shown in Figure 24.19a. NANDing of
signals requires series combinations of NMOS sections and parallel combinations of PMOS sections.
Solution (ORing Sub-logic) To perform the ORing logic VA OR V8 and Vc OR VD, the blocks in
Figure 24.19a labeled NA OR NB and Ne OR ND
should be replaced with parallel combinations of
PMOS pull-up
F =(A+ B)(C + D)E
Ya<)-----+--+------------t--+--------1
Yo<>-----+--+-----~--,
NcORN0
......._,--___,
Yc<l---+--+----------<
NMOS pull-down
VB()-~-+-•
VA
NAORN8
l---"--1
-.:-
(a)
FIGURE 24.19 Five-input Complex CMOS OR-AND-invert/OR-AND Gate of Examples 24.4 and 24.5: (a) Block
diagram representing NANDing of sub-logic sections
24.5
CMOS Complex Logic Gates (AOJs and OAls)
393
------------- 8
T
ilOµmp
2µm E
20µmp
2µm D
~--+---------+--~---j
VE
r· . .
,-···-12µmN
7
"'1µni
C
7
12µmN
"'1µni
D
~.....J
---+------·---~----~
secondary inversion
~•~N,
'------y---··./
~
CMOS pair A
CMOS pair B
'--------y
...J '----y----./
CMOS pair C CMOS pairD
CMOS pairE
(b)
F =(A+ B)(C + D)E
-
F=(A+B)(C+D)E
(c)
FIGURE 24.19 (continued)
(b) Circuit schematic, (c) Logic schematic
Example 24.5 Complex CMOS Logic Gate
Channel Width/Length Ratios
Calculate the channel width/length W/L ratios for all
MOSFETs in the logic gate of the previous example
(Figure 24.196). Both the multi-input and cascaded
inverting stages should have the VTC and transient
response of the CMOS inverter in Example 23.2.
Solution (Second Inverter Stage) Since the two
stages of the CMOS circuit of Figure 24.196 should
have the same response as the inverter of Example
23.2, the inverter stage PMOS and NMOS have
channel W /L ratios given by
Wp 1
10µ,m
Lp1
2 µ,111
WN1
4 µ,m
2 µ,111
and
LNI
Solution (NMOS WN/LN Ratios of Multi-input
Stage) For the initial multi-input stage, all output
394
Chapter 24/CMOS Combinational Logic Gates
r·~30µmp
~-:!µm C
--··
j30µmp
L,-:!µm
D
Your=?
VC
',-.~----,
,-12µmN
7
~
C
8µmN
7µm F
~----~
~-- I ~4µmN
l~Zµiii D
I
sµmN
2µiii
E
(a)
Six-input Complex CMOS AND-OR-invert Gate of Examples 24.6 and 24.7: (a) Circuit schematic
FIGURE 24.20
pull-down paths to ground are through three NMOS
transistors. The W N/LN ratios should therefore be
three times that of N 1 or
WN
(A, B, C, D, E)
LN
=3
The third output pull-up path to VoD is through the
single transistor PE. The Wp/Lp ratio need only be
that of P1 and thus
WNJ
WPr:
W/'1
10
LNJ
Ll'E
Lp/
2
X -
µ,111
µ,111
4 µ,111
12 µ,111
=3X--=-2 µ,m
2 µ,m
Solution (PMOS, Wp/Lp Ratios of Multi-Input
Stage) Three output pull-up paths to VDIJ are
available. Two of the paths are through two PMOS
transistors, P J\ and P 8 or Pc and P 0 . Thus, the PMOS
transistors P Al PB, Pc, and P 0 should have Wp/Lp
ratios twice that of P 1 or
Example 24.6 Complex CMOS
AND-OR-Invert Logic Gate
Wp (A B C D) = 2 x Wpi
Lp
L~
I
I
I
10 µ,nz
2 µ,m
The following two examples demonstrate the
design of a complex CMOS AND-OR-invert logic
gate. The channel width/length ratios are calculated
in the secondary example.
20 µ,m
2 µ,m
=2X--=--
What complex logic function is performed by the sixinput CMOS logic gate of Figure 24.20a?
24.5
CMOS Complex Logic Gates (AO!s and OAls)
395
A
B
c~..___.,,,
VB (l-----+---+----+---------+--------r-----1
Vpo---·- + - - - - + - - - - - - - + - - - - - + - - I
D-----1
'---...----'
F=ABC+D+EF
F
NBANDN,
(b)
FIGURE 24.20 (continued)
(c)
(b) Block diagram, (c) Logic schematic
Solution (Block Diagram, NMOS Pull-Down
Sections) Examining the complex CMOS logic
gate of Figure 24.20a it is seen that three output pulldown paths to ground exist as follows: (1) through
NA, N 13, and Ne; (2) through N 0 ; and (3) through NE
and NF. Figure 24.20b shows a block diagram of this
complex CMOS logic gate with a separate block dedicated to each NMOS pull-down path. As noted in
this and previous sections, series connection of
NMOS devices performs an ANDing of signals.
Thus, the blocks representing the first and third pulldown path are labeled NA AND NB AND Ne and NE
AND NF. The block representing the pull-down of
the single transistor is labeled N 0 .
Solution (Block Diagram, PMOS Pull-Up Sections) Further examining Figure 24.20a, note the
PMOS output pull-up path to VDD is in three stages:
(1) PA, P 8 , and Pc; (2) PD; and (3) PE and Pp. The
P-channel MOSFETs of each pull-up stage correspond to the N-channel MOSFETs of each pulldown path. The block diagram of Figure 24.206 also
includes blocks representing each PMOS pull-up
stage. Since parallel combinations of P-channel
MOSFETs represent ANDing of signals, the block of
Figure 24.206 representing the PMOS pull-up stage
closest to VDD is labeled PA AND P 8 AND Pc. Similarly, the block representing the pull-up stage closest to the output is labeled PE AND PF- The block
representing the single transistor pull-up stage is labeled P 0 .
Solution (NORing of ANDing) Examining the
block diagram of Figure 24.206, the pull-down paths
are in parallel and a corresponding PMOS pull-up
stage is present in a series pull-up. Corresponding
blocks in the pull-down and pull-up paths perform
the same logic function. Hence, the logic gate of Figure 24.20a performs a NORing of the individual sublogic sections. Since each section is either an ANDing
or a single signal, this gate performs the logic function
F = (A AND B AND C) NOR D NOR (E AND F)
= NOT[(A AND BAND C)
ORD OR (E AND F)]
=ABC+ D + EF
Figure 24.20c shows the symbolic representation of
this logic function. Constructing a truth table for all
396
Chapter 24/CMOS Combinational Logic Gates
combinations (2 1' = 64) of low and high input states
and corresponding outputs would provide complete
confirmation of the logic gate output function.
Complex CMOS Logic Gate
Channel Width/Length Ratios
Calculate the channel width/length W/L ratios for all
Example 24.7
MOSFETs in the logic gate of the previous example
(Figure 24.20a). Both the multi-input and cascaded
inverting stages should have the VIC and transient
response of the CMOS inverter in Example 23.2.
Solution (NMOS WNILN Ratios) The channel
width/length ratio for the NMOS transistor of the
CMOS inverter in Example 23.2 was found to be
W~i1LN 1 = 4µ.m/2µ.m. The complex CMOS logic gate
of Figure 24.20a has three NMOS pull-down paths.
The first pull-down path is through the three NMOS
transistors NA, NB, and Ne, The N-channel
MOSFETs N,v N 13, and Ne should therefore have
WN/LN ratios three times that of the NMOS device
in Example 23.2:
wN
LN
I
LN/
I
4 µ.111
2 µ.111
12 µ.m
2 µ.m
=3X--=--
Since ND is a single transistor pull-down path, the
WN/LN ratio is the same as that in the inverter of
Example 23.2 given by
WNo
WN1
4 µ.m
LNo
LN1
2 µ.111
The third pull-down path consists of the two NMOS
transistors NE and NF. The Wr-.;/LN ratio for NE and
NF should therefore be twice that of the Example 23.2
inverter and thus
WN (E F)
LN
I
=
WI'
(A, B, C, D, E, F)
Lr
=
3
x -WI'!
L~
10 µ.111
2 µ.111
30 µ.Ill
2 µ.m
=3X--=--
CMOS logic gates can be even more complex
than those shown previously. The following example
describes a more complex gate.
Super Complex
CMOS Logic Gate
Example 24.8
Determine the logic function performed by the eightinput complex CMOS logic gate shown in Figure
24.21a.
wNT
(A B C) = 3 X
Solution (PMOS Wp/L,, Ratios) The channel
width/length ratio for the PMOS transistor of the
CMOS inverter in Example 23.2 was found to be
W,,i/L"' = 10µ.m/2µ.m. Examining Figure 24.20a, all
output pull-up paths to VLm are through a series
combination of three P-channel MOSFETs. Thus, all
PMOS devices in the complex CMOS logic gate of
Figme 24.20a should have channel Wp/L" ratios
three times that of the inverter in Example 23.2 and
thus
2 X WN/
LN/
4 µ.m
8 µ.m
2 µ.m
2 µ.m
=2X--=--
Solution (Block Diagram) Examining the logic
gate of Figure 24.21a, note that two NMOS output
pull-down paths to ground are present: (1) through
the N,\, NB, Ne, and ND configurations, and (2)
through the NE, N,, Ne, and NH configurations.
Also, the PMOS output pull-up path to VoD is in two
major sections: (1) through the P i\t PB, Pc, and PD
configurations, and (2) through the PE, P,, Pc, and
P, 1 configurations. The block diagran, of Figure
24.216 illustrates this configuration. Parallel configurations of pull-down paths and series configura
tions of pull-up sections imply an overall NORing of
the sub-logic sections.
Solution (Left Pull-Down Path) The NMOS
pull-down path in Figure 24.21a consisting of NA,
NB, Ne, and ND will be considered first. The transistors NA and N 13 are in series, realizing the NMOS
pull-down logic A AND B. TI,e series N,\-N 11
24.5
CMOS Complex Logic Gates (AO!s and OAls)
therefore perform the logic A AND B. The parallel
PA-PB section is in series with Pc achieving the logic
[(A AND B) OR C]. Finally, the Pi\-P8 -Pc configuration is in parallel with the P-channel MOSFET PD.
Thus, the top PMOS pull-up section does indeed realize the same logic [(A AND B) OR C] AND D
performed by the corresponding NMOS pull-down
path.
MOSFETs are in parallel with Ne, thus achieving the
logic (A AND B) OR C. Finally, the NA-NB-Ne configuration is in series with the NMOS device N 0 denoting an ANDing. The N1v N 8 , Ne, and N 0 NMOS
section thus realizes the NMOS pull-down logic [(A
AND B) OR C] AND D.
Solution (Upper Pull-Up Section) The P-channel MOSFETs in Figure 24.21a for the PMOS pullup section closest to V00 are connected to the Nchannel MOSFETs of the NMOS pull-down path on
the left side of the gate schematic. This PMOS pullup section should therefore realize the same logic
calculated in the previous solution sub-section.
The PMOS devices PA and P 8 are in parallel and
Solution (Right Pull-Down Path) The NMOS
pull-down path of Figure 24.21a including NE, NF,
Ne, and NH is made up of two parallel N-channel
MOSFET sections in series. This NMOS configuration realizes the logic (E OR F) AND (G
ORH).
Your=?
-::-
(a)
FIGURE 24.21
397
Eight-input Super-Complex CMOS Logic Gate of Example 24.8: (a) Circuit schematic
398
Chapter 24/CMOS Combinational Logic Gates
f
~
V
I
~
0----
-+- -·
PA' Pa,
Pc, Po
l
!
~
P., P.,
Po, PH
u
0--0---
----
'
D - - - - - - - - - 1...___.,
E------>
OUT
--D OUT
I
!__~
~
!
-
NA,Na,
Nc,No
-----~
OUT = (AB + C)D + (E + F)(G + H)
N8 ,N,,,
Na,NH
I
I
-:-
(b)
FIGURE 24.21 (continued)
(c)
(b) First level block diagram: NORing, (c) Logic schematic
Solution (Lower Pull-Up Section) The PMOS
pull-up section consisting of PE, PF, Pc, and PH is a
parallel combination of series P-channel MOSFETs.
This realizes the same logic (E ORF) AND (G OR
H) performed by the corresponding NMOS pulldown path.
Solution (NORing of Sub-Logic Sections) The
previous solution sub-sections showed that the two
PMOS pull-up sections realize the same logic as the
complementing NMOS pull-down paths. Since the
NMOS pull-down paths and PMOS pull-up sections
are in an overall NORing configuration, the logic
function provided by the complex CMOS logic gate
of Figure 24.21 is
F
= {[(A AND B] OR C)] AND Dl
NOR [(E ORF) AND (G OR H)]
= NOT({[(A AND B] OR C)]
AND D)
OR [(E ORF) AND (G OR H)])
= (AB + C)D + (E + F)(G + H)
This logic function is shown symbolically in Figure
24.21c. Constructing a truth table for all (2 8 = 256)
combinations of low and high inputs and their corresponding outputs would prove a formidable task
but would also provide complete verification of this
logic expression.
f
Tips, Tricks, and Gimmicks
De Morgan's Theorems
De Morgan's theorems will be needed in the
following section. They can be stated simply as
follows:
De Morgan's NOR Theorem:
w+
y =
WY
De Morgan's NAND Theorem:
WY=W+Y
24.6
v.
CMOS XOR/XNOR Gates
399
n--~-+-------------.----[
VXOR
8µmN
Tµiii
A2
stage 2
stage 1
(a)
A
B
XOR
'----y---1
stage 1
stage 2
(b)
FIGURE 24.22
symbol
24.6
:JD-xoR
(c)
XOR Gate: (a) CMOS two-stage combinational logic realization, (b) Logic embodiment, (c) Circuit
CMOS XOR/XNOR GATES
Two Stage Circuit
Exclusive OR (XOR) and exclusive NOR (XNOR)
gates can not be constructed in any clever way similar to the NMOS XOR gate discussed in section 22.5.
The design of a CMOS XOR gate through combinational logic realization results in the two stage
CMOS gate shown in Figure 24.22a. The two stages
of this circuit are a two-input CMOS NOR gate
(A + B) and a three-input CMOS AOI performing
the logic function AB + C. The logic output A + B
of the first stage is fed into the C input of the AOI
giving an output logic function
F =AB+ A+ B
The logic circuit is shown symbolically in Figure
24.226. To show that this is in fact the XOR function,
we apply De Morgan's NOR theorem to the A+ B
term to obtain
F = AB + A B = A XOR B
400
Chapter 24/CMOS Combiniltional Logi c Cc1tcs
r-- · -15
I VDD"~~ DC 5V
I;
n-
6
5
o
-:-
g~:MPA
'41~ ~
:]
-:r-<
VINB
1
>----+----- - - - - +11----;
3
I 5 20UM uDA
2UiVi '"" -
J1 DC
OUM
2UM
lg
MPA2
31 I1- : -"2UM
"OUM
9
MP82
- - -7
~
VNOR
r - ~- - - - + - - - - - - - - - , - - - - - - -2-1 I
-:-
1
,-~------ --
1___3J
I o 4UM
3
82UM
MNA
1~
----
r
2
I
s 20UM
MPAB
2UM
vXOR
o 4UM
:=a2UM
I
MNB
L2J
1
I o BUMMNA2
l-- 2UM
IQ
-:-
FIGURE 24.23
CMOS Two-stage Combinational Logic XOR Gate with Appropriilte SPICE Labelings
111is is indeed the XOR function, since both inputs
low or both inputs high result in logic low output
state.
Disadvantages of Two Stage
Combinational Logic XOR Gate
The disadvantage of using the two stage combina tional logic XOR gate of Figure 24 .22a is that the
propagation delay for two gate stages is twice that of
one gate stage .
Alternate XOR Embodiments
The next chapter on CMOS special purpose gates
presents several alternate methods for constructing
XOR gates using the logic elements to be presented
in that chapter.
Example 24 .9 CMOS Two Stage
Combinational Logic XOR SPICE Simulation
Perform a SPICE simulation similar to that of Example 24.2 on the CMOS two stage combinational
logic XOR gate of Figure 24.22a.
Solution Figure 24.23 shows a CMOS two -stage
combinational logic XOR gate with appropriate
SPICE labelings. The input CIRcuit file for this circuit
is as follows:
CMOS Two-Stage Combinational
Logic XOR Gate
VINA 1 D PULSE(OV 5V DD D 1DNS
+ 20 NS)
VINB 3 D DC DV PULSE(OV 5V DD
+ D 2DNS 40NS)
VDD 5 D DC 5V
Chapter 24
-MODEL NMOSFET NMOS(VT0=1
KP=40U GAMMA=0-37 PHI=D-6
CBD=3-1E-15 CBS=3-1E-15)
-MODEL PMOSFET PMOS(VT0=-1
+ KP=16U GAMMA= □ -4 PHI=0-6
+ CBD=3-1E-15 CBS=3-1E-15)
I
3+
2
* Stage 1: NORing of inputs
1
o-:
I
10 15 20 25
--►
:
,
1
I
5
0
t(ns)
30 35 40
VINB(V)
5------41
4
1 i
o-+
5
0
-+--
-+ -- -------- - ► t(ns)
10 15 20 25
30 35 40
VNoiV)
•
54
3
2
10-+,-'---+---------~+----r-~--. t(ns)
5 10 15 20 25 30 35 40
0
VXOR(V)
II;,.
5-4-
32-
1:
I
5
10
:
MPA
MPB
MNA
MNB
4
2
2
2
1
3
1
3
5 5
4 5
DD
DO
PMOSFET
PMOSFET
NMOSFET
NMOSFET
W=20U L=2U
W=20U L=2U
W=4U L=2U
W=4U L=2U
* Stage 2: AOiing of inputs
~t
0
401
+
+
4-j
0
Problems
,
15 20 25
:
30
1
-----+ t(ns)
35 40
FIGURE 24.24 Results of Example 24.9 CMOS XOR
SPICE Simulation
MPA2 9 1 5 5 PMOSFET W=20U L=2U
MPB2 9 3 5 5 PMOSFET W=2DU L=2U
MPAB 8 2 9 5 PMOSFET W=20U L=2U
MNA2 7 1 DD NMOSFET W=8U L=2U
MNB2 8 3 7 D NMOSFET W=8U L=2U
MNAB 8 2 □ 0 NMOSFET W=4U L=2U
-TRAN 1NS 40NS
-PRINT TRAN V<VINA) V(VINB)
+ V(4)
-END
Note that all PMOS devices in both stages have
Wp/Lp ratios that are twice those of the inverter of
section 23.9. The NMOS devices MNA2 and MNB2
have W N/LN ratios twice that of the inverter of section 23.9, since these make up a two transistor pulldown path. All other NMOS devices have the same
WN/LN ratios as the section 23.9 inverter since each
consists of single transistor pull-down paths.
The result of this transient SPICE analysis is
shown in Figure 24.24. The XOR function is clearly
realized since the output is low when both inputs are
high or both inputs are low and otherwise the output
is high. Examining the output response, note that the
propagation delay associated with this gate is nearly
twice that which resulted from the SPICE simulation
of the (one stage) CMOS inverter of section 23.6.
CHAPTER 24 PROBLEMS
24.1
What logic function is performed by the CMOS
digital circuit in Figure P24.P
24.4
What logic function is performed by the CMOS
digital circuit in Figure P24.4 7
24.2
What logic function is performed by the CMOS
digital circuit in Figure P24.2 7
24.5
What logic function is performed by the CMOS
digital circuit in Figure P24.5?
24.3
What logic function is performed by the CMOS
digital circuit in Figure P24.3?
24.6
What logic function is performed by the CMOS
digital circuit in Figure P24.6 7
402
Chapter 24/CMOS Combinational Logic Gates
q
Your=?
Your=?
-::-
FIGURE P24.1
FIGURE P24.2
Ve
[Pc
VD
[Po
Your=?
[Ne
-::-
FIGURE P24.3
24.7
Draw the NMOS pull-down section and complex
CMOS logic circuit that performs the logic function
24.8
F =AB+ CD
F =(AB+ C)AD
24.9
Also, design the WN/LN ratios for each NMOS
transistor so that this gate will have the transient
response of a CMOS inverter whose N-channel
pull-down MOSFET transistor has WN/LN = 4µ,m/
2µ,m. Use channel lengths of LN = 2µ,m.
Repeat Problem 24.7 for the logic function
Repeat Problem 24.7 for the logic function
F = (A + B)(C + D)
24.10
Repeat Problem 24.7 for the logic function
F = (A + B)(C + D)
Chapter 24
Problems
VDD
,--~ ----~1___J - - - - - - - - ~ L~p~- --- _v, qLr, -- --;
_J
Cr-
v.
oj
P.
VD
LPD
0-
Your=?
i
FIGURE P24.4
oj
v.
0-
Your=?
FIGURE P24.5
403
404
Chapter 24/CMOS Combinational Logic Gates
• o-
V
v. 0 - 0
Your=?
v.o-
FIGURE P24.6
24.11
What logic function is performed by the CMOS
digital circuit in Figure P24.11?
24.19
Figure P24.19 shows the NMOS pull-down section
of a six-input complex CMOS logic gate. What
logic function is performed by this circuit? Draw
the complementary PMOS pull-up section to complete the circuit.
24.20
What logic function is performed by the CMOS
gate in Figure 24.21?
24.21
What logic function is performed by the CMOS
complex logic gate in Figure 24.21?
24.12 What logic function is performed by the CMOS
_ digital circuit in Figure P24.127
24.13 ,.Calculate the total channel area for a symmetric
" two-input CMOS NAND gate using
(a) WN/LN = 4µ,m/2µm for the NMOS transistors
(b) Wp/Lp = 4µ,m/2µ,m for the PMOS transistors
24.14
Repeat Problem 24.13 for a three-input CMOS
NAND gate.
24.22
24.15
Repeat Problem 24.13 for a four-input CMOS
NAND gate.
Modify the gate of Figure 24.21 to provide the inverse of the function it currently performs.
24.23
24.16
What logic function is performed by the CMOS
complex logic gate in Figure P24.16?
What logic function is performed by the CMOS
complex logic gate in Figure P24.23?
24.24
24.17
Modify the gate of Figure P24.16 to provide the
inverse of the function it currently performs.
What logic function is performed by the CMOS
complex logic gate in Figure P24.24?
24.25
24.18
What logic function is performed by the CMOS
complex logic gate in Figure P24.1S?
Sketch the CMOS circuit that performs the logic
function
F =AB+ C + DE
Chapter :?.4
9
1ci[pA
I
VA
O·
~
-~1
·~ll~NA
l
-::-
L.
FIGURE P24.11
FIGURE P24.12
Problems
405
406
Chapter 24/C!vlOS Combinational Logic Gates
I
\_ -H~~ND
--7
FIGURE P24.16
v.
f~---l---------,----{
i
c____ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _J
FIGURE P24.18
-:-
Chapter 24
Problems
407
Your=?
r-0
FIGURE P24.19
VA o-
cF ~ ~ ·~ ~
P,
L-----~
v.
0-
oj
-0
Your=?
JFIGURE P24.23
24.26
F =ABC+ DE+ F
24.27
Sketch the CMOS circuit that performs the logic
function
F =A+ BC+ DEF
24.28
and
Sketch the CMOS circuit that performs the logic
function
Sketch the CMOS circuit that performs the logic
functions
F = AB + CEF + D + GH
F = AB + CEF + D + GH
24.29
Sketch the CMOS circuit that performs the logic
function
F = ABC + DEF + GH + I
24.30
Sketch the CMOS circuit that performs the logic
functions
F = AG + BCH + DE + FI + J
and
F = AG + BCH + DE + FI + J
408
Chapter 24/CMOS Combinational Logic Gates
i
VoUT=?
VC o--
v.
VA
~NA
I
*
FIGURE P24.24
VDD
v.
~
q
i
!
--0
11
-:-
FIGURE P24.31
VOIJT =?
Chapter 24
Problems
409
FIGURE P24.32
24.31
What logic function is performed by the CMOS
complex logic circuit of Figure P24.31?
24.32
What logic function is performed by the CMOS
complex logic circuit of Figure P24.32
24.33
Design a CMOS complex logic circuit that performs
the logical function
24.35
F = ABC + DEF + GJ-J + IJK
and
F=
24.34
24.36
Design a CMOS complex logic circuit that performs
the logical functions
F
= (A +
B)C
+ D(E + F) +
(C
+ H)(I +
n
(G
+
n
and
F=
and
24.37
D + EFG + J-1
(Design for logic only, don't design the W/L ratios)
Design a CMOS complex logic circuit that performs
the logical functions
F
= ABC + D + EFG + J-f
F = ABC +
ABC + DEF + GJ-f + IJK
(Design for logic only, don't design the W/L ratios)
F = AB + CD + E + FGH
(Design for logic only, don't design the W/L ratio)
Design a CMOS complex logic circuit that performs
the logical functions
F
(A
+ B)C +
D(E
+
F)
+
H)(J
+
Design a CMOS complex logic circuit that performs
the logical function
= (AH + B) (C + D + E) + (F + I + n + (C + K)
410
Chapter 24/CMOS Combinational Logic Gates
24.38
Design a CMOS complex logic circuit that performs
the logical fun ctions
24.39
Design a CMOS complex logic circuit that performs
the logical function
F = (AB + CD)E + F + (G + H + l)(JK + L)
F = (A + B)(C + D)(E + F) + G(J-l + l)(J + K)
(Design for logic only, don' t design the W/L ratios)
and
F=
24.40
(A
+ B)(C + D)(E + F) + G(H + l)(J + K)
(Design for logic only, don' t design the W/L ratios)
Make a truth table for the circuit of Example 24.4
for all 32 combinations of low and high inputs. Include states of all NMOS and PMOS transistors,
existence of pull-up and pull -down paths, and output logic state.
CMOS
The CMOS logic gates presented in the previous
chapter all exhibit two consistent characteristics as
follows:
1.
When all inputs are held constant at either V011
or VoLt an output pull-up path to VDD or an output pull-down path to ground is always present.
2.
Output pull-up and pull-down paths are never
present simultaneously.
If neither a pull-up nor a pull-down path are present,
then the output is in a high impedance state. If both
a pull-up and pull-down path are present, the output
is a state of contention. High impedance and contention states are undesirable in straight combinational logic applications. However, a practical use for
high impedance output states is discussed in the
form of a tri-state logic application. In this chapter
two types of CMOS tri-state gates are presented as
follows:
1.
Tri-state inverters and tri-state multi-input logic
gates
2.
CMOS
bi-directional
(switches or pass gates)
transmission
STATE
1.
Static operation (all inputs held constant at Vm
= ground or Voll = VDD) of these logic gates
always provides either an output pull-up path to
VDIJ through P-channel MOSFETs or an output
pull-down path to ground through N-channel
MOSFETs.
2.
Static operation of these logic gates never provides output pull-up and pull-down paths simultaneously.
The present chapter presents CMOS circuits in
which both of these rules are broken. When a combination of inputs to a logic gate provides neither an
output pull-up path to VDD nor an output pull-down
path to ground, the output is said to be in a high
impedance Z-state, which is an open circuit or a
disconnect.
Consider the CMOS circuit of Figure 25.la
which has two inputs and three transistors. Note immediately that there is not a complementing PMOS
device for each NMOS device present (which is intentional for this discussion). The truth table for this
gate will be constructed to observe an output state
that is not present in any of the CMOS logic circuits
studied up to this point.
gates
A common application of tri-state inverters is in driving integrated circuit busses. D-type flip-flops can
also be constructed using either tri-state inverters or
bidirectional transmission gates. Combinational
logic functions can also be constructed using bidirectional transmission gates.
Output Low State VA AND V 8 High
When VA and V8 are both high, NA and Nri are both
active and an output pull-down path to ground is
present. Since V13 is high, P 13 is cutoff and no output
pull-up path to VDD is available. Since an output
pull-down path is present and an output pull-up
path is not, the CMOS circuit of Figure 25.la is in
the output low state for VA and VB high. This verifies
line 4 of the truth table in Table 25.1.
25.1 CMOS LOGIC GATES WITH
HIGH IMPEDANCE Z-STATES
In discussing the CMOS inverter of Chapter 23 and
the CMOS NAND, NOR and even complex CMOS
logic gates of the previous chapter, two elements of
operation are repeatedly demonstrated. These are
listed as follows:
Output High State V8 Low
With V8 low, P 8 is active and an output pull-up path
to VDD is present. Also for V8 low, Nri is cutoff re-
411
412
Chapter 2:i/CMOS Tri--StJtc Cates
19l
I
I
VB u--~
i
r----0
l-1 I
VDD
P.
P.(OFF)
-
!
I
f-- -c
Vour
I
I
I
Vour = floating node (high
impedance Z-state)
_IN.
-7
I
I
~
(a)
(b)
FIGURE 25.1 Two-input Three-transistor CMOS
Digital Circuit with a High-impedance Z--state:
(a) Circuit, (b) With V,, low and VB high neither an
output pull-down path to ground nor an output pull-up
path to V,ll, is present
gardless of the state of NA. With NB cutoff no output
pull-down path to ground is present. With an output
pull-up path and no pull-down path, the CMOS circuit of Figure 25.la is in the output high state. This
corresponds to lines 1 and 3 of the truth table in
Table 25.1.
low, N,, is cutoff and no output pull-down path to
ground is present. With VB high, P 1i is cutoff and no
output pull-up path is present. Hence, for V,, low
and VB high, neither an output pull-down path to
ground nor an output pull-up path to Ytm is available. This corresponds to the equivalent circuit of
Figure 25.16. Since N 1v NB, and PB are all cutoff, the
output voltage of this CMOS circuit is independent
of the transistor input voltages, as well as Vnti and
ground. It was shown in Chapter 17 that the drain-to-source impedance of a cutoff MOSFET is very
high, essentially infinite. With infinite impedance be-
Output High Impedance Z-State
With V;\ low and VB high, the output of the CMOS
circuit in Figure 25.la is in a state which has not yet
been observed in this or previous chapters. With V,,
TABLE 25.1 States of Each N-Channel and P-Channel MOSFET and Presence of Output Pull-Up
and Pull-Down Paths in the Two Input, Three Transistor CMOS Circuit of Figure 25.la for All
Combinations of Low and High Inputs
1
2
3
4
VA
Vs
NA
Ns
Ps
low
low
high
high
low
high
low
high
off
off
on
on
off
on
off
on
on
off
on
off
Pull-Up Path
Pull-Down Path
pl\
none
none
none
none
N,,--N 1i*
pl\
none
VouT
high
Z**
high
low
*For V,, and VB high, a single output pull-down path to ground through N_, and NB is present
**For V,, low and VR high, neither an output pull-down path to ground nor an output pull-up path to V1m is present
25.l
Uv!OS Logic Cates with High lm11cdancc Z-States
TABLE 25.2 Truth Table for a CMOS Inverter
Including High Impedance Z-State Inputs and
Contention X-State Inputs
z
off
on
off
on
off
off
X
?
?
low
high
Pull-Up
Pull-Down
Path
Path
YouT
yes
no
no
yes
no
yes
no
high
low
z
yes
X
1
VA
o----ol l=-
PA
I_
-
-
Va ~}--------- ------rq [Pa
l_ _ _ _ _ _
'
I
I
[----1
High Impedance Z-Nodes are Floating
A CMOS circuit node in the high impedance Z-state
is floJting re!Jtive to all other voltJges of the gate.
The following chmacteristics of high impedance
Z-state nodes can not be under-emphasized:
1.
High ilTtpedance Z-state nodes Jre NOT at
ground.
2.
High impedance Z-state nodes are NOT at Vrm·
3.
High impedance Z-state nodes have NO driving
ability.
[n other words, a high impedance Z-state node is
disconnected from the rest of the gate. A statement
that best describes J node in a high impedance
Z-state is
A gate input cannot be driven by a node
in a high impedance Z-state
To demonstrate this, refer to Table 25.2. This is a
truth table for a CMOS inverter where inputs of
Z-states (and X-states exp!Jined in detail in the following sub-section) are considered. A CMOS inverter driven by a high impedance Z-state input also
has J high in,pedance Z-state output and provides
no useful logic.
The following example demonstrates another
CMOS circuit with output high impedance Z-states.
l
-: qLlPc
? "" NMOS and PMOS modes of operation for input
X-state are unpredictable
tween the output and Vrn 1 and the output and
ground, the output terminal is referred to as being in
a high impedance Z-state. This output state is notated in truth tables by a Z as shown in line 2 of Table
25.1.
413
r----0 V
I
--~' -----i
l-~
8
Otrf
~ i--~c
L_T _
_J
FIGURE 25.2 Three-input, five transistor, CMOS
Digital Circuit with High-impedance Z-states for
Example 25.1
Example 25.1 CMOS Circuits with Output
High Impedance Z-states
Determine if any combination of low and high inputs
results in the output high impedance Z-state for the
CMOS circuit of Figure 25.2.
Solution (Output High State) Examining the
CMOS circuit of Figure 25.2, an output pull-up path
to V1m is present only if all inputs are low. This corresponds to line 1 of the truth table in Table 25.3.
Solution (Output Low States) If either Vii or Vc
is high, the corresponding N-channel MOSFET is active and an output pull-down path to ground is present. Also, a high input cuts off the corresponding
PMOS device and eliminates the presence of a pullup path. This corresponds to lines 2, 3, 4, 6, 7, and 8
of Table 25.3.
Solution (Output High Impedance Z-state)
When Vi\ is high, Pi\ is cutoff and regardless of the
other inputs, no output pull-up path is present.
When VB and Ve are low, NB and Ne are cutoff and
no output pull-down path is present. Hence, with V,\
high and Vil and Ve low, neither a pull-up nor pull-
414
Chapter 25/CMOS Tri-State Gates
TABLE 25.3 States of Each N-Channel and P-Channel MOSFET and Presence of Output Pull-Up
and Pull-Down Paths for the CMOS Circuit of Figure 25.2 for all Combinations of Low and High
Inputs
1
2
3
4
5
6
7
8
VA
Va
Ve
NB
Ne
PA
Ps
Pc
Pull-Up Path
low
low
low
low
low
low
low
on
on
on
on
on
on
off
off
on
off
on
off
none
high
low
off
on
off
on
P,\-PR-Pc
high
high
off
off
on
on
none
none
none
Ne
NB
NR, Ne
low
low
low
high
high
high
high
low
low
hiP"h
u
low
off
off
off
off
on
on
off
off
on
off
on
off
none
none
none
none
z
high
off
on
off
on
none
high
off
off
on
on
Ne
N1,
Nri, Ne
low
low
low
high
high
high
low
down path is present and the output is in a highimpedance Z-state. This state corresponds to line 5
of Table 25.3. Hence, the CMOS circuit of Figure 25.2
has a single output high impedance Z-state.
25.2 CMOS LOGIC GATES WITH
CONTENTION X-STATES
The previous section discussed CMOS circuits where
certain combinations of inputs provide neither pullup paths nor pull-down paths at the output terminal.
The present section discusses the situation when
combinations of low and high inputs provide output
pull-up paths to V00 and output pull-down paths to
ground simultaneously. When a node is subject to
simultaneous pull-up and pull-down paths the logic
state of the node is referred to as a contention
X-state.
Examine the two input, two transistor CMOS
circuit of Figure 25.3a. Note that this is essentially a
CMOS inverter with two separate inputs. The truth
table for this gate will be constructed to observe the
presence of any contention X-states.
Output High State VA and V 8 Low
With both inputs to the CMOS circuit of Figure 25.3a
low, P 13 is active and NA is cutoff. Thus, an output
pull-up path is present and an output pull-down
path is not. The CMOS circuit of Figure 25.3a is
therefore in the output high state for both inputs low.
This corresponds to line 1 of Table 25.4.
Pull-Down Path(s)
VouT
Output Low State VA and V 8 High
When both inputs to the CMOS circuit of Figure
25.3a are high, P 13 is cutoff and NA is active. An output pull-down path is therefore present and no output pull-up path is available. Thus, for both inputs
high the CMOS circuit of Figure 25.3a is in the output low state. This corresponds to line 4 of Table
25.4.
Output High Impedance Z-State VA
Low and V8 High
With VA low and Vil high, both NA and N 8 are cutoff.
With both MOSFETs cutoff neither a pull-up nor a
pull-down path is available and the circuit of Figure
25.3a is in an output high-impedance Z-state. This
corresponds to the equivalent circuit shown in Figure
25.36. The output for this state is floating. This corresponds to line 2 of Table 25.4.
Output Contention X-State VA High
and V8 Low
If VA is high and V8 is low, Vcs,N > VrN and Vsc,r >
-V-1" and both MOSFETs are active. With both
MOSFETs active, output pull-up and pull-down
paths are simultaneously present and the output is
at a voltage between ground and VoD• This combination of input voltages is depicted in Figure 25.3c.
If the output voltage resulting from this state is midway between VDD and ground, both MOSFETs are
operating in the linear region of operation. Such a
voltage is neither sufficient as an input low voltage
nor an input high voltage and therefore cannot be
25.2
v.~
CMOS Logic Gates with Contention X-Statcs
&----- -i"::
:
~-: :
VB
p .(OFF)
.---L
j ~
Your
r---~ :- -
415
Your= floating node (high
impedance Z-state)
·~ l
Y
VA o
-.:-
N (OFF)
(b)
(a)
Your = logic level is undefined
(contention X-state)
-.:-
(c)
FIGURE 25.3 Two-input, Two-transistor CMOS
Digital Circuit with a High Impedance Z-state and a
Contention X-state (Example 25.2): (a) Circuit, (b) With
VA and VB high neither an output pull-down path to
ground nor an output pull-up path to VDD is present, (c)
With VA high and VB low an output pull-down path to
ground and an output pull-up path to V0 D are present
simultaneously
TABLE 25.4 States of Each N-Channel and P-Channel MOSFET and Presence of Output Pull-Up
and Pull-Down Paths for the CMOS Circuit of Figure 25.3a for All Combinations of Low and High
Inputs
1
2
3
4
VA
Vs
NA
Ps
Pull-Up Path
Pull-Down Path
VouT
low
low
high
high
low
high
low
high
off
off
on
on
on
off
on
off
PB
none
none
none
PB
NA
NA
high
Z*
X**
low
none
*For VA low and VB high neither an output pull-down path to ground nor an output pull-up path to VDo is present
**For VA high and VB low an output pull-down path to ground and an output pull-up path to VDo are present
416
Chapter 25/CMOS Tri-State Gates
used to drive the input of another CMOS logic gc1te.
The output pull-up ilnd pull-down pc1ths are said to
be in contention and the output state resulting from
this situation is said to be a contention X-state. This
corresponds to line 3 of Table 25.4.
In the following example, the magnitude of the
output voltage for the CMOS circuit of Figure 25.3a
in the contention X-state is calculated for typical
CMOS designs.
Example 25.2 Output Voltage
of Contention X-State
Calculate the output voltage of the CMOS circuit of
Figure 25.3a for the output contention X-state. Use
Vm ground = 0 and VDLJ = 5 V. For the MOSFETs,
use the values kN = kp = 80 µ,ANc and VTN = -VT!'
= 1 V (these are the values for the symmetric CMOS
inverter of Example 23.2).
=
Solution To solve for the output contention voltage, equate the linear drain currents for the N- and
P-channel MOSFETs to obtain
or
Example 25.3 CMOS Circuits with Output
Contention X-States
Determine if any combination of low and high inputs
results in output contention X-states for the CMOS
circuit of Figure 25.4.
Solution (Output Low States) If all inputs are
high then all NMOS devices are active and all PMOS
devices are cutoff. Thus, output pull-down paths are
available and no output pull-up path is present. The
CMOS circuit of Figure 25.4 is therefore in the output
low state for all inputs high. This corresponds to line
8 of Table 25.5.
Also, if VA is low with VHand Vc high, the circuit
is still in the output low state since Nil and Ne are
still active and all P-channel MOSFETs are cutoff.
1l1is corresponds to line 4 of Table 25.5.
Solution (Output High States) If either Vn or Vc
is low, the corresponding PMOS transistor is active
providing an output pull-up path. With either Vil or
Ve low, no output pull-down path is present through
the series Nil-Ne combination. Also, ifV,\ is low with
either Vil or Vc low, then no output pull-down path
is avai!Jble and the CMOS circuit of Figure 25.4 is in
the output high state. TI1ese states correspond to
lines 1, 2, and 3 of Table 25.5.
Solution (Output Contention X-State) If either
VR or Ye is low or both are low, then an output pull-
Substituting Vcs,N = VINJ\ = Vu1 I = 5 V, Vsc,I' = v,JD
- V1:--:ll = VDD - V0 1_ = 5 V, Vns,N = VouT, and VsLJ.1'
= VDD - VouT yields
VzJLrr}
-
(80µ,) [(5) - (l)JVou1 - -
{
2
= (80µ,) { [(5) + (-1)](5 - V0 u 1 )
-
2
(5 - V
) }
OUT
2
Collecting like terms and solving for Your yields
Vour
Von
= 2.5 V = -
2
= Vx
Thus, the output voltage Vx for the contention state
is half of the supply voltage V1m which is a direct
result of the symmetry for the P- and N-channel
devices.
FIGURE 25.4 Three-input, Five-transistor, CMOS
Digital Circuit with Contention X-states for Example 25.3
25.3
CMOS Tri-State (Clocked) Inverters
417
TABLE 25.5 States of Each N-Channel and P-Channel MOSFET and Presence of Output Pull-Up
and Pull-Down Paths for the CMOS Circuit of Figure 25.4 for All Combinations of Low and High
Inputs
1
2
3
4
5
6
7
s
VA
VB
Ve
NA
NB
Ne
PB
Pc
Pull-Up Path
low
low
low
low
low
low
high
high
low
high
low
high
off
off
off
off
off
off
on
on
off
on
off
on
on
on
off
off
on
off
on
off
Ps, Pc
Ps
Pc
none
none
none
none
high
high
high
high
low
low
high
high
low
high
low
high
on
on
on
on
off
off
on
on
off
on
off
on
on
on
off
off
on
off
on
off
Ns-Nc
NA
NA
NA
NA, N8 -Nc
up path is present. If VA is high, then NA is active
and an output pull-down path is also available. Thus,
for VA high and V13 and/or Ve low, the CMOS circuit
of Figure 25.4 is in an output contention X-state. This
verifies lines 5, 6, and 7 in Table 25.5 providing three
contention X-states.
25.3 CMOS TRI-STATE (CLOCKED)
INVERTERS
Figure 25.5a displays a three-input four-transistor
CMOS logic gate that has a high impedance Z-state
for certain combinations of inputs. The inputs of this
gate are labeled V1N, VNEN, and Vf'EN (these subscripts are explained in the following sub-section).
Operation of this gate to exploit the high impedance
output Z-states is useful in CMOS integrated circuits. Before explaining this statement, the truth table is constructed in the following example.
Truth Table of
CMOS Tri-State Inverter
Pn, Pc
Pn
Pc
none
Pull-Down Path(s)
VouT
high
high
high
low
X
X
X
low
for VrN and VEN high, the CMOS gate of Figure 25.5a
is in the output low state. This establishes lines 6 and
8 of Table 25.6.
Solution (Output High State) When V1N and
VrEN are low (regardless of the state of VNEN), both
PMOS devices are active and both NMOS devices
are cutoff (conduct zero current). An output pull-up
path to VDo is then present through P 1 and PEN and
no output pull-down path to ground is present.
Therefore, with V1N and VPEN low, the CMOS gate
of Figure 25.5a is in the output high state. This establishes lines 1 and 2 of Table 25.6.
Solution (Output High Impedance Z-States) If
either V1N is low and VPEN is high (regardless ofV NEN)
or V1N is high and VNEN is low (regardless of VpEf,:),
neither an output pull-up path nor an output pulldown path is present. Thus, for any of these combinations of inputs, the circuit of Figure 25.5a is in a
high impedance output Z-state. This establishes
lines 3, 4, 5, and 7 of Table 25.6. Since all combinations of inputs have been considered, no output contention X-states are present.
Example 25.4
Construct the truth table for the CMOS gate of Figure 25.5a. Include the state of each transistor and
existence of an output pull-down path to ground or
pull-up path to VDo for each combination of inputs.
Solution (Output Low State) When inputs V1N
and VNEN are high (regardless of the state of VrEN),
the NMOS devices N 1 and NNEN are active and the
PMOS devices Pr and PEN are cutoff. An output pulldown path to ground then exists through N 1 and NEN
and no output pull-up path to VDD is present. Thus,
Tri-State Logic Realization
Examining the truth table of Table 25.6 for the
CMOS circuit of Figure 25.5a, a possible exploitation
of the presence of high impedance output Z-states
is observed.
Logical Inversion Operation
When VNEN is held at a constant high and VPEN is
held at a constant low (lines 2 and 6 of Table 25.6),
the output is the logical NOT of the input. This is
exemplified in Figure 25.5b by showing that NEN is
418
Chapter 25/CMOS Tri-State Gates
~~-----.pe,;(ON)
VIN
r--D
VTINV
V Nor
I
- i~N~
2µmNI
11\.r
tn1'.n
l"'llN~VH)
~ l{,
7
Yoo
-L
VNEN
(a)
(b)
Yoo
Yoo
VPEN
PI
PEN
Pl!N(OFF)
VIN
:---
~
V 2 = floating node (high
impedance Z-state)
m-~=
Nl!N(OFF)
q
NEN
NI
VNEN
-::-
(c)
FIGURE 25.5
(d)
CMOS Tri-state Inverter: (a) Circuit, (b) Inverting state, (c) High-impedance z-state, (d) Circuit symbol
25.4
Appliec1tion of Tri-State Inverters
419
TABLE 25.6 States of Each N-Channel and P-Channel MOSFET and Presence of Output Pull-Up
and Pull-Down Paths for the CMOS Tri-State Inverter of Figure 25.5 for All Combinations of Low
and High Inputs
VIN
VPEN
VNEN
N1
NEN
PEN
P1
Pull-Up Path
low
low
high
high
low
high
low
high
off
off
off
off
off
on
off
on
on
on
off
off
on
on
on
on
P1,:-rP1
4
low
low
low
low
5
6
7
8
high
high
high
high
low
low
high
high
low
high
low
high
on
on
on
on
off
on
off
on
on
on
off
off
off
off
off
off
none
none
none
none
1
2
3
PE,'!-Pl
none
none
Pull-Down Path
none
none
none
none
none
N1-NEN
none
N1-N1l':
YouT
high
high
Z*
z
z
low*
Z*
low
*Denotes an operating state used in tri-state operation
brought into active operation when VNE,'! is high and
Pi::---: is brought into active operation when V1,EN is
low, Hence, V;--;EN and V1,i:;--; can be thought of as inverter enabling signals for active high and low, respectively, Also, the subscripts NEN and PEN stand
for N-enable and P-enable, respectively,
Output High Impedance Z-State Operation
When VNEN is held at a constant low and YnN is held
at a constant high (lines 3 and 7 of Table 25.6), the
output is a high impedance Z-state regardless ofV 1N.
Figure 25.Sc demonstrates this by showing that NE"
is cutoff when VNEN is low and PEN is cutoff when
Yi'EN is high. Thus, regardless of V1N, neither an output pull-down path to ground nor an output pull-up
path to Yn 11 is present Hence, VNEN low ,:md V1,EN
high disable the logical NOT operation of this gate,
Complementing Enable Inputs
Since enabling the circuit of Figure 25.Sa for inverting
operation requires the active high enabling input
VNEN to be high and the active low enabling input
Vl'EN to be low, the two enabling inputs are c01nplcmc11tary enabling inputs, one for the N-channel
MOSFET and the other the P-channel MOSFET.
Tri-State Logic
If operation of the CMOS gate in Figure 25.Sa is limited to the combination of inputs listed in lines 2, 3,
6, and 7 of Table 25,6, three output logic states are
possible: output high logic, output low logic, and a
high impedance output Z-state, This is referred to as
tri-state logic and the circuit of Figure 25.Sa is referred to as a tri-state inverter, or sometimes as a
clocked inverter. The circuit symbol used for the tristate inverter is shown in Figure 25.5d, This circuit
symbol represents an inverter with two additional
inputs at the top and bottom of the symbol. The input at the botton, is the active high Y;--;EN NMOS
transistor enabling input and the input at the top of
the symbol is the active low VPEN PMOS transistor
enabling input To distinguish between the two complementing enabling inputs, an inverting bubble denotes the active low Vl'EN input.
25.4 APPLICATION
OF TRI-STATE INVERTERS
The application of tri-state logic with high impedance Z-state outputs is demonstrated in Figure 25.6a.
Note that the outputs of four separate tri-state inverters are connected to a single node. With the simple two-state inverters of the previous chapter (or the
NAND, NOR, or even more complex logic gates),
this connection would cause logic contention, if the
gates were in different output states. However, the
circuit arrangement in Figure 25.6a limits operation
of the tri-state inverters in output states (outside of
the high impedance Z-state) to a single gate at any
given time.
Each tri-state inverter of Figure 25.6a is accompanied by a single two-state inverter between the
two complementing enable lines. Thus, if the signal
420
Chapter 25/CMOS Tri-State Gates
output of multiple
tri-state
buffers
connected to a
single node
A
D
L
1
control
signals
0
2:4 decoder
only one tri-state buffer at a
time is enabled - thus, the
multi-driven node is never in
contention
(a)
FIGURE 25.6
(a) Outputs of several tri-state inverters connected to a single node
labeled AEN is high, the tri-state inverter TA is operating in its inverting state. If AEN is low, then TA is
operating in a high impedance output Z-state. Likewise, T8 is operating in an inverting state if BEN is
high and operates in a high impedance outp~t
Z-state if BEN is low. Similar situations for the tnstate inverters Tc and TO exist, for the logic states of
CEN and DEN, respectively.
Each of the enable signals is provided from a 2: 4
demultiplexer. Thus, at any given time, only one enable signal (AEN, BEN, CEN, or DEN) is high. The tristate inverter corresponding to the high enable line
is operating as an inverter and the other three tristate inverters are in output high-impedance
Z-states, since their corresponding enable lines are
low.
Example 25.5 Tri-State Inverter
Circuit Embodiment
Determine the operation of the circuitry in Figure
25.6a if the AEN enable signal is high and the BEN,
CEN, and DEN enable signals are all low.
Solution Figure 25.6b shows the circuitry of Figure
25.6a with AEN high and BEN, CEN, and DEN low. For
this situation, TA is operating as an inverter providing
the logic signal NOT A. T8 , Tc, and T0 are all in highimpedance output Z-states and act as open circuits
to their output nodes in the same way a cutoff pulldown NMOS device and a cutoff pull-up PMOS device acts as an open circuit to the output node inside
an individual logic gate.
25.4
Application of Tri-State Inverters
421
driven by A
~ /
IBC
A
00-
-------+----~~D
TD;
D"'low
B"'low
0
2
3
Tu, Tc, and TD are all in high
control
signals
2:4 decoder
impedance output Z-states
(essentially
disconnected
from the output node) - TA is
operating as an inverter
(b)
FIGURE 25.6 (continued)
(b) Tri-state inverter TA is enabled; T8 , T0 and T0 are all disabled
Example 25.6 D-Type Flip-Flop with CMOS
Tri-State Inverters
Figure 25.7 shows a D-type flip-flop realized with tristate inverters. Determine its operation.
Solution (CK High) If the input labeled CK is
high, then the tri-state inverter T1 is enabled and Tr
is in an output high-impedance Z-state. For CK high
the node labeled MEM is therefore driven by the
logic state D.
Solution (CK Low) If the CK input is low, then
the tri-state inverter TF is enabled and T1 is in an
output high-impedance Z-state. The node labeled
MEM is therefore driven by Q for CK low. Note that
with TF enabled, the loop containing the nodes
MEM and Q, the inverter IMEM, and tri-state inverter
TF make up a stable feedback loop.
The previous example demonstrates a practical
use for tri-state inverters in circuitry that would otherwise require a multiplexing of signals. The following sub-section discusses the application of tri-state
inverters in digital integrated circuits that would not
422
Chapter 25/CMOS Tri-State Gates
inverting when CK
low
Z-state
output when CK
high
CK,,___~~,~ 1
i
\
7'~
25.6 ORDERING OF STACK
TRANSISTORS IN TRI-STATE
INVERTERS
lcK~-
--+--~~
1
!
Do--~
~ 'T,
~ IMEM
/~..
inverting when CK
high
Z-state
output when CK
is low
FIGURE 25. 7
Note that since the eight input bus BUS[7: OJ is
driven by tri-state inverters the bus carries the inversion of the signals driving it. Hence, these signals
should be inverted before used elsewhere in the
circuit.
~--o Q
~
·"'-..
this node driven by
only one tri-state
inverter
O-type Flip-flop Realized with Tri-state
Inverters
only require huge multiplexors but large amounts of
metal to connect the internal blocks of circuitry.
25.5 INTEGRATED CIRCUIT BUSes
UTILIZING TRI-STATE INVERTERS
Digital integrated circuits containing many registers
often employ the fabrication of a bus. A bus is an
array of wires intended to deliver a desired array of
signals to or from any number of register inputs or
outputs. Figure 25.8 shows a portion of such circuitry. Eight wires labeled BUS [7: O] can be driven by
any of the outputs of four eight bit registers labeled
A, B, C, or D. The signals labeled A[7:0] drive eight
tri-state inverters with a single two-state inverter
providing the register enabling signal AEN. The signals labeled B[7: O] drive eight different tri-state inverters, as do C[7:0] and D[7:0], each with a single
two-state inverter to invert the enable signals BEN,
CEN, and DEN, respectively. The advantage of a bus
is the alleviation of huge multiplexors and separate
wiring for every register output to such a multiplexor
that would otherwise be needed. Such buses are employed in all modern microprocessors and memories.
Figure 25.9 shows a three-input four transistor
CMOS circuit that realizes the same truth table of
Table 25.6 and hence also functions as a tri-state inverter. This new circuit, however, has placed the
NMOS and PMOS devices serving as enabling inputs at the bottom and top of the stack, respectively,
while the tri-state inverter of Figure 25.5a placed the
MOSFETs corresponding to the enabling inputs in
the middle of the stack. Either one of these circuits
can properly be used as a tri-state inverter. Connection of the enabling inputs to the middle of the stack
MOSFETs or the top and bottom of the stack
MOSFETs depends upon how often the enabling
lines will change states. If the enabling signals
change state more often than the input voltage, then
the enabling signals should be connected to the middle of the stack MOSFETs and the inverter input
voltage should be connected to the top and bottom
of the stack MOSFETs as in Figure 25.5a. If the input
voltage changes state more often than the enabling
inputs, then the enabling signals should be connected to the top and bottom of the stack MOSFETs
and the input voltage should be connected to the
middle of the stack MOSFETs as in Figure 25.9. Such
arrangements provide for an overall faster output
switching speed.
25.7 TRI-STATE LOGIC OF
MULTI-INPUT LOGIC FUNCTIONS
Realization of tri-state logic embodying other combinational logic functions, other than inversion, is
also possible. If the NMOS and PMOS transistors in
the shaded box of Figure 25.9 are replaced with the
MOSFET configurations used between V00 and
ground for two-state logic output circuits, tri-state
realization of that particular function will be realized.
25.7 Tri-State Logic of Multi-Input Logic Functions
423
B[7:0]
B!!N
01234567
BUS[7:0]
FIGURE 25.8 8-bit Data Bus Driven by Four Register
Outputs; each bit of each register output has a single tristate inverter driving a corresponding bus line; ENA,
ENB, ENC, and END are the enabling signals of register
A, B, C, and D drivers, respectively-one enable signal at
most is high at any given time
424
Chapter 25/CM0S Tri-State Gates
Tri-State NAND Gate
realizes the same truth
table as the CMOS
tri-state inverter of
Figure 25.5
Figure 25.10a shows a four transistor NAND configuration placed between the enabling input N- and
P-channel MOSFETs. A truth table for all possible
combinations of inputs will verify that this gate realizes a tri-state NAND function. The circuit symbol
for this gate is shown in Figure 25.10b. This is simply
the circuit symbol of a NAND gate with enabling
inputs at the top and bottom of the symbol as is used
for the tri-state inverter.
Non-Inverting Tri-State Logic
CMDS Tri-state Inverter with Enabling
PM0S and NM0S at the Top and Bottom of the Stack
FIGURE 25.9
If a non-inverting tri-state logic gate is desired, a two
stage gate is required. Caution must be used in the
ordering of the stages. If the tri-state logic gate feeds
a two-state inverter as in Figure 25.11a, the two-state
inverter stage will be driven by a high-impedance
Z-state, whenever the tri-state inverter is disabled.
This will create unpredictable Vcx: 1 states and will
not provide proper tri-state operation. Figure 25.11b
shows the correct way to construct a non-inverting
pl!N
--. Vw.~..,
B
Vn
TNAND
A
Nl!N
(a)
FIGURE 25.10
CMOS Tri-state NAND Gate: (a) Circuit, (b) Circuit symbol
(b)
25.7
VPEN
T
...,.
J:-
~q [
V00
2~=
-/
A•
_ __...,..__..
1~,-:'l; Pm
,
I
I
Tri-State Logic of Multi-Input Logic Functions
1-~ [-7 ~
er
tri-state inverter can
feed
inverter
with
high-impedance Z-states
this
results
in
unpredictable inverter
I
P,
[:,~Po/
'---------0 Your
~-
NEN
__.. ,. . ,.V-...,.
425
I [__ J ~
7 __ ,
-
N
0
l
l_l lliN,
THIS WON'T WORK!
(a)
Non-inverting tri-state output
~
(b)
FIGURE 25.11 Obtaining a Non-inverting Tri-state
Buffer: (a) A tri-state inverter feeding an inverter will
produce unpredictable outputs when the tri-state inverter
is in its output high-impedance Z-state, (b) Inverting a
signal prior to the tri-state inverter provides a noninverting tri-state buffer
426
Chapter 25/CMOS Tri-State Gates
vPEN
A
$
B
NEN
(a)
FIGURE 25.12
(b)
CMOS Bi-directional Transmission Gate (Switch): (a) Circuit, (b) Circuit symbol
tri-state gate. A signal is inverted and then fed into
the tri-state inverter. High-impedance Z-states occur
directly at the output of this non-inverting tri-state
buffer as should be the case.
25.8 CMOS BI-DIRECTIONAL
TRANSMISSION GATE (SWITCH)
Circuit and Symbol
Figure 25.12a displays a parallel NMOS-PMOS configuration. The circuit is called a CMOS bi-directional transmission gate or CMOS switch. This
gate also acts as a non-inverting tri-state logic element that can transmit a signal in either direction.
That is, signal transmission occurs either from VA to
VB or from VB to VA as symbolically indicated in Figure 25.126. CMOS bi-directional transmi?sion gates
are generally connected between the output and input of CMOS combinational logic gates. General operation will then be that of an output load capacitance charging and discharging between VoL and
VOH· As will be seen in the following discussion of
the CMOS transmission gate operation, the channel
ends of the constituent MOSFETs are alternately defined as drain and source depending upon the polarity of voltage biasing this logic element.
CMOS Bi-Directional Transmission
Gate Operation
Enabling of Signal Transmission
Note that the signal inputs to the gate terminals of
the NMOS and PMOS transistors are labeled VNEN
and VPE:s:• In order to enable bi-directional transmission of signals through the NMOS transistor, V NEN
must be high so that the NMOS gate voltage is positive with respect to the source. Conversely, VPEN
must be low so that the gate terminal of the P-channel MOSFET is negative with respect to its source
and the PMOS device is enabled for bi-directional
transmission of signals. Thus, simultaneously holding V NEN high and VPEN low enables the CMOS
transmission gate for bi-directional transmission of
signals. With VNEN low and VrEN high, both the
N- and P-channel MOSFETs are cutoff and signals
can not be transmitted in either direction through the
CMOS transmission gate. The following section
elaborates on this further.
Charging of Load Capacitance
Figure 25.13a shows a CMOS bi-directional transmission gate connected between a voltage source
and load capacitance. The enable signal VNEN is high
and VPEN is low. With the input voltage positive, the
N- and P-channel MOSFETs will source current to
charge the load capacitor. Figure 25.13 shows a step-
25.8
CMOS Bi-Directional Transmission Gate (Switch)
427
VIN(V)
YourCV)
VDD
PM
line
NMOS channel end
at higher voltage
I------·-----f--------------------------~-NMOS cutsoff
:
-VDD-VTN
enters
mode
:
-----~-P_M_O_S_an_d_NM
__
O_S_ ___. t(ns)
enter saturation mode
(b)
(a)
charged
capaciter can
not discharge
through cutoff
MOSFETs
Ps(OFF)
i~- j
N 5 (OFF)
'
I
¼!+voo
i-
(c)
FIGURE 25.13 CMOS Bi-directional Transmission
Gate Charging a Load Capacitance: (a) Circuit schematic,
(b) Step voltage input and output response, (c) With
brought high and VNEN brought low while capacitor
is charged, capacitor can't discharge through cutoff
MOSFETs regardless of V1N
VPEN
428
Chapter 25/CMOS Tri -State Gates
up input voltage and the resulting output voltage re sponse appearing across the capacitor. The channel
end of the NMOS device held at V,N is at a higher
voltage than the channel end at the capacitor. Thus,
during charging of the load capacitance, the drain
and source of the NMOS device are the channel ends
at V,N and Vmm respectively. Since the PMOS channel end at Your is at a lower voltage with respect to
the channel end at V, N, the drain and source of P s
are the channel ends at Your and V,N, respectively,
during load capacitance charging.
Assuming the capacitor initially uncharged 0/c:
= 0), prior to the input rising 0/, N = 0), Vcs,N = VoD
and V0 s,N = 0, the NMOS device is active and operating in the linear mode with Io,N = 0. The PMOS
source-to-gate voltage is Vsc, r = 0 < -Vw, so the
P-channel MOSFET is cutoff. Hence, neither
MOSFET conducts a current and
l e = Io,N (LIN)lvt1sN=o
+ Io,r(OFF)
=
0
Thus, the capacitor remains completely discharged.
After the input low-to-high transition, V, N
equals a constant VoD and V5 c,r = Yoo and Yso,r =
V00 bringing the PMOS device into the saturation
mode of operation. The drain-to-source voltage of
the N-channel MOSFET rises to Vos,N = V00 bringing the NMOS device also into the saturation mode
of operation. The capacitor now begins to charge
through both MOSFETs with
Ic(charging)
= l 0 ,N (SAT) + l 0 _,,(SAT)
As the load capacitance charges, the capacitor
voltage begins to rise. When VoUT = Ve reaches
-VTP, the source-to-drain voltage has decreased to
Vso, r = V00 + VTP :-s Vsc, r + VT,I' and the PMOS
device enters the linear mode of operation. The capacitor charging current is
lc(charging)
= 10 ,N (SAT) + I 0 _,,(LIN)
As the capacitor charges further, the output
eventually rises above Your= V00 - V,N and Vcs, N
< VTN, cutting off the NMOS device. The PMOS de vice, however, still operates in the linear mode. The
capacitor charging current therefore drops to
I e(charging)
= 10 ,N(OFF) + l 0 _p(LIN) = I 0 y(LIN)
Since the PMOS device will remain active all the way
up to VoUT = V00 the load capacitance can be
charged all the way to V00 . Thus, unlike the NMOS
transmission gate, th e CMOS bi -direction al transmission gate can transmit signals rail-to-rail.
Disabling Transmission of Signals
with Capacitor Charged
With the output load capacitor charged to Vc = V0 0
and the enabling signals VNEN and VPEN brought low
and high, respectively, the CMOS transmission gate
is disabled . This situation is illustrated in Figure
25 .13c where You r remains at V00 .
Discharging of Load Capacitance
With VNEN high and V,,EN low, a charged load ca pacitance can discharge through the CMOS bi -di rectional transmission gate . Figure 25.14a shows the
CMOS bi-directional transmission gate of Figure
25 .13a with the input voltage brought to ground
0/Nr:--: = v,)I) and vl'EN = 0). Figure 25.146 shows an
input step down voltage and the resulting voltage
across the discharging load capacitance . The capacitor has an initial voltage Vc = VDIJ for the following
discharge operation description.
After the input is switched high-to-low, the
channel end of the NMOS transistor at Your is at a
higher potential than the channel end at V,N - Thus,
for discharging the load capacitance, the NMOS
drain and source terminals are the channel ends at
YoUT and V, N, respectively (opposite of that for
charging). The channel end of the PMOS device at
Y1N is at a lower potential. The drain and source
regions of the PMOS during load capacitance discharge are therefore the channel ends at Y, N and
YouT, respectively.
After the input high-to-low transition, Y1r-,.; is
held constant at ground . Thus, Vcs,N = V os,N = Yoo
and thus the N-channel MOSFET is operating in the
saturation mode . The source-to-gate and source-todrain voltages of the PMOS device are Vsc ,r = Y50 y
= Y00 . The PMOS transistor is therefore also operating in the saturation mode. Hence, the load ca pacitance begins to discharge with a current given by
Ie(discharge)
= l 0 ,N (SAT) + l 0 y(SAT)
As the load capacitance discharges, the voltage
across the capacitor (and the output) begins to drop.
When the output voltage drops to Your = Y00 YTN, the NMOS drain-to-source voltage drops to
VDs.N = Yoo - VTN :-S Ycs,N - Vn.: and the NMOS
25.8
CMOS Bi-Directional Transmission Gate (Switch)
429
Vm(V)
~
0
'--~~~----------+. t(ns)
r-0--
!
Vour(V)
.l
PMOS and NMOS
enter saturation mode
NMOS channel end
at higher voltage
PMOS cutsoff
(b)
(a)
FIGURE 25.14 CMOS Bi-directional Transmission
Gate Discharging a Load Capacitance: (a) Circuit
schematic, (b) Step-down voltage input and output
response
transistor enters the linear mode of operation. The
capacitor now discharges with a current
is disabled and the load capacitance cannot be
charged regardless of the value of VrN• This situation
is illustrated in Figure 25.15 in which VoUT remains
zero.
Ic(discharge) = In.N(LIN)
+ I 0 _p(SAT)
After the capacitor discharges to below the voltage Vc = -Vw, the source-to-gate voltage of the
PMOS transistor drops below Vscy < -Vw and the
PMOS device cuts off. Thus, the capacitor discharging current drops to
lc(discharge) = l 0 ,N(LIN) + 10 ,p(OFF) = 10 ,N(UN)
Since the NMOS device has Vcs,N held constant at
V0 D, N 5 will remain active until the capacitor completely discharges to Ve = VDs,N = 0 and ID.ts-: = 0.
Disabling Transmission of Signals
with Capacitor Discharged
With the capacitor discharged, if VNEN is brought low
and VPEN brought high, the CMOS transmission gate
Bi-Directionality of Signal Transmission
The previous qualitative analysis demonstrated that
the transmission of signals through the CMOS transmission gate of Figure 25.12a is in fact bi-directional.
That is, signal transmission was demonstrated in one
direction by charging of a load capacitance, the
transmission of VDD from one side to the other. Signal transmission in the opposite direction was
demonstrated by discharging of the capacitor. An
important characteristic exhibited by the CMOS bidirectional transmission gate that was not present
with the NMOS transmission gate of section 22.6 (or
a single transistor PMOS transmission gate) is
430
Chapter 25/CMOS Tri-State Gates
VDD
o
VPEN
discharged
capaciter can't
charge
through cutoff
MOSFETs
:----:
I
Ps(OFF):~~our
i
7+
Ns(OFF)
Ci_!-
0V
FIGURE 25.15 With VPEN High and Vr--:Et-: Low,
Capacitor Cannot be Charged Through Cutoff MOSFETs
regardless of V1N
CMOS bi-directional transmission gates
exhibit non-degraded rail-to-rail
transmission of signals
Analytical analysis of the time required for a CMOS
transmission gate to charge and discharge a load capacitance is somewhat mathematically rigorous and
is left as a homework problem.
The following example determines load capacitance charging and discharging times with a SPICE
simulation.
Example 25.7 SPICE Simulation of CMOS
Bi-Directional Transmission Gate
Perform a SPICE simulation to determine charging
and discharging times of a load capacitance of CL =
0.1 pF through a CMOS bi-directional transmission
gate. Use channel width/length ratios of Wp/Lp =
10µ,m/2µ,m and WN/LN = 4J.Lml2J.Lm.
Solution Figure 25.16 shows a capacitive loaded
transmission gate with appropriate SPICE labelings.
The SPICE input CIRcuit file for this circuit is as follows:
*CMOS Bi-Directional
*Transmission Gate
VPEN 8 D PULSE<SV DVD DD SNS
FIGURE 25.16 CMOS Bi-directional Transmission
Gate with Appropriate SPICE Labelings
+ 1DNS)
VNEN 7 D PULSE(OV SV DD D SNS
+ 1DNS)
VIN 4 D PULSE<DV SV DD D 7-SNS
+ 1SNS)
VDD 2 D DC SV
-MODEL NMOSFET NMOS(VTO=1
+ KP=4DU GAMMA=O-37 PHI= □ -6
+ CBD=3-1E-1S CBS=3-1E-1S)
MPS 4 8 S 2 PMOSFET W=1OU L=2U
-MODEL PMOSFET PMOS<VTO=-1
+ KP=16U GAMMA= □ -4 PHI= □ -6
+ CBD=3-1E-1S CBS=3-1E-15)
MNS 4 7 SD NMOSFET W=4U L=2U
CL SD
□ -1PF
-TRAN - □ SNS 1SNS
-PLOT V(7) V(8) V(4) V(S)
-END
Figure 25.17a shows the input waveforms of V1N,
VNEN, and V PEN and the resulting voltage response
across the load capacitance. The rise time t, between
the 10% and 90% points is approximately 0.7 ns and
the low-to-high propagation delay is much smaller
at tl'LH = 0.1 ns. The fall time tr between the 90%
and 10% points is 0.8 ns and the high-to-low propagation delay is 0.4 ns.
25.9
Application of CMOS Bi-Directional Transmission Gates
Your= (VA AND
VNEN(V)
5
431
v.) OR [V. AND (NOT V,)]
F=AS +BS
4-3-2-~
1-~
0
0
:
I
2
4
I
I
6
8
I
I
I
10
I
I
I
12
14
I
~
Your
t(ns)
16
V~)
5
4
3
2
1
0---1---1--1--.._____t---+-1.--+--1---1--+ t(ns)
0
2
4
6
8
10
12
14 16
FIGURE 25.18
Switches
CMOS 2: 1 Multiplexor using CMOS
VIN(V)
5
Example 25.8 Two Input Multiplexor
Embodying CMOS Bi-Directional
Transmission Gates
4
3
2
1
O+------l--+--t---'-1--......--+--i--+--+ t(ns)
0
2
4
6
8
10
12
14
16
Your(V)
5-1-.------4
3-·
2
1
0 -1------1--+--t----+--+---"'-I---,--+---. t(ns)
0
2
4
6
8 10 12 14 16
Design a two-input multiplexer utilizing CMOS bidirectional transmission gates.
Solution Figure 25.18 shows a two input multiplexer utilizing two CMOS bi-directional transmission gates and a single inverter. The control signal is
Vs and the input signals to multiplex are VA and VB.
If Vs is high, the transmission gate SA is enabled and
the transmission gate S8 is disabled. The output voltage VoUT is therefore equal to VA· With Vs low, SB is
enabled and S;,. disabled. Thus, VoUT = V8 for Vs low,
with the output voltage realizing
VouT = (VA AND Vs) OR
lVa AND
(NOT Vs)]
or
FIGURE 25.17 Input Voltage Time Waveforms and
Output Capacitance Voltage Response from SPICE
Simulation of CMOS Bi-directional Transmission Gate
F =AS+
BS
Note that the transmission of signals from the multiplexor inputs to the output are non-inverted.
25.9 APPLICATION OF CMOS
BI-DIRECTIONAL TRANSMISSION
GATES
Example 25.9
XOR Gate
The following examples present several applications
for CMOS bi-directional transmission gates.
Figure 25.19 shows an XOR gate realized with
CMOS transmission gates. Verify the XOR operation
by considering all combinations of input states.
CMOS Transmission Gate
432
Chapter 25/CMOS Tri-State Gates
Solution (V, High, VJJ Low) Also noted above, S,\
and SH are enabled and diszibled, respectively, zind
VH is trnnsmitted to the output. Thus, the output is
high for this combimtion of inputs. This rezilizes line
3 of Tzible 25.7.
---------0
I
VXOR
the
(a)
:j~XOR
Solution (Both Inputs Low) With VJ\ low, the
CMOS switch Sil is enabled and SJ\ is disabled.
Therefore, V8 is transmitted to the output. Thus, for
both inputs low, the output is low. This realizes line
1 of Table 25.7.
Solution (Both Inputs High) With VJ\ high, the
CMOS switch SJ\ is enabled and Sn is disabled. Thus,
Vll is transmitted to the output. Hence, the output is
also low for both inputs high. This realizes line 4 of
Table 25.7.
Solution (VA Low, V 8 High) As noted above, with
VJ\ low the CMOS switches SA and S 13 are disabled
and enabled, respectively and VB is transmitted to the
output. Thus, the output for this combination of inputs is high. This realizes line 2 of Table 25.7.
TABLE 25.7 States of Each CMOS BiDirectional Switch and Output State for the
CMOS XOR Gate of Figure 25.19a for All
Combinations of Low and High Inputs
4
gdtC of Figure 25.19.
Analyze the operation of the D-type flip-flop (realized in part with a CMOS transmission gate) of Figure 25.20. CoITtpzire with Example 25.6
FIGURE 25.19 CMOS XOR Gate (a) CMOS Bidirectional transmission gate realization, (b) Circuit
symbol
3
crv10s
Example 25.10 D-Type Flip-Flop with CMOS
Bi-Directional Transmission Gates
(b)
1
2
Solution (Realization of XOR Logic) Since the
output is low for both inputs low and both inputs
high, zind the output is high for either input high and
the other input low, the XOR truth table of Table 25. 7
is verified zind the XOR logic function is rezilized by
VA
VB
SA
SB
VouT
low
low
high
high
low
high
low
high
disabled
disabled
enabled
enabled
enabled
enabled
disabled
disabled
low
high
high
low
Solution If the CK input is high, then the CMOS
switch S1 is enabled and the CMOS tri-state inverter
TF is diszibled Thus, for CK high, the node lzibeled
MEM is driven by the input D (noninverted) through
S1• For CK low, the CMOS switch S1 is disabled and
the tri-state inverter Tr- is enabled. As with the Dtype flip-flop of Example 25.6 (Figure 25.7) with CK
enabled, the loop containing the nodes MEM and
Q, the inverter I:viE~-,, and the tri-state inverter Tr:,
make up a stable feedback loop. Since the input D is
transmitted noninverted to the input of the inverter
l:viE~,, the output of hiE~, is the signal Q zind an inverter is included at the output to reinvert the memory node and give the noninverted output Q.
Compming the D-type flip-flop of Figure 25.20
to the D-type flip-flop of Figure 25.7, the CMOS
switch S 1 has two less transistors than the tri-state
inverter T 1• However, the additional inverter IQ is
necessary adding two transistors. The overall number of transistors for both circuits is therefore twelve.
25.10 DISADVANTAGES OF CMOS
BI-DIRECTIONAL TRANSMISSION
GATES (NON-FAULT GRADABILITY)
A serious disadvantage resulting from the use of
CMOS bi-directional transmission gates is the lack
of full testability of both MOSFETs in the comple-
Chapter 25
Problems
433
allows feedback of Q
to MEM when CK is
low - high impedance
when CK high
o--1t--=~/
/
CK
I
ICK
I
I
I
I
D o-
/
I
-+/"--J~ MEfv![>o~~~,
I
s,
allows _J>assage of
D to :rvIBM when
CK is high - high
impedance
when
CK is low
FIGURE 25.20
-~i
IMEM
'~~
this node driven by
either the tri-state
inverter or the
transmision gate
D-type Flip-flop Realized with CMOS Switches
mentary pair. A method of testing a post-fabricated
integrated circuit called (fault grading), tests a circuit
for expected outputs for as many combinations of
input stimuli as possible. The problem with testing a
CMOS bi-directional transmission gate is that if either the N- or P-channel MOSFETs don't operate
properly, a load capacitance can be partially charged
or discharged. Thus, a mal-fabricated MOSFET in a
CMOS transmission gate pair may not be properly
detected as nonoperational. Therefore, the general
use of CMOS bi-directional transmission gates in
CMOS integrated circuits should be avoided.
CHAPTER25PROBLEMS
25.1
Derive the truth table of Figure P25.1 for all combinations of low and high inputs. Include in the
truth table the state of each transistor, whether an
output pull-up or pull-down path exists, and the
output voltage. Include high impedance Z-states
and/or contention X-states.
25.2
Repeat Problem 25.1 for Figure P25.2.
25.3
Repeat Problem 25.1 for Figure P25.3.
25.4
Repeat Problem 25.1 for Figure P25.4.
25.5
Repeat Problem 25.1 for Figure P25.5.
25.6
Derive the truth table for the CMOS inverter of
Figure P25.6 assuming four different inputs: V1N =
low, V 1N = high, V1N = Z, and V1N = X. Include in
the truth table the state of each transistor, whether
an output pull-up or pull-down path exists, and the
output voltage.
Yoo
v, "~
q LIP,
Your
y
VA
C
1
i
FIGURE P25.1
434
Chapter 25/CMOS Tri-State Gates
Yoo
YPEN
Yoo
9
V,e>~~:__ _
cP,
[ JP~
~◊V-
'J
i ~ .
Your
-!-IL(
1
I
I
0
•
YNEN
FIGURE P25.2
FIGURE P25.5
~--0 Your
FIGURE P25.6
FIGURE P25.3
25.7
Calculate the output voltage of the CMOS circuit
of Figure P25.3 for the output contention X-state.
Use VoL = GND = 0 and VDo = 5 V. For the
MOSFETs, use the values kN = kr = 80 µ.A/V2 and
VTN = -VT!' = 1 V.
Your
--IFIGURE P25.4
25.8
Construct the truth table for the circuit of Figure
25.4 with two inputs VA and V 13 = Ve.
25.9
Construct the truth table for the circuit of Figure
25.9.
25.10
Construct the truth table for the tri-state NAND
gate of Figure 25.10.
25.11
Construct the truth table for the non-inverting tristate logic gate of Figure 25.llb.
25.12
Using a similar circuitry to Figure 25.10, construct
a CMOS tri-state NOR gate with two logic inputs.
Chapter 25
Problems
435
Yoo
0
i
Ve
~ , - ~ ~ · -[P
r- --- ---,
0
Vo
L ---
O
r~E=~·
-q r;p~
Your
-0 Your
V,o
-wF
J_
FIGURE P25.15
FIGURE P25.19
25.13
Construct a truth table for the two-input multiplexor of Figure 25.18 and determine the logic
function at the output.
25.14
Construct a truth table for the XOR gate of Figure
25.19 and verify the logic function at the output.
25.15
Analyze the CMOS circuit of Figure P25.15 and list
the output X and Z-states.
25.16
Analyze the CMOS circuit of Figure P25.16 and list
the output X and Z-states.
25.17
Design a CMOS tri-state NOR gate with two logic
inputs and complementary enabling inputs. (Hi11t:
examine Figure 25 .10)
25.18
Design a tri-state CMOS complex logic gate that
realizes the logic function
F(c11nblerl)
=
A(B
when enabled and has complementary enabling
inputs. (Hint: examine Figure 25.10.)
25.19
Analyze the CMOS circuit of Figure P25.19 and list
the output X and Z-states.
25.20
Design a tri-state CMOS AND-OR-invert logic
gate that realizes the logic function
F(cnab/cd)
= AB + CD
when enabled and has complementary enabling
inputs. (Hint: examine Figure 25.10.)
25.21
Design a six-transistor CMOS tri-state inverter that
has a single logic input, two active high enabling
inputs, and two active low enabling inputs. The circuit symbol for the desired gate is shown in Figure
P25.21.
25.22
Modify the tri-state gate designed in Problem 25.21
to perform the logic function
+ C)
F(cnablrd)
=A +B
when enabled.
25.23
Design a tri-state NAND gate similar to that in Figure 25.lOa that has the enabling NMOS and PMOS
transistors in the middle of the stack. Sketch the
PENl
PEN2
IN~
FIGURE P25.16
• NEN2
I
NENl
FIGURE P25.21
TINV
436
Chapter 25/CMOS Tri-State Gates
PEN
!
A
C
TriF
B
D
NEN
FIGURE P25.27
circuit. (Hint: the tri-state inverter of Figure 25.Sa
has its enabling MOSFETs in the middle of the
stack.)
FIGURE P25.26
25.24
Design a tri-state AND gate with three logic inputs.
Sketch the circuit.
25.25
Expand the circuit of Figure 25.18 to be a 4: 1 multiplexor with two controlling inputs using four
CMOS transmission gates. Sketch this circuit including the logic necessary for the decoding.
25.26
Analyze the CMOS circuit of Figure P25.26. What
function does it perform 7
25.27
Design a CMOS circuit that performs the tri-state
logic symbolized in Figure P25.27.
CMOS SCHMITT
TRIGGER GATE
In the previous chapters, the single-input CMOS inverter was introduced and analyzed. The outputhigh-to-low transition demonstrated to take place at
an input dependent upon the ratio of the NMOS and
PMOS device transconductance parameters. The input voltage for which the output changes state was
the same for both the output high-to-low transition
and the output low-to-high transition. The multiinput logic gates then presented were shown to possess similar characteristics. In this chapter, a type of
CMOS digital circuit will be presented where the
output high-to-low and low-to-high transitions occur at different input voltages. This phenomenon is
known as hysteresis and circuits exhibiting hysteresis
are referred to as Schmitt triggers. Schmitt trigger circuits exhibiting output hysteresis are easily implemented in CMOS using source-follower positive
feedback MOSFETs. As will be seen, these circuits
are useful for speeding up slow signals and cleaning
up noisy signals.
This chapter begins with a brief description of
hysteresis and the "hysteresis loop." The basic sixtransistor MOSFET Schmitt trigger is then introduced and analyzed. The design procedure of the
CMOS Schmitt trigger is easily deduced from the
analysis. Two buffering augmentations are also discussed along with general theory for embodying
Schmitt hysteresis in multi-input logic gates.
26.1
HYSTERESIS
In this chapter, a type of logic circuit is described that
has a different voltage transfer characteristic for the
output high-to-low and low-to-high transitions. Unlike
the CMOS logic circuits described previously, the
output high-to-low and low-to-high transitions occur at different input voltages. This phenomenon is
known as hysteresis and the voltage transfer characteristic (VTC) exhibits a "hysteresis loop."
Trip Voltages
Figure 26.la shows a pair of input and inverting output waveforms that demonstrate hysteresis. Figure
26.16 displays the vrc for such an inverter. Examining these waveforms, it is seen that the output experiences a high-to-low transition only when a rising
input voltage initially exceeds
V1N = Vw
Examples are shown at times t 2 and t 8 in Figure 26.la.
Furthermore, the output experiences a low-tohigh transition when a falling input initially drops
below
such as at time t 5 .
The voltages V10 and V1LJ are referred to as trip
voltages and m order for hysteresis to occur, the
condition
is required.
Good for Cleaning Up Noisy Signals
In Figure 26. la, note that at times ti, t1,, and t 7, the
input rises above V 1LJ but not above VID and the output does not change state. Likewise, at times t3 and
t4 , the input falls below Vm but not below V1LJ and
the output does not change. Therefore, observing
that V1:--.i is extremely noisy, whereas V0 UT is not, observe that a circuit exhibiting hysteresis is excellent
for cleaning up noisy signals. Even the spikes that
occur at times t1 , t6 , and t7 are not sufficient to change
the output.
Voltage Transfer Characteristic
of Inverter with Hysteresis
Figure 26.16 displays the voltage transfer characteristic for a digital logic inverter circuit exhibiting hys-
437
438
Chapter 26/CMOS Schmitt Trigger Gates
-
Ym(V)
input rises above Vm
''
''
'
- --i-----input high-to-low ttip point------'
':
'
:
!
,,,___~----+-___,\.......- J - +_ _ _
~--+---------+-'- - - f - - - - - - - - l - '_ _
t,
'
t,
t,
¼
t,
I
'
'
t,,
''
''
input drops below Vru
► t
t,
(a)
Your CV)
t,
t,,
Output low-to-high transition
You-+--...,..-----,.-.._
Output high-to-low transition
t
t
t
(b)
FIGURE 26.1 (a) Input and inverting output voltage
waveforms for a circuit exhibiting hysteresis, (b) Voltage
transfer characteristic of a CMOS inverter exhibiting
hysteresis; in both (a) and (b) the output high-to-low
and low-to-high transitions occur at a different input
voltage
26.2
CMOS Schmitt Inverter
439
VIN(V)
5
4
3
2
1
t,
t,
t,
Vour(V)
5- ,___
:
4-~
3-~
21->-~---------4-----------+----+--__..t
t,
FIGURE 26.2
Input and Inverting Output Waveforms Exhibiting Hysteresis for Example 26.1
teresis. This VTC indicates a high-to-low output
transition at an input voltage (Vm) higher than that
at which the output low-to-high transition (V1u) occurs. Note the familiar hysteresis "loop."
Schmitt Triggers
At times t3 and t6 , the output is seen to undergo an
output low-to-high transition when the input falls
below
Vru =
1V
Note that the output voltage does not exhibit spikes.
Circuits that exhibit hysteresis are referred to as
Schmitt Triggers. There are Schmitt trigger inverters, noninverters, NANDS, NORs, and AOis.
26.2
Hysteresis
Figure 26.2 shows the input and resulting output
voltage time waveforms of a CMOS circuit that exhibits hysteresis. What are the output high-to-low
and low-to-high trip voltages for this circuit?
Example 26.1
Solution Examining the waveforms of Figure 26.2,
at times t1 and t 5 the output is observed to undergo
a high-to-low transition when the input rises initially
above
Vw = 4 V
CMOS SCHMITT INVERTER
Circuit
Figure 26.3a displays a CMOS inverter circuit referred to as a Schmitt inverter. Two N-channel
MOSFETs (N 1 and N 0 ) and two P-channel MOSFETs (P 1 and P 0 ) are connected with their drain-tosource channels in series between the supply voltage
V00 and ground. The gates of these four transistors
are all connected and serve as the input of this logic
gate. The output is taken from the middle of the
stack.
440
Chapter 26/CMOS Schmitt Trigger Gates
t
I
.J20µm p
-Zµm 1
60µ.m
-1
Pp 2µ.m
L_
20µ.m
2µ.m
:LJ --1.
0
0
IN~jyo--oUT
Yoo
>------s~riJ
Np
24µ.m
2µm
(a)
(b)
Your (Y)
Output high-to-low transition
t
t
_L-
Output low-to-high transition
t --- !
(c)
FIGURE 26.3 CMOS Schmitt Inverter: (a) Circuit,
(b) Circuit symbol, (c) Voltage transfer characteristic
Feedback Devices
A third NMOS device Nr- feeds the output voltage
back to the node common to N 1 and N 0 by connecting its gate to the output node and its source to
the N 1-N 0 common mode. Note that the drain of N 1
exhibiting hysteresis: output high-to-low transition
occurs at V11;; output low-to-high transition occurs at V1u
is connected to V1m. The PMOS device Pr- serves as
a feedback device between the output and the node
common to the stacked PMOS transistors. Its gate is
also connected to the output with its source connected to the P 1-P 0 common node and its drain connected to ground.
26.3
Figure 26.3b displays the circuit symbol for a
Schmitt inverter. This is the circuit symbol for an inverter with a representation of the output voltage
hysteresis characteristic indicated on the symbol.
Hysteresis of Schmitt Inverter
Figure 26.3c displays the VTC for the CMOS Schmitt
inverter of Figure 26.3a. The output high-to-low
transition occurs at an input voltage of VID and the
low-to-high transition occurs at an input voltage V,u
where Vm > VIu, thus indicating hysteresis. The hysteresis in this circuit is the result of the output feedback to the intermediate points of stacked NMOS
and PMOS transistors. Gates with such an output
hysteresis have a high noise immunity and are useful
for noisy inputs, non rail-to-rail inputs (TTLto-CMOS translators), and slow inputs, as already
observed.
Operation of the CMOS Schmitt inverter and
analysis of the voltage transfer characteristic are explained in the following section.
transistor PF is Vsc.PF = 0 and P" is cutoff for the
output high steady state.
Output HighmtOmLow Transition
Considering Figure 26.3a, when V1N rises above VTN,
N 1 turns on. With the gate of NF at V0 H = VDo and
the drain of NF connected directly to V0 0 , Vco.NF =
0. Since the source of NF is connected to the drain
of N 1, when N 1 turns on, NF enters the saturation
mode of operation. With NI active, NF in the saturation mode of operation, the gate of N 1 connected
to V1N and V1N low, N 1 and NF operate in a manner
similar to the saturation enhancement-only loaded
NMOS inverter. We will assume N 1 is operating in
the saturation mode of operation (which can be verified after this analysis) for V1N slightly larger than
VTN. Equating the drain currents of N 1 and NF gives
26.3 OPERATION AND VOLTAGE
TRANSFER CHARACTERISTIC OF
THE CMOS SCHMITT INVERTER
Output High Voltage = V0 8
Considering Figure 26.3a, with VIN at ground, the
gate-to-source voltage of NI is less than VTN and N 1
is cutoff. With NI cutoff no output pull-down path
to ground is present. The source-to-gate voltage of
PI, however, is sufficient to bring PI into linear operation with VIN at ground. A highly conductive path
is therefore present between V00 and the source of
P0 . Since the source of P O is at a virtual V0 0 , the
source-to-gate voltage of P O is also sufficient to bring
P0 into linear operation. Hence, an output pull-up
path to V 00 is present through P 0 and PI. The PMOS
drain current of P O is equal to the NMOS drain current of N 0 . Since N, is cutoff, Ioro = I0 p 1 = IoNo =
IDNI = 0. With zero drain currents for P 1 and P 0 ,
VDs,PI and Vos,ro are also zero, since these transistors
are in the linear region of operation. Hence, the output high voltage for this gate is
=
=
ILJ.NI(SAT)
Io,NF(SAT)
or
kNJ
Vo11
441
Operation and Voltage Transfer Characteristic of the CMOS Schmitt Inverter
2
(V
IN
- V )2 TN
kNF (V
2
GS,NF -
VTN
)2
VIN was substituted. Solving for
where Vcs.NI
Vcs.NF gives
Vcs,NF
-
=
IE
(VIN - VTN) +
VTN
From this, an expression for Vos,NI as a function of
VIN can be obtained:
Since VoUT = VoH = V00 was used, this expression
for Vos.Ni is valid only when N 0 is cutoff. This is
acceptable since this expression is intended to be
used to determine the input voltage at which N 0
turns on. Since the source of N 0 is connected to
the drain of N 1, N 0 turns on when V1N reaches
Vos.NI+ VTN:
Voo
Note that with VouT = VDo and Vs.PF= VD,rl = Voo
the source-to-gate voltage of the PMOS feedback
Solving for V1N gives the expression for the input
voltage at which N 0 turns on as follows:
442
Chapter 26/CMOS Schmitt Trigger Gates
kNI
-VTN
--1-+~}§--Fk,w·
ViN =
The input voltage Vm at which N 0 turns on and the
output begins to fall is referred to as the output highto-low trip voltage. With N 0 active, an output pulldown path to ground is present through the
channels of N 0 and Nr. As V1N is increased further,
N 0 becomes more conductive and the output drops
further.
Output Low Voltage
the PMOS device Pr turns on. With the gate of PF at
Vrn. = 0 and the drain of PF connected directly to
ground, VDC.l'F = 0. With the source of PF connected
to the drain of Pr when P 1 turns on, Pr enters the
saturation ITtode of operation. Assuming that P 1 is
operating in the saturation mode of operation (which
should be verified after this analysis) for VrN slightly
lower than VDD + Vrl', an expression for the turn on
voltage of P 0 can be obtained. Equating drain currents of Pr and Pr, gives
ln,r1 (SAT)
= ln.N(SAT)
or
= VoL
Considering Figure 26.3a, with V1N at the upper Vrm
rail voltage, the source-to-gate voltage of Pr is less
than VT!' and P 1 is cutoff. With P 1 cutoff no output
pull-up path to Vrm is present. The gate-to-source
voltage of Nr, however, is sufficient to turn on Nr. A
highly conductive path is therefore present from
ground to the source of N 0 . Since the source of N 0
is at a virtual ground, the gate-to-source voltage of
N 0 is sufficient to also bring N 0 into active operation. Hence, an output pull-down path to ground is
present through the channels of N 0 and Nr. Since P 1
is cutoff and the drain currents of all MOSFETs in
the stack are equal, IDNr = Io:--10 = IDl'o = lrw1 = 0.
Since Nr and N 0 both have zero drain currents and
these transistors are operating in the linear region,
their drain-to-source voltages are also 0. The output
low voltage for the CMOS Schmitt inverter is
therefore
With VouT = 0 and Vs,NF = VD,Nr = 0, the gate-tosource voltage of the feedback NMOS device NF is
Vcs.NF = 0 and NF is cutoff for the output low steady
state.
Substituting VSC,l'r = VDI)
-
v,N
gives
Solving for Vsc.r'F yields
Vsc;,pr =
i
WoD -
ViN +
Vyp) - VTr
An expression for the drain voltage of P 1 relative to
ground (VD,l'i) as a function of V,N can be derived
from this realizing from the circuit that
V DJ'/ = Vour + Vsc.l'r = 0 + Vsc,l'r
and by substitution
v/),l'I
=
1€
(VDD
-
ViN +
Vn,) - VT/'
Since VocT = VoL = 0 was used, this expression for
VsD.l'I is valid only when P 0 is cutoff. This is acceptable since this expression is intended to be used to
determine the input voltage at which P 0 just turns
on. Since the source of P 0 is connected to the drain
of Pr, the input voltage at which P O turns on is
Output Low-to-High Transition
The output low-to-high transition is similar to the
output high-to-low transition considering the PMOS
transistors. For the output low-to-high transition the
input voltage is swept from VoH = Vm; down to
Solving for Vr;--..i gives an expression for the input voltage at which P 0 enters active operation as follows:
VOL =0.
Considering Figure 26.3a, with V1N = Vrnr
V DD, the source-to-gate voltage of Pr is O and P 1 is
cutoff. IfV 1N drops belowVDD + VT!' (=Vrm - IVTI'!),
Vm
~
t
(Vi)/)+ Vyp)
1
+
Jf,f;
Viu
26.3
Operation and Voltage Transfer Characteristic of the CMOS Schmitt Inverter
When the input voltage is decreased from a high
value, the input voltage Vn_; at which P 0 turns on and
the output begins to rise is referred to as the output
low-to-high trip voltage. With P 0 active an output
pull-up path to V 00 exists through the channels of
P 0 and P 1. As V 1N further decreases, P 0 becomes
more conductive and the output rises eventually to
Vrn-1 = Voo·
Example 26.2 CMOS Schmitt Inverter
Critical Voltages
For the CMOS Schmitt inverter of Figure 26.3a, find
the output high and low voltages and the high-tolow and low-to-high trip voltages for V 00 = 5 V. Use
k~ = 40 µ,AN 2 and VTN = 1 V for all NMOS devices
and k{, = 16 µ,AN 2 and VTP = -1 V for all PMOS
devices. Use WNifLN 1 = WN 0 /LNo = 8 µ,m/2 µ,m,
WNF/LNF = 24 µ,m/2 µ,m, WpifLp 1 = Wp 0 /Lp 0 = 20
µ,m/2 µ,m, and Wpp/LPF = 60 µ,m/2 µ,m.
Solution (MOSFET Device Transconductances)
The device transconductance parameters for the
MOSFETs of this CMOS Schmitt inverter are
kN1 = kNo
i
=
,
WNF
kNF
=
kNF LNF
kp1
=
kpo
kPF
=
,
kpF
=
WNI
kN1 -
=
LNI
A
(24 µ,)
= (40 µ,) (2 µ,) = 480 µ, v 2
, Wp/
kp1 -
=
Lp1
WPF
Ll'F
(8 µ,)
A
(40 µ,) -(- ) = 160 µ,--:;
2 µ,
v-
=
(20 µ,)
A
(16 µ,) - - = 160 µ,--:;
(2 µ,)
V-
(60 µ,)
(16 µ,) ( µ,)
2
480 µ,
=
A
v2
Solution (Output High and Low Voltages) As
with other CMOS logic circuits, the output range of
the CMOS Schmitt inverter of Figure 26.3a operates
rail-to-rail and the output high and low voltages are
VoH
=
Voo
=
5 V
VoL = ground = 0
Solution (Trip Voltages) The high-to-low and
low-to-high trip voltages are found by substituting
directly into the expression for Vm and V1u derived
in this section:
+
(5)
1
+
(160 µ,) (1)
(43 0 µ,)
(160 µ,)
(480 µ,)
= 3.54 V
443
and
Viu
(160 µ,) [(5) + (-1)]
(480 µ,)
= _,__ __..:..._-'---:===-(160 µ,)
1+
(480 µ,)
1.46 V
Thus, the high-to-low trip voltage is approximately
2 V higher than the low-to-high trip voltage. Note
that the trip voltages are symmetric about the midpoint voltage V 00 /2 = 5/2 = 2.5 V. This will be examined in the following sub-section on designing
CMOS Schmitt inverters.
Example 26.3 CMOS Schmitt Inverter
SPICE Simulation
Perform a transient SPICE simulation on the CMOS
Schmitt inverter of the previous example to determine the high-to-low and low-to-high trip voltages.
Use an input PULSE stimulus with a period of 40 ns
and rise and fall times of 10 ns, so that the trip voltages are easily determined.
Solution The CMOS Schmitt inverter of Example
26.2 and Figure 26.3a with a capacitive load and appropriate SPICE labelings is shown in Figure 26.4.
The input SPICE CIRcuit file for this circuit is as
follows:
CMOS Schmitt Inverter
VIN 5 D PULSE(OV SV D 1DNS 10NS
+ 20NS 60NS)
VDD 7 D DC SV
-MODEL NMOSFET NMOS(VT0=1
+ KP=40U GAMMA= □ -37 PHI= □ -6
+ CBD=3-1E-15 CBS=3.1E-15)
-MODEL PMOSFET PMOS<VT0=-1
+ KP=16U GAMMA= □ -4 PHI=0-6
+ CBD=3-1E-1S CBS=3-1E-1S)
MPI 3 S 7 7 PMOSFET W=20U L=2U
MP◊ 9 S 3 7 PMOSFET W=20U L=2U
MPF 3 9 D 7 PMOSFET W=b □ U L=2U
MNF 7 9 2 D NMOSFET W=24U L=2U
MN◊ 9 S 2 D NMOSFET W=8U L=2U
MNI 2 SD D NMOSFET W=8U L=2U
CLOAD 9 D □ -SPF
-TRAN 1NS SONS
-PRINT TRANS V(VIN) V(9)
-END
444
Chapter 26/CMOS Schmitt Trigger Gates
1_1!
s
20UMMPI
2UM
13·
I
I
1
•
sg8:
MPF
f------~3 7 !
L -~
s
I i~l2g8~ MPO
-;;-:
_j_l_'------,9
~
I
sj H
~
1-
!SUMMNO
-2uM
Your
12f--.------;~- -.~ [7
~
s I o SUM
:~ o 12uMMNI
I-1
--0~
9
MNF
2
~8:
Yoo
............
f1
CLO AD
0.1 pf
-:;:-
I
-=1FIGURE 26.4
CMOS Schmitt Inverter with Appropriate SPICE Labelings
The input stimulus and output response from this
simulation are shown in Figure 26.5. Examining this
plot, the high-to-low trip voltage occurs at an input
voltage of V10 = 3.6 V and the low-to-high trip voltage at Vil; = 1.4 V. These are in close agreement with
the values determined using the analytical analysis
of the previous example.
nel length possible with a given fabrication process).
In a similar manner, all N-channcl MOSFETs in a
CMOS Schmitt inverter have the same channel
length or
Likewise, all P-channel MOSFETs in a CMOS
Schmitt inverter should have the same channel
length or
DESIGN OF CMOS
SCHMITT INVERTER
26.4
The W/L ratios for each device of the CMOS Schmitt
inverter take into consideration the desired drive
strengths and switching speeds.
Channel Lengths
In the previous chapters on CMOS combinational
logic and tri-state logic gates, all N-channel MOSFETs in a particular gate were designed with the
same channel length (generally the minimum chan-
Channel Widths of MOSFETs
in the Stack
In the design of the CMOS combinational logic and
tristate logic gates of the previous chapters, all
stacked NMOS devices were designed with the same
channel width. The NMOS devices in the stack of a
CMOS Schmitt inverter (N 1 and N0 ) also have the
same channel width as follows
26.4
Design of CMOS Schmitt Inverter
445
case with two-input CMOS NOR gates and tri-state
inverters).
Channel Dimensions of
Feedback MOSFETs
t(ns)
10
20
30
40
50
10
20
30
40
50
Ymrr(V)
A
5
4 .l
32,
I
1-
The high-to-low and low-to-high trip voltages are
dependent upon the W/L ratios of the NMOS and
PMOS feedback devices, respectively. The larger the
W/L ratios, the greater the difference between the
trip voltages and the midpoint voltage. The previous
examples had feedback W/L ratios three times that
of the stacked devices and had a hysteresis of about
2 V, or 40% of the supply voltage. Increasing the W/L
ratios of the feedback devices would increase the
hysteresis further, and decreasing the feedback W/L
ratios would bring the output transitions closer
together.
An expression for the feedback NMOS WNr/LNF
ratio in terms of the high-to-low trip voltage V1D can
be found by first solving for kNF in the expression for
Vm, yielding
t(ns)
0
0
FIGURE 26.5 CMOS Schmitt Inverter Transient
Response from SPICE Simulation of Example 26.2
Cancelling k~ = /.LNCcSx from both sides (since kN is
the same for all NMOS devices in a single process)
gives
WNF =
LNF
Likewise, all PMOS devices in a CMOS Schmitt inverter stack (P 1 and Pu) have the same channel width
as follows:
The drive strength of a CMOS Schmitt inverter
is dependent on the W/L ratios of the devices in the
MOSFET stack. Since the output pull-down path to
ground is through two NMOS transistors, the widths
of the stacked N-channel MOSFETs should all be
twice that of the constituent NMOS devices in an
inverter with the desired drive strength (as was the
case with two-input CMOS NAND gates and tristate
inverters). Similarly, the output pull-up path to VDD
is through two P-channel MOSFETs. Thus, the channel width of the stacked PMOS devices should be
twice that of the P-channel MOSFET in a CMOS
inverter with the desired drive strength (as was the
(Vm - Vm)
2
Voo - Vio
WN1
LN1
This is a design expression used to find the necessary
W NF/LJ\:F in relation to the W N/LN ratio of the stacked
input NMOS devices that provides the desired Vm.
An expression for the Wn/Ll'F ratio for the
PMOS feedback device is similarly obtained by solving for kl'F in the expression for V1u derived earlier in
this section, yielding
2
_ (Voo + VTP - Viu) k
k
i'F -
V1u
PI
Cancelling k(, from both sides gives
Wp1·
Lff
= (Vim + Vn, - Viu)
Vm
2
Wp1
L0
This is a design expression used to obtain the required W l'I·/Lpf in relation to the Wp/Lp ratio of the
P-channel MOSFETs in the stack that provides the
desired Vn_;-
446
Chapter 26/CMOS Schmitt Trigger Gates
Substituting values into the expression for WPF/LPF
derived in this sub-section, maintaining the channel
length at 2 ,urn, gives
Design of CMOS
Schmitt Inverter
Example 26.4
Design a CMOS Schmitt inverter that has the drive
strength (that is the dynamic response time) of the
CMOS inverter of Example 23.3 (see Figure 23.5) and
trip voltages of Ym = 4 Y and Y1u = 1 Y. Use
Y00 = 5 Y and a channel length of 2 ,um for all
transistors. Assume kN = 40 µ,AN 2 , k{, = 16 µ,AN 2 ,
YTN = 1 Y, and Vrp = -1 Y.
2
WI',
L1,1
=
[(5) + (-1) - (1)] Wp1 = 9 (20 µ,)
(1)
Lp1
2 µ,
180 µ,111
26.5 CMOS SCHMITT INVERTER
WITH BUFFERED OUTPUT
Solution (Stacked MOSFETs) The W/L ratios of
the N- and P-channel MOSFETs should be twice
that of N 0 and P O in Figure 23.5, respectively, and
the channel lengths remain at 2 ,um. Hence,
The input terminal of the CMOS Schmitt inverter of
Figure 26.3a is connected to the gates of four MOSFETs, all of which have twice the channel area of
those in a CMOS inverter of equivalent current drive
strength. Hence, the input capacitance of a CMOS
Schmitt inverter is approximately four times the input capacitance of a CMOS inverter of equivalent
drive strength. Increasing the size of the MOSFETs
in a CMOS Schmitt inverter in order to increase the
drive strength could increase the input capacitance
to an unmanageable amount. Therefore, if a CMOS
Schmitt inverter with a large current drive is desired,
it is best to use a CMOS Schmitt inverter with a two
stage inverting buffer where each inverter has increasing drive strength. (Clwpter 27 presents an in
depth discussion of multi-stage inverter drivers.) Figure
26.6 shows such a buffered CMOS Schmitt inverter.
8 ,um
2 ,um
and
20 ,um
2 ,um
Solution (Feedback Devices) Substituting values into the expression for W:--:r:ILNF derived in this
sub-section, maintaining the channel length at 2 ,um,
gives
Ysour
Your
24µm
Np 2µm
FIGURE 26.6
CMOS Schmitt Inverter with Buffered Output (to increase output current drive)
26.6
CMOS Schmitt Inverter with Buffered Output and Feedback
The first inversion stage of the buffer has W/L ratios
three times that of series NMOS and PMOS pairs.
That is
WNBI
=
26.6 CMOS SCHMITT INVERTER
WITH BUFFERED OUTPUT
AND FEEDBACK
WNO
3
LN/ll
44 7
LNo
+
LNJ
When the input to a CMOS Schmitt inverter with
buffered output is extremely noisy, the transient response can be improved by the addition of a feedback inverter between the midpoint of the two stage
output buffer and the output of the Schmitt inverter.
Figure 26.7 shows such a circuit configuration. The
feedback inverter provides further noise immunity by
applying positive feedback to the input of the first
and
Wpo
wl'BI
-- = 3---Lpl)/
Lpo + Lp1
Furthermore, the second stage of the buffer pair has
W/L ratios three times those of the first stage. This
is due to the so-called rule of three described in the
next chapter.
Your
(a)
lo-,!
?
----
[20µm p
7-,.. ,pl '"~
[
20µmp
2µm o
N..
ri
---,
i
~rl--'
YsmJT
Your
I
sµm N
,
Y·.•DD
~
24µm
N p 2µm
(b)
FIGURE 26.7
CMOS Schmitt Inverter with Buffered Output and Feedback: (a) Logic schematic, (b) Circuit schematic
448
Chapter 26/CMOS Schmitt Trigger Gates
stage of the output buffer. This has the disadvantage
of increasing the propagation delay across the two
stages of the output buffer and slightly increasing the
output rise and fall times.
To avoid contention between the outputs of the
Schmitt inverter and the feedback inverter upon
switching of the Schmitt inverter output, the drive
strength current capability of the feedback inverter
should be less than that of the Schmitt inverter itself.
To understand this, consider that the propagation
delay of the Schmitt inverter output through the first
stage of the output buffer will be finite, no matter
how small. Furthermore, the propagation delay
through the feedback inverter will also be non-zero.
When the input of the Schmitt inverter crosses the
trip point, the Schmitt inverter output will begin to
change. The output of the feedback inverter will not
begin to change until the first stage of the output
buffer changes state. This is a potential cause of contention between the outputs of the Schmitt inverter
and the feedback inverter. If the drive strength of the
feedback inverter is less than that of the Schmitt inverter, than the contention will be avoided, since the
FIGURE 26.8
Schmitt inverter will out-drive the feedback inverter.
The Schmitt inverter configuration of Figure 26.7
shows the W /L ratios of the feedback inverter with
increased channel lengths to decrease its output current drive. T11e weak feedback stage is often referred
to as a cheater latch.
The following example compares the switching
characteristics of the CMOS Schmitt inverter with
buffered output with and without a positive feedback
stage.
Example 26.5 Comparison of CMOS
Buffered Output Schmitt Inverters with and
without Feedback Inverter
Perform SPICE simulations on the CMOS Schmitt
inverter circuits of Figure 26.6 and 26.5 with load capacitances of 0.5 pF and compare the overall output
switching speeds.
Solution (SPICE Simulation with Output Buffer
and No Feedback Inverter) Figure 26.8 shows
the CMOS Schmitt inverter circuit of Figure 26.6
CMOS Schmitt Inverter with Buffered Output and Appropriate SPICE Labclings
:?.h.h
CMOS Schmitt Inverter with Buffered Output and Feedback
with appropriate SPICE labelings. The SPICE input
CIRcuit file for this circuit is as follows:
*CMOS Schmitt Inverter with
*Buffered Output
VIN 5 0 PULSE<OV 5V D 1DNS 1DNS
+ 2DNS b □ NS)
VDD 7 D DC 5V
-MODEL NM◊SFET NMOS(VT◊=1
+ KP=40U GAMMA=0.37 PHI= □ .6
+ CBD=3-1E-15 CBS=3-1E-15)
-MODEL PM◊SFET PM◊S(VT◊=-1
+ KP=16U GAMMA=0-4 PHI= □ .6
+ CBD=3-1E-15 CBS=3-1E-15)
*Schmitt inverter
MPI 3 5 7 7 PM◊SFET W=30U L=2U
MP◊ 9 5 3 7 PMOSFET W=30U L=2U
MPF 3 9 D 7 PMOSFET W=90U L=2U
MNF 7 9 2 D NMOSFET W=36U L=2U
MN◊ 9 5 2 D NMOSFET W=12U L=2U
449
MNI 2 5 DD NMOSFET W=12U L=2U
*inverting buffer
MPBI 20 9 7 7 PM◊SFET W=45U
+ L=2U
MNBI 20 9 DD NM◊SFET W=18U
+ L=2U
*output buffer
MPB◊ 30 20 7 7 PM◊SFET W=135U
+ L=2U
MNBO 30 20 0 D NMOSFET W=54U
+ L=2U
CL◊AD 30 D □ -5PF
-TRAN 1NS 5DNS
-PLOT TRAN V<VIN) V(9)
-END
The plot obtained from this simulation is shown in
Figure 26.9. The overall output fall and rise times are
observed to be approximately tr = 160 ps and
tr = 180 ps.
VDD
MP~t: I
10UM Fti=I
4UM
lroo
IO
'
J_
Your
VDD
17
L-30 • MNB2
LJMPB1
I
I
~
2
:-__?J 30UM
0
36UM
2UM
'.I
3~
2UM
MNF ~~~
'~-- 511CJ2UIIII
0 BUM MNI
r
':lo
Ysour
o,
!
I o MNB1
1::-::;=i
12UM
2u1111
1
FIGURE 26.9
01
CMOS Schmitt Inverter with Buffered Output and Feedback with Appropriate SPICE Labelings
CLO.AD
0.5pF
450
Chapter 26/CMOS Schmitt Trigger Gates
VIN(V)
VIN(V)
5•
5f-
4
4-.-
3
3 :
2
1
1 _J_
0---t-----+--+----+-------1---+-----. t(ns)
0-',~--+----+--+---~------ t(ns)
10
0
20
30
40
0
50
10
20
30
40
50
YsourCV)
VsmrrCV)
5+
4
3
2
~r--------+-----+-1 _;_
1
--+---.----,--"-+-
0
0
10
20
30
40
-+-►
t(ns)
50
0~
0
10
20
30
40
50
t(ns)
vsourCV)
YsourCV)
5f-
5
4
:+
3
2-,-
2
1 -
1
o---J~'--+---:--:i----...---i--► t(ns)
0---+---+--+----+-------1---+-----. t(ns)
0
10
20
30
40
0
50
5
5
4
4
30
1
1
40
50
•
3
3
2
2-,-
1
1
0--+-------'+--+---+--""-+----+---►
20
30
40
1
50
Solution (SPICE Simulation with Output Buffer
and Feedback Inverter) Figure 26.10 shows the
CMOS Schmitt inverter circuit of Figure 26.7 with
appropriate SPICE labelings. The SPICE input CIRcuit file for this circuit is as follows:
*CMOS Schmitt Inverter with
~
0-+----'-+-------.-J--+------+---.t(ns)
t(ns)
FIGURE 26.10 Transient Solution from SPICE
Simulation of CMOS Schmitt Inverter with Buffered
Output for Figures 26.6 and 26.8
*feedback
20
Vour(V)
VourCV)
0
10
0
10
20
30
40
50
FIGURE 26.11 Transient Solution from SPICE
Simulation of CMOS Schmitt Inverter with Buffered
Output and Feedback for Figures 26.7 and 26.9
VIN 5 D PULSE(OV 5V D 1DNS 1DNS
2DNS b □ NS)
VDD 7 D DC SV
-MODEL NMOSFET NMOS(VT0=1
+ KP=40U GAMMA=D-37 PHI= □ .6
+ CBD=3-1E-15 CBS=3-1E-15)
-MODEL PMOSFET PMOS(VT0=-1
+ KP=16U GAMMA= □ .4 PHI=0-6
+
Chapter 26
NAND=
Problems
A~DB~
(a)
ll.
451
NANDSCHMITf
(b)
FIGURE 26.12 Two-input CMOS Schmitt NAND Gate: (a) Circuit is composed of inverting Schmitt inputs feeding an
OR configuration, (b) Circuit symbol
+
CBD=3,1E-15 CBS=3-1E-15)
*
Schmitt inverter
MPI 3
MP◊ 9
MPF 3
MNF 7
MN◊ 9
MNI 2
*
5 7 7
5 3 7
9 0 7
9 2 0
5 2 0
5 0 0
PM0SFET
PM0SFET
PM0SFET
NM0SFET
NM0SFET
NM0SFET
W=20U L=2U
W=20U L=2U
W=b0U L=2U
W=24U L=2U
W=8U L=2U
W=8U L=2U
inverting buffer
MPBI 20 9 7 7 PM0SFET W=30U
L=2U
MNBI 20 9 0 0 NM0SFET W=12U
+ L=2U
+
* feedback inverter buffer
MPBF 9 20 7 7 PM0SFET W=10U
L=4U
MNBF 9 20 0 0 NM0SFET W=4U L=4U
* output buffer
MPB0 30 20 7 7 PM0SFET W=90U
+ L=2U
+
MNB◊
30 20 0 0 NM0SFET W=36U
Schmitt inverter with feedback are approximately tr
= 260 ps and tr = 270 ps, respectively. Thus, the
output logic level transitions are increased by only
about 60%.
26. 7 CMOS SCHMITT NAND GATES
Standard CMOS logic chip sets include the 54C132/
74C132 Schmitt NAND gate. This is a gate that realizes the logic NAND function with hysteresis between the inputs and the output. Figure 26.12a
shows the circuit construction embodying this function and Figure 26.12b displays the circuit symbol for
this Schmitt NAND gate. Each input is fed directly
to a separate Schmitt inverter. The Schmitt inverter
outputs are then fed to the logical equivalent of an
OR gate. The output of this gate therefore realizes
the function
L=2U
CL0AD 30 D 0,5PF
-TRAN 1NS 50NS
,PRINT TRAN V(VIN) V(9)
-END
Applying DeMorgan's NOR theorem
The plot obtained from this simulation is shown in
Figure 26.11. The overall fall and rise times for the
Thus, the NAND function is indeed realized with the
hysteresis provided by the input Schmitt inverters.
+
A
+ B = (A+ B)
(A + B) =
(A B)
= AB
CHAPTER26PROBLEMS
26.1
Determine Vrn 1 and Vrn. for the CMOS Schmitt
inverter of Figure P26.1 and sketch the voltage
transfer characteristic.
26.2
Derive the expressions for the high-to-low and
low-to-high trip voltages of Figure P26.1
26.3
Using the expressions derived in Problem 26.2, calculate the high-to-low and low-to-high trip voltages of Figure P26.1 for V0 u = 5 V. Use kN = 40
µA/V 2 and VTN = 1 V for all NMOS devices and
k{, = 16 µ,A/V 2 and V1 p = -1 V for all PMOS de-
452
Chapter 2G/CMOS Schmitt Trigger Gates
FIGURE P26.1
vices. Use WNifLN1 = WNo/LNu = 16 µm/2 µm,
W Nr/LNr = 48 µm/2 µm, WpifLp1 = Wp 0 /Lpu = 40
µrn/2 µm, and Wp 1/Ll'F = 120 µm/2 µm. Sketch
the voltage transfer characteristic.
26.4
Show that as WF/LF----'> 0 for both feedback devices
the hysteresis ----'> 0 and the Schmitt inverter becomes a normal (non-Schmitt) inverter.
26.5
Repeat Problem 2G.3 for a circuit with
26.6
26.7
26.8
Repeat Problem 26.3 using W :,.; 1 /LNr = 720 µm/2
µm and W 1,1/L 1'1' = 180 µm/2 µm.
26.9
Repeat Problem 26.3 using W:--; 1/L:,.; 1 = W:,.: 0 /Lr--:(> =
32 µm/2 µm and WpifL 1,1 = Wp 0 /L 1,0 = 80 µm/2
µm.
26.10
Design a CMOS Schmitt inverter for a drive
strength four times that of the CMOS inverter of
Example 23.3 (see Figure 23.5) and trip voltages of
V1D = 4 V and V 11; = 1 V. Use VDD = 5 V and a
channel length of 2 µm for all MOSFETs. Assume
k( = 40 µAN", k(, = 16 µAIV", VrN = 1 V, and
Vn, = -1 V.
26.11
Repeat Problem 26.10 with V1)]) = 7 V.
26.12
Repeat Problem 26.10 with
26.13
For the circuit of Figure P26.13, determine the output logic function and the equivalent circuit
symbol.
10 V.
26.14
Repeat Problem 26.10 for V1D = 3 V and V1c = 2 V.
26.15
Repeat Problem 26.14 with Vl)IJ = 7 V.
26.16
Repeat Problem 26.14 with Vi>D = 10 V.
= 3 V.
Repeat Problem 26.3 for a circuit with V1m = 10 V.
VDD
Repeat Problem 26.3 using WNF/LNF = 60 µm/2µm
and wl'F/Ll'F = 150 µm/2 µm.
Vt)])=
FIGURE P26.13
CMOS DRIVERS
In section 23.8 the dynamic response of a CMOS
inverter with a capacitive load is presented. Expressions for the high-to-low and low-to-high propagation delays and rise and fall times are derived. All
four transient characteristics are found to be directly
proportional to load capacitances and inversely proportional to device transconductances. In this chapter, capacitive loads driven by cascaded CMOS inverters are described. It is shown that the time
required to charge and discharge a capacitive load is
decreased by using multi-stage CMOS inverter drivers in place of single inverters. Such multi-stage drivers are a necessity for driving capacitive loads above
a few picofarads.
A special driver configuration exhibiting highimpedance Z-states when disabled is also discussed.
This tri-state driver is generally used to drive the relatively large capacitance seen from inside an IC at
the output pins of an integrated circuit package. The
benefit of the tri-state embodiment is in saving
power when the external pins are not being driven.
T
Likewise, the expression for t 1'LH is also directly
proportional to the load capacitance and is inversely proportional to the PMOS device transconductance parameter kl', where
The constant of proportionality B is a function
of the supply voltage V 1m and the PMOS
threshold voltage VT!' and is given specifically
by
In section 23.8, expressions were obtained for
the high-to-low and low-to-high propagation
delay times. These are repeated here as follows:
=
2C1VrN
-,
kNWnn - VTN)-
+
cL
ln(1.sv/)/) kNWoo - VTN)
0.5Vrm
ln(l.SVuo + 2Vn')
O.SVno
(Voo + Vrl')2
Woo+ Vrp)
Note that for the case of a symn,etric inverter
where VTN = -Vn,, the constants of proportionality A and B are equal, that is
= kP (V DD + VTl') 2
CL
-2Vr1'
B=-----+--------
2v1N)
and
tpui
The constant of proportionality A is a function
of the supply voltage V 1)1) and the NMOS
threshold voltage Vrn and is given specifically
by
Tips, Tricks, and Gimmicks
CMOS Inverter Propagation
Delay Times
tPI/L
It should be noted that the expression for
tl'HL is directly proportional to Ci, and inversely
proportional to the NMOS device transconductance parameter kl':, that is
A
l (1.5V00 + 2Vp)
O.SVim
= B (symmetric inverter)
These expressions will be used in the following
section on multi-stage CMOS drivers.
+ kl'(V1)[) + Vn,) n
where C1, is the output load capacitance.
453
454
Chapter 27/CMOS Drivers
T
Tips, Tricks, and Gimmicks
T
Tips, Tricks, and Gimmicks
Exponential Property of Logarithms
Quotient Rule of Derivatives
The logarithm of a constant raised to a power
is governed by the relation
The derivative of the quotient of functions is
also used in the following section and is realized by the relation
ln a1' = b ln a
This relation is needed in the derivation presented in the following section.
3- [u(x)]
dx
27.1 CASCADED CMOS INVERTERS
DRIVING A LOAD CAPACITANCE
In section 23.8, expressions for the high-to-low and
low-to-high propagation delay times are derived
(and are repeated in the Tips, Tricks, and Gimmicks
box preceding this section). These expressions for
tr1-1L and trLH are directly dependent on the load capacitance being driven. Also, the expressions for trHL
and tru-1 are inversely proportional to the NMOS and
PMOS device transconductance parameters kN and
kr, respectively. Thus, if a large output load capacitance is to be driven, the values of kN and kr for
reasonable values of trLH and tl'HL for the N- and
P-channel MOSFETs should also be large. Large values of kN and kp arc obtained by using large W /L
ratios.
For example, the CMOS inverter of Figure 27. la
is shown driving a relatively large (for CMOS digital
integrated circuits) load capacitance of 10 pF. The
channel sizes (Wp/Lr = 1750µ,m/2µ,m and WN/LN =
700µ,m/2µ,m) of the constituent MOSFETs are also
relatively large compared to the CMOS circuits seen
in the last four chapters. While this inverter will be
1it
Tips, Tricks, and Gimmicks
Derivative of Natural Logarithm
The derivative of the natural logarithm function
is also needed in the derivations presented in
the following section and is
d
- (ln x)
dx
v(x)
able to drive the load capacitance with acceptable
propagation delays, the input capacitance
c/N
=
Ccp
+
CcN = (WpLp
+
WNLN)C,
will then be very large. The CMOS gate that has to
drive this large inverter will then have a large load
capacitance to drive, as shown in Figure 27.16. While
the propagation delay across the large CMOS invetter is manageable, the propagation delay of the
small inverter will be much larger, as seen in the following example.
Example 27.1 Relative Propagation Delays
of Cascaded CMOS Inverters
Use the expressions developed in section 23.8 and
specified in the Tips, Tricks, and Gimmicks box preceding this section to determine the propagation delays of each of the inverters in Figure 27.16. Use
V00 = 5 V, VTN = 1 V, VTP = -1 V, kr'.J = 40 µ,A/V 2,
and k& = 16 µ,A/V 2 • A;so, use a gate capacitance per
unit area of c:,, = 690 aF/ µ,m 2 • Note that this is the
value of C~x used in Example 23.3.
Solution Since Wr/Lp = 2.5 X WN/LN for both
inverters and VT!' = -VTN, both inverters are symmetric. Thus, tr1-1L = tpu-, for both inverters. Also, the
constants of proportionality A and B stated in the
Tips, Tricks, and Gimmicks box preceding this section
are equal and thus calculating yields
2(1)
A
= B = -[(5-)---(-1)-]2
1
x
v(x) du(x) _ u(x) dv(x)
=
dx
dx
v 2 (t)
+
ln[l.5(5) - 2(1)]
0.5(5)
1
--[()---(l-)l- = o.322
5
v
27.1
Cascaded CMOS Inverters Driving a Load Capacitance
455
lOµmp
2µm 01
Your
Your
=r
700µm N----:-1 lOpF
O
2µm
700µm N02
2µm
r,
'-'EXT
lOpF
l
Cm,"" 175CINI =3.38 pF
(b)
(a)
FIGURE 27.1
(a) A large CMOS inverter driving a large load capacitance, (b) Large CMOS inverters have large input
Solution (Second Stage Propagation Delay)
The device transconductance parameters of the
(symmetric) second inverter are
The (equivalent) propagation delay across the first
stage is therefore
tp 1
700µ,)
kN = kr = ( - (40µ,) = 14.0 m 2A
2µ,
V
The (equivalent) propagation delays across the second stage are
tl'2 = (0.322)
(lOp)
(14.0m)
=
0.230 ns
which is quite acceptable.
Solution (First Stage Propagation Delay) The
device transconductance parameters of the (sym metric) first inverter are
A
kN = kp = ( 4µ,)
µ, (40µ,) = 80 µ, v
2
2
The load capacitance on the output of the first stage
is the sum of the gate capacitances of the second
stage and thus
(WN2LN2 + WP2Ln)Cbx
690a
= [(700µ,)(2µ,) + (1750µ,)(2µ,)] -
µ, 2
= 3.38 pF
(3.38p)
= (0.322) -(--) = 13.6
80µ,
11S
which is 59 times larger than tp 2 and bordering on a
propagation delay that is too long.
This example displays that driving a large capacitance with a large-sized inverter has the drawback
that this inverter possesses a large input capacitance.
Thus, the propagation delay of a previous stage will
be extremely large. The next example examines the
possibility of using additional stages with transistor
sizes intermediate to those of the previous example.
Example 27.2 Propagation Delay Across
Multiple Cascaded Inverters
Figure 27.2 shows the two stage CMOS inverter
driver of Figure 27.16 with two additional inverter
stages. Note that the two middle inverters are symmetric and have channel sizes intermediate to those
at the beginning and end of the chain. Find the propagation delay across each stage and the total propagation delay time. Compare with the propagation
456
Chapter 27/CMOS Drivers
Yoo
!
i
50µmp
2µm 02
lOµmp
[ ' 2µm o1
r-vir-.1[.
300µm
2µm p 03
_r-.1 [
_j
'-1
!
l750µm p
l
2µm
I
L----0
20µmN
2µm o2
[ -·
120µgiN
2µm o,
04
VP.Xr
L_I [70~tt~
½KT~
N04
lOpF
I
l
Crn,=96.6fF
Crn,=580fF
Cm•= 3.38 pF
intermediate
sized
inverters
inserted
between the series inverters of Figure 27.1
will decrease the total propogation delay
delay calculated in the previous example. Use the
same values for VDD = 5 V, VTN = 1 V, Vw = -1 V,
k~ = 40 µ,A/V 2 , k{, = 16 µ,A/V 2, and C x = 690
aF/ µ,m 2 as in the previous example.
0
Solution (Constants of Proportionality) Since
VDD and the threshold voltages are the same, the
constants of proportionality remain constant at
A= B
1
= 0.322 V
Solution (Second Stage Propagation Delay)
The device transconductance parameters of the
MOSFETs in the second stage are
The load capacitance of the second stage is the sum
of gate capacitances of the third stage and thus
C1.2
Solution (First Stage Propagation Delay) The
device transconductance parameters of the
MOSFETs in the first stage are
kNJ = kp 1
=
(~:)(40µ,)
80 µ, ;
=
2
The load capacitance of the first stage is the sum of
gate capacitances of the second stage, given by
Cu = CcN2
+ CcP2 =
(WN2LN2
+ WP2LP2)Cbx
690a
µ, 2
= [(50µ,)(2µ,) + (20µ,)(2µ,)] -
=
96.6 JF
The propagation delay across the first stage is therefore
tp1
=
(96,6!)
(0,322) -(--) = 0.39
80µ,
115
+
+
=
CcN.1
=
[(120µ,)(2µ,) + (300µ,)(2µ,)]
Ccl'.1 = (WNJLN1
Wp1Lp,)C(x,
690a
w
-7
=
580
'ff
The propagation delay across the second stage is
therefore
(580!)
tp2
= (0.322) (400µ,) = 0.47 ns
Solution (Third Stage Propagation Delay) The
device transconductance parameters of the MOSFETs in the third stage are
kN, =
kp.1
120µ,)
= ( ~ (40µ,) = 2,4
111
vA2
The load capacitance of the third stage is the sum of
gate capacitances of the fourth stage
27.2
Cu
= CcN4
+
Ccp 4 = (WN4LN4
+
Wp4Lp4)C!ix
690a
[(700µ,)(2µ,) + (1750µ,)(2µ,)) - " = 3.38 pf
µ,"
The propagation delay across the third stage is therefore
(3.38p)
(0.322) - - ) = 0.45
(2.4m
tp3 =
kN4
700µ,)
A
= kp4 = ( - (40µ,) = 14 m --;,
2µ,
V"
The load capacitance of the first stage is the sum of
gate capacitances of the second stage
CIA
=
CEXT
=
10 pF
The propagation delay across the fourth stage is
therefore
tp4 =
(10p)
(0.322) -(- ) = 0.23
14111
11S
Solution (Total Propagation Delay) The propagation delay across the CMOS four stage inverter
driver is therefore
tP,TOT/\L
= tp1 + t/'2 + tp3 + fp4
= (0.3911) + (0.4 711) + (0.4511) + (0.2311)
= 1.54
11S
This is almost a 90°/4> reduction in propagation delay
as compared to the 10 pF loaded two stage driver of
the previous example. Hence, the additional stages def-
initely improve the dynamic response of a multi-stage
inverter driver charging a load capacitance.
457
The question to ask now is what arrangement of
multi-stage inverters gives the optimum response?
That is,
1.
How many stages should be used for a given
load capacitance?
2.
What is the relation between the channel sizes
of successive stages?
115
Solution (Fourth Stage Propagation Delay)
The propagation for the final stage was found in the
previous example and is repeated here for convenience. The device transconductances of the MOSFETs in the fourth stage are
CMOS Multi-Stage Inverter Drivers
In the following sub-sections, the answers to these
questions are obtained and the resulting relations are
developed.
Load Capacitance of Each Stage Is
Input Capacitance of Following Stage
To determine the optimum design of a CMOS multistage inverter driver, examine the general )-stage
driver in Figure 27.3. The load capacitance on a given
stage i is the input capacitance of stage i + 1, which
we will continue to estimate as the sum of the gate
capacitances of the MOSFETs in stage i + 1 as follows:
Thus, the propagation delays across each stage i can
be written as
and
t Pl.II
_ B Cu _ B C1NU>
-
lcr;
-
11
kp;
Reduction of Propagation Delay
Expressions for Symmetric
Inverter Stages
To simplify the analysis, consider a symmetric inverter for which A = B and
27.2 CMOS MULTI-STAGE
INVERTER DRIVERS
The previous examples indicated that a 10 pF load
capacitance can be charged through CMOS two- and
four-stage inverter drivers and the four-stage driver
had a distinct improvement in dynamic response.
tPHL -_ tI'Li/ -_ A
CIN(i+I) _
-
kN;
A
CIN(i+1)
kp,-
The device transconductance parameters of each
stage i are
458
Chapter 27/CMOS Drivers
Yoo
Yoo
Yoo
Yoo
y
?
(.)
0
I
L~P.
q
I
q~w~~P
1;1+I)
VIN
O(i+l)
!
V;JO-
.----------0-- -
[ :t-N=.,
1~¥:N•
C.OI
(l+I)
'
-:-
~
-;-
Cu=
FIGURE 27 .3
~
Stage i + 1
~
Stage i
Stage 1
7
Stagej
CIN(i+l)
Load Capacitance of Stage i is the Input Capacitance of the Next (i + 1) Stage
and
and
For a symmetric inverter where the channel lengths
of the NMOS and PMOS device are equal (LN; =
Lp; = L;), the W/L ratios for the N- and P-channel
MOSFETs can be rewritten as
Since k~ = 2.5 X k~, the expression for tPLH can be
rewritten as
and
k
_
2.5WNi
Li
Pi -
Note that the equations describing tl'HL and tPLH are
now identical and the single equation for the propagation delay
k'
l'i
For symmetric inverters, using the relations the
input capacitance of each stage i + 1 can now be
rewritten as
Cu = CrN(i+l)
=
=
[WN(i+1)LN(i+1)
+
Wru+1)Lru+1)]C:,x
3.SWN(i+l)Lic;,x
Substituting the expressions for device transconductances and input capacitance of a symmetric inverter into the propagation delay equations results in
t /'/IL
- A c/N(i+·1) - A 3.5WN(i+1)L(i+l)Cx
-
-
kNi
WNi k'
L
I
N
is used to describe Both the high-to-low and lowto-high propagation delays for the remainder of this
discussion.
Assume Equal Channel Length for
N- and P-Channel Devices of All Stages
If the channel lengths of the NMOS and PMOS devices of all stages are equal (which is not uncom-
27.2
mon), the above expression can be further reduced
as follows:
CMOS Multi-Stage Inverter Drivers
If the external load capacitance CEXT is defined as a
times the input capacitance of the final stage, then
CExT is related to the input capacitance of the first
stage by the expression
C1:xT
Defining a new constant
459
=
aiC1N1
Dividing both sides by C1N 1 gives
A = A 3.5L2C~x
k/_i
1
The propagation delay expression can be stated as
Taking the natural log of both sides yields
·
((EXT)
ln a 1 = In - C1N1
Propagation Delay Across Each Stage
Is Proportional to Relative Size
of Successive Stages
The final expression for the propagation delay across
any given stage i is thus proportional to the ratio of
channel widths of successive stages. Defining a con stant
Utilizing the exponential property of logarithms
gives
(CExT)
1 a =1 n - ;· n
C1N1
and solving for j yields
ln(~~:J
j= - - - ln a
to represent this ratio, the propagation delay for a
single stage is finally obtained as
tr=
A'a
If all pairs of successive stages are scaled by the
factor a, then the overall propagation delay across a
j-stage driver is given by
This is a design equation for j which is defined as the
number of stages in an optimally designed multistage symmetric CMOS inverter driver.
Substituting the expression for j into the expression for the propagation delay across a j-stage driver
given above yields the propagation delay as follows:
tP,tota/
, ((EXT)
Cl'
= A In - - -1c/NJ
n
Cl'
j
tP,total
=
I
tp; =
j
X tp =
jA'a
i=l
Input Capacitance of Successive Stages
Is Also Scaled by a Factor of a
In the analysis up to this point, it has been assumed
that the channel length of all NMOS and PMOS devices in a j-stage CMOS driver are equal and the
channel area of both the N- and P-channel MOSFETs of each stage are scaled by a factor a over the
preceding stage. Hence the input capacitance, and
therefore the load capacitance of each stage, is also
scaled by a factor a times the preceding stage or
Optimal Design for a Multi-Stage
CMOS Driver
To determine the optimal design of a multi-stage
CMOS inverter driver, the expression for tP,totaI
should be minimized with respect to a. This is obtained by taking the derivative of tr.total with respect
to a and setting it equal to zero. Solution of this
equation yields the value of a for which tr.total has a
local minimum. Taking that derivative yields
dtl',total
da
= !!__
da
[A' ln(CEXT)
~]
C
In a
1N1
= A' In(~~:~) d~
Cnaa)
460
Chapter 27/CMOS Drivers
f(a)=aAna
3.4
3.2
3.0
Multi~Stage Cl\10S Driver Rule of
Three
i
i-
For practicality in fabrication, a = e is generally
rounded off to a = 3 and this design rule is appropriately referred to as the rule of three.
t
T
Example 27.3 Optimal Design of a
Multi-Stage CMOS Driver
2.8
What is the opt1mai number of stages to use in a
multi-stage CMOS driver with a load of 10 pF. Design this driver with an initial stage having WN 1/LN 1
= 4µ,m/2µ,m and Wr 1/Lp 1 = 10µ,m/2µ,m. Assume
the gate oxide capacitance per unit area is C,'" = 690
aF/ µ,m 2 .
e
2.6
1------+-----1---+--------+-----1---1---___.
1
2
e 3
FIGURE 27.4
5
4
a
6
Solution The input capacitance of the first stage is
the sum of its gate capacitances or
Plot of a/In a: local minimum occurs
CINI = Cc.NJ
+
CcP1 = (WN1LN1
= [(10µ,)(2µ,)
Using the quotient rule of derivatives and equating
to O then gives
dtl',to/11/
= A ln(CEXT) In
I
da
CIN 1
Q' -
1 = 0
= 2.718
Therefore, a local minimum occurs at a
value of
frn;n(a)
=-
Q'
1n a
I
=
e with a
=e
min
Thus,
The optimum design for a multi-stage
CMOS driver has the channel sizes of
each successive stage scaled by a factor
of e = 2.718 over the previous stage,
Hence, substituting a
gives
= e into the expression for
.J In(CExT)
CIN,
j
(C,xr)
=---=In --
In e
wl',L1'1)C()x
-2
µ,
= 19.3
fF
Using the expression forj derived in this sub-section
.
[ (lOp) ]
.7 = ln (l . f) = 6.25
93
(In a)2
which has a solution for In a = l or
a = e
+ (4µ,)(2µ,)]
+
690a
C1N1
which is the optimal number of stages in a multistage CMOS driver.
Rounding this off, the optimal number of stages in
this driver is 6. Figure 27.5 shows such a six-stage
driver. Each stage is three times the size of the preceding stage, except the final stage is a little over
twice the size of the fifth stage (this is due to rounding of j to 6 and using the rule of three instead of the
"rule of e"). Note that the final stage has an input
capacitance 1/3 that of the external capacitance CEXT·
The sum of propagation delays across all stage except
the fifth and sixth is approximately 0.93 ns. The total
propagation delay is less than 1 ns which is a further
reduction in the delay calculated in Example 27.2 for
the four-stage driver in Figure 27.2. (Calculation of
these delays is left as a homework problem.)
Disadvantage of Larger Silicon Area
The previous examples and preceding derivation indicate that multi-stage drivers definitely decrease the
time needed to charge and discharge a large load
capacitance. The obvious disadvantage is that the ad-
27.3
C
.•.
:;1
0
'(
I
!
I
I
I
p06
8 lOµIl!
2µm
[
rl? !Ql,l!I! J-J
N
V
Vm
I
CMOS Tri-State Pin Drivers (PAD Drivers)
I~
7
2µm
/ '-1
;J
30µm
L _2µm
l
i
rl pl
''-1 _
J90µm
2µm
7
1
(J
05
03
rl ~- 2721!!11 . rl p
L_ 2µm "-1
N
I
461
I
!
. 1750µm
_ 2µm
i
V
~-~-
;
I
½xr..L
2µm
N:i
N~
½m =58 fF
FIGURE 27.5
2µm
2µm
Nt
4,, = 174 fF
Ni
4,, =522 fF
2µ
2µm
N
lOpF
!
0
,~
Cm,= 1.56 pF
Cm,= 3.38 pF
Six-stage Driver Driving a 10 pF Load (Example 27.3)
ditional inverting driver stages require additional silicon surface area. Thus, a driver should not be designed to operate faster than is really necessary.
Inverting or Non-Inverting Drivers
The discussion in this section ignored whether the
output of the final stage should be an inversion of
the original driving signal or not. If an inverter is
required and the design equations yield an even
number of stages (a non-inverter), then one additional or one less stage should be used, and the size
ratio froIT1 stage-to-stage is selected using the rule of
three.
27.3 CMOS TRI-STATE PIN
DRIVERS (PAD DRIVERS)
The previous section considered multi-stage CMOS
inverter drivers used to drive large capacitive loads.
An example of such a large capacitive load is an output pin of an IC. However, when driving IC output
pins, it is advantageous to use a tri-state driver.
Pin Driver (or Pad Driver) Circuit
Figure 27.6 displays a tri-state pin driver (sometimes
referred to as a pad driver). The signal to be driven is
input (IN) to the NAND and NOR gates. The NAND
and NOR signals are then increased in drive by two
using successive inverters whose MOSFETs have increasing channel sizes. These increased drive NAND
and NOR signals then separately drive the gate terminals of relatively large P- and N-channel MOSFETs. Note that the gate terminals of the final stage
MOSFETs are not connected in a CMOS inverter to
turn on and off the output NMOS and PMOS devices.
Truth Table of Pin Driver
To verify that the circuit of Figure 27.6 can be used
as a tri-state driver, a truth table is constructed.
ENable Low-Output High-Impedance ZState
If the ENable input is low, then the NAND output
is held high. With the NAND output high, the gate
terminal of the PMOS device PPAD is high and the
PMOS output device is cutoff. Thus, no output pullup path to V00 is available from the output node
PAD.
Considering the lower portion of the circuit in
Figure 27.6, EN is inverted and fed into the NOR
gate. With EN low, EN is high and the output of the
NOR gate is held low. The gate terminal of the
NMOS device NPAD is therefore also held low. Thus,
no output pull-down path to ground is available
from the output node PAD. Hence, when the ENable signal is held low, neither an output pull-up nor
462
Chapter 27/CMOS Drivers
VDD
0
7$ii
~~
2251!!!!_
2µm
IN
[945µmp
2µm
EN
~
901!:J!l
~µm
3~
PAD
i
I
2~=
iluii
(a)
IN~PAD
EN
(b)
FIGURE 27.6
Tri-state NAND/NOR Pad Driver: (a) Circuit, (b) Circuit symbol
an output pull-down is present and the output is in
a high-impedance Z-state. This verifies lines 1 and 2
of the truth table in Table 27.1
Output Low State-EN High and IN Low
With IN low, the NAND output node is high. With
EN high (EN low) and IN low, the NOR output is
also high. With the NAND and NOR outputs both
high, the gate terminals of PrAo and Nr,Ao are also
both high. Therefore, NPAD is active and an output
pull-down path to ground from PAD is present.
With the NAND node high PPAD is cutoff and no
TABLE 27.1 Truth Table for the
Non-Inverting Tri-State Pad Drivers
of Figures 27.6 and 27.8
EN
IN
NAND
NOR
PAD
1
2
0
0
0
z
z
3
1
1
1
0
1
1
1
1
0
0
1
0
0
0
1
4
pull-up path is present. Thus, for EN high and IN
low, the pad-driver is in an output low state. This
verifies line 3 of Table 27.1.
Output High State-EN and IN High
If both the EN able and IN put signals are high, then
the NAND output node is low. With IN high, the
NOR node is also low. Hence, with the NAND and
NOR nodes both low, the gate terminals of the devices Nl'AD and Pl'AD are also both low. Thus, PPAD
is active and an output pull-up path to VDo exists.
Also, NPAD is cutoff and no output pull-down path
is present. Therefore, for EN and IN high, the paddriver output is high. This verifies line 4 of the truth
table in Table 27.1.
Pad Driver Is a Non-Inverting
Tri-State Driver
Examining Table 27.1, the IN put signal is propagated
to the output node (labeled PAD), non-inverted
when the ENable signal is high. When EN is low,
27.4
Tips, Tricks, and Gimmicks
Make-Before-Break and
Break-Before-Make Circuits
Figure 27.7a shows a logic configuration consisting of two-input AND and OR gates. This
circuit has a single input IN and two outputs
AND and OR that are fed back to the inputs
as indicated. The input IN is fed to both input
gates. The AND output is fed to the second
input of the lower gate and the OR output is
fed to the second input of the upper gate.
Operation
To analyze the operation of this configuration,
assume the propagation delay across each of
the four gates (including the inverters) is 1 ns.
If IN is low, the AND output is low regardless
of the other NAND gate input. The two inputs
to the OR gate are therefore both low and the
OR output is also low. This is shown in Figure
27.7b where both outputs are low for the first
few nanoseconds.
Input Low-to-High Transition
When IN switches high, the output of the OR
gate switches high two nanoseconds later, 1 ns
for the gate delay across the NOR gate and a
second ns for the inverter Im:• Upon initial
switching of IN, the OR output is still low and
the AND gate does not yet have two high inputs. That is, the two inputs to the AND gate
are not high until 2 ns (the gate delays across
the NOR gate and I01J after IN goes high.
Hence, 2 ns later (4 ns after IN goes low-tohigh) the AND output goes high. This is observed in the waveforms in Figure 27.7b.
Input Higlt-to-Low Transition
A similar situation occurs when the input signal
IN is switched low. The AND output switches
2 ns later and the OR output falls 2 ns after
that.
Make-Before-Break Circuit
This circuit is useful as a make-before-break circuit and this is accomplished by using the
PAD Driver with Ilrcc1k-Bcforc-lvli1kc Embodiment
463
AND output as an Jctivc-low enable signJI
Jnd the OR output JS Jn active-high enable.
Upon switching of the input high, the OR enable is made before the AND enable breaks.
Upon switching of the input low, the AND enable is made before the OR enable breaks.
Break-Before-Make Circuit
The circuit of Figure 27.7 can also be used as a
break-before-make circuit by using the AND
output as an active-high enable and the OR
output as an active low enable.
It should be noted that the delay time between the switching of the outputs can be increased by including an even number of additional inverter stages between the output of the
NAND and NOR gates and the AND and OR
outputs.
the output node PAD is in a high-impedance
Z-state. Thus, the pad driver circuit of Figure 27.6 is
a 11011-inverting tri-state driver. The logic symbol for
the tri-state pad driver is shown in Figure 27.6b.
27.4 PAD DRIVER WITH BREAKBEFORE-MAKE EMBODIMENT
The propagation delays for the NAND gate and inverters I/\ND and IN/\ND of Figure 27.6 are essentially
the same as those for the NOR gates, IoR, and INoR•
Thus, when the pad driver of Figure 27.6 is in its
ENabled state, the output stage devices PP/\D and
N 1,/\o change modes of operation in a simultaneous
fashion similar to the MOSFETs of a CMOS inverter.
Since the MOSFETs in the pad driver final stage are
relatively large, the short circuit switching current
that will exist between V DD and ground through Pl'/\D
and Nl'/\D will be quite large, dissipating a momentary large amount of power.
To avoid this sizeable power dissipation, J
break-before-make AND-OR embodiment should
be implemented. Such a configuration is shown in
Figure 27.8. The AND node is fed to an additional
input of the NOR gate and the OR node is fed to an
additional node in the NAND gate. Thus, if IN is
464
Chapter 27/CMOS Drivers
VIN(V)
V:u
• •· · · ······-'----►t(ns)
IN ' >---~-----1
V AND(V)
Yoo\
0
I
i________________
__.
►
t(ns)
YoaCV) .
>--'----{ I
OR
•
VDDI
I
01
2
4
6
(a)
FIGURE 27.7 "Make-before-Brea!<' AND/OR Circuit:
(a) Schematic, (b) Input and output waveforms: upon
switching low-to-high, the OR output responds first;
8
10
12
14
L►
16
t(ns)
(b)
upon switching high-to-low the AND output responds
first
IN o~
EN c}----+--~----1
I
'- ~o PAD
I
I
I OR
FIGURE 27.8
~[NPAD
Tri-state Pad Driver with AND/OR "Break-before-Make" Configuration
switched low-to-high when the pad driver is ENabled, the NMOS pull-down device will cutoff slightly
before the PMOS device turns on and pulls the output high. Similarly, when IN switches high-to-low
the PMOS device will cutoff before the NMOS device turns on.
A disadvantage resulting from using the breakbefore-make circuitry is that the output voltage can
shoot beyond the rails when switching states. However, if the nodes connected to the pins external to
the IC are properly protected from voltage spikes,
this problem is minimal.
Chapter 27
Problems
465
CHAPTER 27 PROBLEMS
27.1
For a load capacitance of 5 pF, calculate the input
capacitance and the propagation delay for each
stage of the two-stage inverter of Figure P27.1. Use
VrN = 1 V, Vrp = -1 V, and c;,x = 690 aF/ µ,m 2
(Remember. kN = kN(WN/LN), kp = k~(Wp/Lp),
kN = /LNCox, and k{, = µ,pCox; for silicon /LN =
0.058 nl/V · s and µ,p = 0.023 m 2 /V · s.)
27.6
Repeat Problem 27.4 with all MOSFET W/L ratios
doubled.
27.7
Calculate the optimum number of stages that provide minimum propagation delay for a multi-stage
CMOS driver with a load of 5 pF. Let the first stage
have WN1/LN 1 = 4µ,m/2µ,m, and Wp1/Lp1 = 10µ,m/
2µ,m. Use C,'.x = 690 aF/ µ,m 2 •
27.8
Calculate the propagation delays associated with
each stage in Problem 27.7. Use VoD = 5 V, V-rN =
1 V, VTP = -1 V, and Cx = 690 aF/ µ,m 2 •
27.9
Calculate the optimum number of stages that provide minimum propagation delay for a multi-stage
CMOS driver with a load of 5 pF. Let the first stage
have WN1/LN 1 = 4µ,m/2µ,m and Wp 1/L 1, 1 = 10µ,m/
2µ,m. Use c;,x = 1000 aF/ µ,m 2 .
27.10
Repeat Problem 27.8 for MOSFETs with
1000 aF/ µ,m 2 .
27.11
Repeat Problem 27.8 for MOSFETs with transconductance parameters that are doubled.
HXTT
27.12
i
Repeat Problem 27.7 with WN 1/LN 1 = 8µ,m/2µ,m
and Wp 1/Lp1 = 20µ,rn/2µ,m.
27.13
Calculate the propagation delays for each inverter
in Problem 27.12.
27.14
Design a make-before-break AND/OR circuit that
has larger time delay than that shown in Figure
2
27.3
Repeat Problem 27.1 for MOSFETs with transconductance parameters doubled.
27.4
Calculate the input capacitance and the propagation delay for each stage of the 4-stage non-in-
.
C
l
FIGURE P27.1
VDD = 5 V
_j
VDD =5 V
q
[50µmp
2µm 02
I
I
VOUT2
_J
Cm,
FIGURE P27.4
c,N2
Vmm
1¼
I'pF
l~~N
-1c~lllN
l
2µm
1_?1Qµ_II1 p
2µm 04
Youn
~--~--
2µm
02
o,
-.:-
-.:-
c[N,
c;" =
VDD = 5 V
l
lOµmp
2µm o,
= 1000 aF/ µ,m 2 .
Repeat Problem 27.4 with C~x
Repeat Problem 27.1 using Cc'ix = 1500 aF/ µ,m
02
= 1 V,
27.5
27.2
2µm
l[ J2QgmN
verting driver of Figure P27.4. Use V-rN
V-1T = -1 V, and c~x = 690 aF/ µ,m 2 .
Cm,
466
Chapter 27/CMOS Drivers
FIGURE P27.15
27.7. Do this using additional inverters in series
with IAND and Irn,· Sketch the input and output
waveforms assuming each CMOS gate has a propagation delay of 1 ns.
27.15
Construct the truth table for the tri-state NANO/
NOR pad drivers of Figure P27.15.
27.16
Construct a truth table for the AND/OR circuit of
Figure P27.16. For time delays of 2 ns for each gate,
sketch the waveforms for a pulse of input voltage
low-to-high and then high-to-low.
IN
o~~---LY---f>2-l--o
~= -=
-- -1>-{>e 1
AND
---o OR
FIGURE P27.16
DYNAMIC CMO
In the specialized areas of high speed, higher fan-in,
extremely low power dissipation and/or very high
packing density, other digital logic circuit alternatives
to CMOS have been considered with some success.
In this chapter, we describe three of these alternatives to CMOS. The circuits are basically NMOS or
CMOS gates with slight modifications that provide
improvements in the specialized areas.
The specific digital logic families described in
this chapter are called pseudo-NMOS logic, dynamic
logic, and CMOS domino logic. Each of these have
specific operating advantages over NMOS or CMOS
but also exhibit disadvantages in other areas.
28.1
PSEUDO-NMOS LOGIC
Hence, a discussion of precharging and discharging
of a load capacitance is appropriate here.
28.2 CMOS PRECHARGING
AND DISCHARGING OF A
LOAD CAPACITANCE
The gates to be considered have the same disadvantages that NMOS combinational logic circuits possess. Namely, a degraded output low voltage and
high power dissipation. The solution to overcoming
these disadvantages is using CMOS logic. With
CMOS combinational logic gates, in addition to a
rail-to-rail output, power is dissipated only while
switching.
Pseudo-NMOS logic consists of an NMOS gate
Storage of Charge in a Non-Driven
Load Capacitance
with a PMOS transistor load. Figure 28.la displays a
typical pseudo-NMOS AND-OR-invert gate. Note
that the P-channel load device at the top of the circuit is always operating in the linear mode since the
gate is grounded and the source is at Vsy = VDD =
5 V. Hence, the output is precharged high by the
PMOS load. When inputs are applied, the logic function implemented is
Figure 28.2a shows a two input, two transistor MOSFET circuit with a load capacitance CLOAl)· The circuit
is made up of a single pull-down NMOS device and
a single pull-up PMOS device, with the gate of each
MOSFET serving as separate circuit inputs. From the
chapters on CMOS combinational logic, recall that if
the input connected to the gate of the PMOS device
is low, a low impedance output pull-up path to VDD
is present to charge the load capacitance. If the input
to the gate of the NMOS transistor is brought high,
a low impedance output path to ground is available
to discharge the load capacitance.
F=A·B+C·D
Figure 28.1b shows the logic syn1bol for this gate. Of
course, other pseudo-NMOS gates can be implemented by structuring only the NMOS circuits. Thus,
compared to CMOS, this family has higher packing
density, since for n inputs only n + 1 transistors are
required.
The main disadvantage with pseudo-NMOS
gates is the large static power dissipation that occurs
whenever a pull-down path is activated. Since the
PMOS load is always active, when a pull-down path
is also active, current flows from VDD to ground.
The principle of operation in these pseudoNMOS logic gates (and in the gates to follow in this
chapter) is to precharge the load initially and then
discharge the load as the input logic levels dictate.
Charging the Load Capacitance
If both inputs to the circuit of Figure 28.2a are low,
as shown in Figure 28.2b, the PMOS device is
brought into active operation and the NMOS device
is cutoff. Thus, the output capacitance will charge
through the source-to-drain channel of the PMOS
transistor. When the load capacitance has fully
charged, the output voltage is
467
468
Chapter 28/Dynamic CMOS
AB-
Y.~
i---c
F=AB +CD
C
NMOS pull-down
D-
(b)
(a)
FIGURE 28.1
Pseudo-NMOS AND-OR-invert (AOI) Gate
?
y O.P
o---------q
Yw
Your
y-
al
load
capacitance
charges through P
~P(ON)
~*'-N(OFF)
(b)
(a)
Y0 0
Yo.,
Le! [_ _
,:.)
load
JP(OFF)
' '---1
N
holds charges
Your
'------0------1
+
(c)
Pull-up PMOS and Pull-down NMOS
with a Capacitive Load and Separate Inputs: (a) Circuit,
(b) Load capacitance charges through active pull-up
FIGURE 28.2
load
capacitance
discharges through
capacitance
(d)
PMOS, (c) Load capacitance holds charge (and voltage)
when both MOSFETs are cutoff, (d) Load capacitance
discharges through active pull-down NMOS
?.8.3
DvnJmic 0\10S Logic
469
Va,.(V)
t
VDDi
ol
►
V 0 :,,(V)
t
t
VDDi
I
o I-------------~
...
Yaur(V)
t
v:t/. . .____,(
\.__ - v
- ./, -
corresponds
to (b)
----y------ A
corresponds
to (c)
-
-y-· ·- __;
corresponds
to (d)
(e)
FIGURE 28.2 (continued)
(e) Voltage waveforms of demonstrating (a) through (d)
Output Capacitance Holding Charge
If after the output capacitance is fully charged, the
PMOS gate circuit input is brought high, and the Pchannel MOSFET will be cutoff. If the NMOS gate
circuit input remains low as shown in Figure 28.2c,
neither an output pull-up nor output pull-down path
is present. This is (as referred to in Chapter 25) a high
impedance output Z-state. Since the load capacitance at the circuit output is allowed to fully charge
before the PMOS device is cutoff, the load capacitance must still be fully charged, since no output
pull-down path is available to discharge CLO/\D·
Since a charged capacitor has a voltage across its terminals, the charged load capacitor of Figure 28.2c
must also have a voltage. Furthermore, the charge
stored in Cu)i\D is still equal to that required to pullup the output to VDD· Hence, the voltage at the circuit output (across the load capacitance) is the supply
voltage or
VouT(storcd charge)
=
Vou
=
ViJO
Discharging the Load Capacitance
If the circuit input connected to the NMOS gate is
brought high, while the PMOS gate remains at VDo
(as shown in Figure 28.2d), a low-impedance output
pull-down path to ground is present. The charge
stored in the load capacitance then discharges
through the drain-to-source channel of the N-channel MOSFET. The output voltage then reduces to
V01 == ground = 0
Figure 28.2e shows a graph of the voltage variations with time corresponding to the switched inputs of the previous sub-sections.
The analysis of this section serves as an
introduction to the charging and discharging of
CMOS logic structures presented in the following
sections.
28.3
DYNAMIC CMOS LOGIC
The basis for dynamic CMOS logic is displayed by
the circuit of Figure 28.3. To make the gate dynamic,
a clock pulse is applied to the gate of complementary
P- and N-channel devices at the top and bottom of
the stack, respectively. Note that this gate consists of
an NMOS logic circuit whose output node is precharged to VDD by the PMOS transistor, when the
clock is zero. Furthermore, the output node is conditionally discharged by the NMOS transistor connected to ground when the clock is high. For n inputs, dynamic logic requires n + 2 transistors and
thus a reduced packing density as compared to
470
Chapter 28/Dynamic Gv!OS
logic
inputs
Vm2
o-+-
NMOS
l?gi~
circuit
I
VCL!{ o-1
-
-~
[_jNCL!{
-1
J_
FIGURE 28.3
PMOS device
Basic CMOS Dynamic Gate: NMOS logic circuit is placed between a clocked NMOS and
CMOS. Hence, the dynamic logic circuits have small
area, high speed, and compact layouts.
However, such gates also have disadvantages, as
follows:
1.
2.
3.
Circuit operation is more complex due to the required clock.
The inputs can only change during the precharge
phase and must be stable during the evaluate
portion of the cycle.
Simple single phase dynamic CMOS gates cannot be cascaded.
Example 28.1
Dynamic CMOS Logic Gate
What logic function is performed by the dynamic
CMOS logic gate of Figure 28.4a?
Solution Examining the NMOS logic core portion
of Figure 28.4a, it is easily seen (according to the rules
of Chapter 22) that the logic function performed by
this circuit is
F =AB+ C + DE
Figure 28.46 shows the logic symbol solution for this
example.
Example 28.2
The last disadvantage requires explanation.
Upon precharging, the output nodes of two succeeding stages are changed to VDD· However, upon application of a clock pulse when the first output is
switched low, some delay is incurred due to the finite
pull-down time. Thus, the precharged output node
of the driving gate can still discharge the output node
of the cascaded gate, before the first gate is correctly
evaluated resulting in an erroneous output.
The following are two examples of dynamic
CMOS logic gates.
What logic function is performed by the dynamic
CMOS logic gate of Figure 28.5a?
Solution Examining the NMOS logic core portion
of Figure 28.5a, it is easily seen that the logic function
performed by this circuit is that indicated in Figure
28.56
F = (A
+
B)(C
+
D)
+
(E
+
F)G
+
H
Figure 28.56 also shows the logic symbol solution for
this example.
28.4
CMOS Domino Logic
471
(a)
-F=AB+C+DE
(b)
FIGURE 28.4
28.4
Dynamic CMOS Logic Gate of Example 28.1: (a) Circuit, (b) Logic symbol
CMOS DOMINO LOGIC
CMOS domino logic gates are an extension of dynamic CMOS gates that allow cascading of stages.
The simple modification entails incorporating a static
CMOS inverter at the output of each logic gate. A
driving stage is displayed in Figure 28.6. During precharge of this gate when CLK = 0, the output node
of the dynamic gate is precharged high and the output node of the CMOS inverter is low. Since subsequent stages are connected to the output of the
inverter, each will be turned off during the precharge
phase. However, when the clock goes high with logic
inputs applied, the output of the driving gate will
conditionally discharge, allowing the output of the
inverter to conditionally go high. Each connected
gate output can then make a transition from low-tohigh, in sequence. In a domino logic circuit with cas-
caded logic blocks, when the driving gate evaluates,
the next stage then evaluates and then the next and
so on in the same manner that a line of dominos
would fall. There is no restriction on the number of
logic stages that can be cascaded provided that all
stages can evaluate during one clock pulse. One advantage of domino logic is that for large fan-in, fewer
transistors are incorporated than for CMOS. For n
inputs, domino logic requires n + 4 transistors,
whereas CMOS requires 2n. Another advantage of
domino logic is that a single clock can be used to
precharge and evaluate all stages at the same time.
However, this type of logic also has disadvantages.
First, each logic block must incorporate a separate
inverter. Also, each block performs only non-inverting logic.
Finally, as is the case with all dynamic CMOS,
charge redistribution can be problematic.
V0,,=5 V
(a)
AB
-
c~
DE-
OUT= (A+B)(C+D) + (E + F)G + H
(b)
FIGURE 28.5
Dynamic CMOS Logic Gate of Example 28.2: (a) Circuit, (b) Logic symbol
V 00
l
precharge. output
~,
--q[~ Po
JIIL.,N;;
+d,..
FIGURE 28.6
CMOS Domino Logic Gate
connected
gates
Chilpter 2ti
4 73
Problems
CHAPTER28PROBLEMS
28.1
What logic function is performed by the pseudoNMOS logic gate of Figure P28.1?
28.2
\,\That logic function is performed by the pseudoNMOS logic gate of Figure P282?
28.3
Design a pseudo-NMOS logic g.:ite to perform the
logic function
Modify the circuit of Figure P28.2 to perform the
logic function
F = (AD
28.8
+ BE)CF
Modify the circuit of Figure P28.5 to perform the
logic function
F = AB(C + C) + DH + (E + I)F
F = A +BC+ D
28.4
28.7
Design a pseudo-NMOS logic gate to perform the
logic function
F
= (!\B +
C)
+ DE
28.5
\A/hat logic function is performed bv the pseudoNMOS logic gate of Figure P28.5?
28.6
What logic function is performed by the pseudoNMOS logic gate of Figure P28.G?
Your
0
FIGURE P28.5
...L
FIGURE P28.1
Your
T----o
i
J
-·q[_PL
i
(, Your
--~ r-tc
··1 ____ ~
VB 0
I
-l~NB
- - ~ ! .. --·-- ... .J
...L
FIGURE P28.2
FIGURE P28.6
474
Chapter 28/Dynamic CMOS
Yoo
0
0
I
q
PCLK
VOIIT
~
VA
~
l~N=
VCLK 0
i
FIGURE P28.10
FIGURE P28.9
28.9
What logic function is performed by the dynamic
CMOS logic gate of Figure P28.9?
28.10
What logic function is performed by the dynamic
CMOS logic gate of Figure P28.10?
28.11
Modify the circuit of Figure P28.9 to perform the
logic function
28.12
Modify the circuit of Figure P28.9 to perform the
logic function
F = (A + C)E(BF + DC)
28.13
F = (A + C)(B + D + E)F
Modify the circuit of Figure P28.10 to perform the
logic function
F
= (A +
BCD)E
f
PCLK
VOIIT
FIGURE P28.14
Chapter 28
Problems
4 75
28.14
\!\That logic function is performed by the dynamic
CMOS logic gate of Figure P28.14 7
28.16
Examine the logic gate of Figure P28.16. Describe
its operation.
28.15
Modify the circuit of Figure P28.14 to perform the
logic function
28.17
Design a pseudo-NMOS logic gate to perform the
logic function
F
= AB + CD + E + (F + G)H
F = (A + B)C + DE(F + G)
Sketch this circuit.
28.18
Design a pseudo-NMOS logic gate to perform the
logic function
F = [(A + B)C + DE(F + G)H]I
Sketch this circuit.
28.19
Design a dynamic CMOS logic gate to perform the
logic function
F = (A + B)C + DE(F + G)
Sketch this circuit.
I
V=c
Vcun
28.20
Modify the pseudo-NMOS logic gate of Figure
P28.5 to be a dynamic CMOS logic gate that performs the same logic function.
28.21
What logic function is performed by the domino
CMOS logic gate of Figure P28.21?
28.22
What logic function is performed by the domino
CMOS logic gate of Figure P28.22?
28.23
Modify the domino CMOS logic gate of Figure
P28.21 to perform the logic function
o .................... ____ . .
FIGURE P28.16
F =(AD+ B)CE
V=
u-__,_-----i
FIGURE P28.21
4 76
Chapter 28/Dvnamic CMOS
Yno
i
Ve O
+If
Va C
VLU c, ..........
[
L .................................................................................................. j
FIGURE P28.22
[JN~
COMPARISON
AND
INTERFACING OF
LOGIC FAMILIES
The values displayed are typical and various vendors
provide chips with similar parameters.
The three versions of Schottky TTL logic listed
in Table 29.1 are LSTTL (low-power Schottky TTL,
discussed in Chapter 8), ALSTTL (advanced lowpower Schottky TTL, discussed in section 9.1), and
FAST (Fairchild Advanced Schottky TTL, discussed
in section 9.2) which offers an improvement in speed
over the LSTTL and ALSTTL sub-families.
The LSTTL sub-family of ICs provides a current
and power reduction improvement over standard
TTL by about a factor of 5. Furthermore, the LSTrL
sub-family is faster because of the Schottky BJTs,
which do not operate in the saturation mode. Because of these improvements, LSTTL has forced
standard TTL (non-Schottky) into obsolescence.
From Table 29.1, we can observe that the
ALSTTL sub-family offers even lower power dissipation, as well as increased speed. Furthermore, the
FAST sub-family has additional speed improvement
with increased power dissipation. The improvement
in speed for these two lines is due to the use of advanced fabrication and processing of the IC chip.
The ECL sub-families listed in Table 29.1 are for
MECL (Motorola ECL). The three versions of ECL
shown in Table 29.1 are MECL lOK, MECL lOKH,
and MECL III. The MECL lOK has been the industry
standard for high speed applications for years. Note
that the MECL sub-families have the fastest speed
by far of any logic family. However, the power dissipation per gate is also the largest.
The MECL lOKH and MECL III are advanced
versions of the MECL lOK. The MECL lOKH line
offers high speed with an improvement of 100% in
propagation delay from the standard MECL lOK (see
This chapter gives a comparison of important digital
logic families and describes interface circuits that are
necessary in order to interconnect different logic
families in a single system. The logic families considered are STTL, ECL, CMOS, and gallium arsenide
(GaAs) logic families, the latter presented in later
chapters. The parameters compared are speed,
power dissipation, noise margins, and packing
density.
Interface circuits are necessary in order to transform the output current and voltage levels from one
logic family into compatible input current and voltage levels for the connected family. Descriptions of
various interface circuits are presented.
29.1 COMPARISON OF SILICON IC
LOGIC FAMILIES
The various silicon logic families discussed in this text
have evolved through the years as state-of-the-art
IC fabrication has advanced. Each of these families
have advantages as well as disadvantages relative to
one another.
In previous chapters, analysis of the basic logic
circuits for each family has led to the determination
of the various logic parameters. In this section, we
verify previously determined values by comparing
these parameters with actual IC parameters obtainable from manufacturers' data sheets. The silicon
logic families considered are STTL, ECL, and CMOS.
Table 29.1 lists the speed and power parameters
for several versions of ICs for STTL, ECL, and
CMOS. These parameters are frequently used for determining the selection of one family over another.
477
478
Chapter 29/Comparison and Interfacing of Logic Families
TABLE 29.1
Speed and Power Parameters for Silicon Logic Families
MECL
STTL
Parameter
Quiescent supply current
per gate
Power per gate
(quiescent)
Propagation delay
Speed-power product
Maximum clock
frequency (OFF)
Maximum clock
frequency (counter)
Units
LS
ALS
FAST
lOK
lOKH
mA
0.4
0.2
1.1
5.0
5.0
mW
2.0
1.0
5.5
26
ns
pJ
MHz
9.0
18
33
7.0
7.0
35
3.7
19.2
125
MHz
40
45
125
Table 29.1). The MECL III has a similarly small propagation delay; however, flip-flop toggle rates are improved by a factor of 2 to 4.
The last two columns in Table 29.1 provide parameter values for two versions of CMOS, standard
CMOS, and high-speed CMOS (HCMOS). Note
that HCMOS has speed comparable to LSTTL. Furthermore, note that CMOS exhibits extremely low
power dissipation per gate. Coupled with the fact
that CMOS requires the least amount of chip area
of any family for a given logic function, it is not
surprising that portable electronic circuits (hand
calculators, watches, and so on) all use CMOS
circuitry.
29.2 COMPARISON WITH
GALLIUM ARSENIDE DIGITAL
LOGIC FAMILIES
Digital logic circuits fabricated from gallium arsenide
(GaAs) are the most promising of all in the area of
ultrafast digital ICs. Using GaAs NMESFET logic
gates, such as those described later in this text, propagation delays on the order of 10 ps have been
achieved at room temperature. Using GaAs high
electron mobility transistors (HEMTs), propagation
delays approximately 30% lower have been obtained
at room temperature and even lower at 77 °K. These
magnitudes of propagation delays indicate that GaAs
digital logic circuits are the fastest of all digital logic
families.
CMOS
III
Standard
HCMOS
10
0.0001
0.0003
26
54
0.0006
0.001
2.0
52
150
1.0
26
300
1.1
59
550
125
0.075
4.0
8.0
0.01
40
150
300
1200
5.0
40
Figure 29.1 displays the speed-power characteristics for GaAs inverter gates as well as silicon
NMOS, CMOS, and ECL for comparison purposes.
Actual data points for each case have been achieved
inside each football-like shape. Note the lines of constant power-delay product expressed in femtojoules
(fJ) and picojoules (pJ). Clearly, GaAs MESFET digital
logic circuits indicate an order of magnitude improvement over CMOS in this parameter.
Observe that GaAs digital ICs possess the lowest
propagation delay of any of the other families. However, the power dissipation is larger than that for silicon CMOS.
Also, note that from this graph CMOS is faster
and dissipates less power than NMOS and hence the
extensive use of CMOS gates over NMOS gates.
29.3 INTERFACING
LOGIC FAMILIES
Digital logic systems usually consist of component
chips from a single logic family. In some instances,
however, different logic family chips are mixed in the
overall system. This is done to take advantage of the
best capabilities of each family. For example, in the
memory portion of a logic system, CMOS can be
used more advantageously since this family has the
highest packing density and lowest power dissipation of any of the families. On the other hand, if high
speed is required in another portion of the logic system, ECL circuitry can be used.
29.3
Interfacing Logic Families
4 79
Propogation ( ms )
Delay
stage
10'
100
l
0.1
0.01
···i······················································-·+-·-··---·--·····-,·······················································'·························································.. ,··········►
0.01
0.1
1
lO
Power
Dissipation
(·mW)
stage
100
FIGURE 29.1 Propagation Delay per Gate Versus Power Dissipation for Various Logic Families with Constant PowerDelay Product Lines Indicated
The interconnection of different logic family circuits requires compatibility of the voltage and current
levels between the two circuits. Furthermore, the
various logic families in general have very different
logic levels. Hence, a direct connection of the output
of one family to the input of another family is often
not possible. Then, an interface circuit or translator
circuit is placed in between the two chips. Many in-
terface circuits are available in chip form. Basically,
an interface circuit performs a level shifting of the
driving device output current and driven voltage to
make these compatible with the input of the driven
circuit.
In this section, we consider various examples of
interfacing. The interface circuits used are not
unique, as we shall see.
480
Chapter 29/Cornparison and Intcrfocing of Logic Families
Vr-c=V00 =5V
9
7
FIGURE 29.2
Resistor
STIL Driving CMOS with Pull-up
On the other hand, when the output is low, the output NMOS device must sink a large current. Since
this current can be on the order of mA, the voltage
produced by this current and the output resistance
can be larger than V,L for the STIL gate. To avoid
this situation, a buffer amplifier is used that sinks the
current of the STIL circuit. Figure 29.3 displays the
circuitry used to translate the CMOS levels to those
of STIL. The buffer circuit acts like an emitter-follower and provides a fixed output voltage and a low
resistance path for the TTL input.
Interfacing ECL with STTL
Interfacing STTL and CMOS
For STIL driving CMOS, the interface circuit required is simply a pull-up resistor R" as displayed in
Figure 29.2. The DC supply voltage for each family
is assumed to be the same where Vcc = VDo = 5 V.
The pull-up resistor is required because when
the STTL gate is in the high state V0 H = 4.3 V or 3.6
V with no load. If the STIL gate is also driving other
STIL gates, Vo1-1 can reduce still further. This value
then becomes critically close to the minimum input
high voltage for CMOS. The resistor Rf' acts as a voltage level shifter and pulls the output voltage up to
Vee- As long as the current through R" is small, the
associated voltage drop is small and V011 becomes
equal to V cc• Typically, R 1, has a magnitude on the
order of 1 kH.
For CMOS driving STIL, a translator circuit is
required only for the output low state. For VcJH, the
STIL gate draws zero current, since the input
Schottky BJT is in the reverse Schottky mode. Thus,
for this high value of voltage, a direct connection of
the output of CMOS to the input of STIL is possible.
Since ECL circuits normally operate with Vee at
ground and -VEE= -5.2 V or -5 V (as observed in
chapters 11 through 15), the normal logic levels are
negative and totally different from other logic fornily
voltage levels. An interface circuit that shifts the voltage levels is a definite requirement for translating
ECL to STIL or STIL to ECL. In order to translate
the logic levels between these two families, various
interface IC chips are commercially available. For example, Figure 29.4 displays two MECL/STIL translator circuits in block diagram form. The MC10124
and MC10125 are quad translators for STIL-to-ECL
and ECL-to-STIL, respectively. The ECL circuits use
-VEE= -5.2 V and the STIL circuits use Vee= 5 V.
To observe the level shifting performance of these
translators, we will observe basic circuits for each
case.
ECL Driving STTL
Figure 29.5 displays a simple translator circuit for
translating ECL voltage levels to STTL Rernll that
for ECL, V01_1 corresponds to -0.77 V and VuL corresponds to -1.58 V, while the corresponding levels
for STIL are 3.6 or 4.3 V and 0.4 V.
(a)
FIGURE 29.3
CMOS Driving TTL: (a) Without an interface, (b) With an interface
(b)
29.3
o--
interfacing Logic Families
r---04
5D
~
60-1·
I
0
481
2'.J~t>
02
-----() 4
30 --
--03
7D-~
·---0
1
I
10~ ~
1 1 ~ 12
140=t>-----o 13
150
(b)
(a)
= ground, pin 9 =
FIGURE 29.4 Translator IC Chips for ECL-to-TTL:
(a) MC10124 quad STTL-to-ECL translator, (b) MC10125
quad ECL-to-STTL Translator (pin 16
Vee= 5 V, pin 8 = -V11 = -5.2 V)
Considering the circuit of Figure 29.5 we observe
that the input portion is just a basic ECL inverter and
the output portion is a basic RTL inverter. When the
input to Q 1 is high (V 1N = -0, 77 V), the input BJT Q 1
is on while the reference BJT Q1, is off and Vc,1
low and is negative. Under this condition Q 0 is off,
and Vmn = Vee- Similarly, when the input to Q1 is
low, V1N = -1.58 V, Q 1 is off while QR is on. This
forces Q0 into the ON HARD mode since Vcc = 5 V
is applied through Re = 2 kfl directly to the base of
Q0 . This results in a large base current which is
=
Ill
5 - 0.7
=
v••
-------------0
-1.175 V
FIGURE 29.5
ECL-to-STTL Translator
-:-
2
= 2.15
mA
482
Chapter 29/Comparison and Interfacing of Logic Families
VIN
o-----J<l----
Your
D1
R.
FIGURE 29.6
i
1.18 kQ
STIL-to-ECL Translator
sufficient to force Q 0 into the ON HARD mode and
= 0.4 V. Hence, the input voltage is inverted
twice and the overall circuit provides noninversion
with the desired voltage level shifting. Note that the
output transistor is a Schottky BJT, thus avoiding operation in the saturation mode as would be the case
if Q0 were an ordinary (non-Schottky clamped) BJT.
and by substitution
VouT
STTL Driving EGL
Viu =
=
=
Vo11
3.6 V or 4.3 V
the voltage at point P is one diode drop above V 1c.:.
Hence, for the worst case,
Vp =
ViN +
Vn(ON) = (3.6)
+ (0.7) = 4.3 V
and the voltage at the base of Q 1 is obtained by superposition as
J
0.23 V
- liuiRrn - Vm:(ECL)
Vour
=
(5 2) [
(3k)
.
(3k) + (4k)
Thus, Q 1 is on, since V131 > V 1m = -1.175 V. Furthermore, QR is off and VouT is high, given by
Figure 29.6 displays a basic voltage level shifter that
translates STTL levels to ECL levels. The input portion of this circuit is simply a diode resistor voltage
level shifter, while the output portion is a basic noninverting ECL circuit with output buffer.
Considering
VIN
(4.3) [ (3k) (~) (4k) J
-(VEf. f3Rr
- Vour)R rn -
V ·(£CL)
Bt:
(5.2) - (0.75)]
(lO0) ( k)
(300) - (0. 75)
3
-0.77 V
= [
which is the output high voltage for ECL.
Considering V1N = V oL = 0.4 V, we again determine the voltage at the base of Q 1 by superposition but use
Vi,=
VcJL + Vn(ON)
+
= (0.4)
(0.7) = 1.1 V
Thus, by substitution
Viu = (l.l)L3k/~\4k)J -
= -1.6
V
5 -2)[(3k/:\4k)]
C
Chapter 29
This value for VB,I is less than V1rn and thus Q1 is off,
while QR is on. Hence, VoL'T is obtained as follows:
VouT
= - IRrnRcR - ViiE(ECL)
-[vllB - VBr(ECL) + Vn:]R
.
RE
CR
Problems
483
Interfacing ECL with CMOS
Since CMOS and TTL are essentially compatible
when Vol) = Vee = 5 V, the ECL-to-TGTL quad
translators MC10124 and MC10125 described previously are used as interfaces for ECL-to-CMOS.
- V8 E(ECL)
[
(-1.175) - (O. 75) + (5.2)] ( 00)
3
(1.18k)
- (0.75)
1.58 V
which of course is the output low level for ECL.
CHAPTER29PROBLEMS
29.1
Consider the ECL-to-STIL translator circuit of Figure P29.1. Calculate the collector current of Q1 for
V1N high and low. Use V8 io{ECL) = 0.75 V.
29.2
Calculate the output high and low voltage levels
for the circuit of Figure P29.1 with all resistors reduced to 1 kfl. Let Vm,(FA) = 0.7 V, VBE(SAT) =
0.8 V, VnE(ECL) = 0.75 V, and Vc 1JECL) = 0.2 V.
Ra
29.3
Determine the output high and low voltage levels
for the circuit of Figure P29.3. Let VmJFA) = 0.7 V,
VBE(SAT) = 0.8 V, VtdECL) = 0.75 V, and
V0JECL) = 0.2 V.
29.4
Repeat Problem 29.3, if all resistors except RL are
changed to 1 kn.
29.5
Figure P29.5 displays a MOS-to-STIL translator.
Calculate the output voltage levels for input low
and high values corresponding to CMOS. Use
VcE(HARD) = 0.5 V and VmJFA) = 0.7 V.
220Q
v••
---0
Your
-1.3 V
-VFE = -5.2 V
FIGURE P29.1
-VFE = -5.2 V
FIGURE P29.3
484
Chapter 29/Comparison and Interfacing of Logic Families
FIGURE P29.5
VINA
0--~
DIA
I
-~---------j
DLI
l>f~
Du
----0
Du
Qo
R.,
4.5 kn
6
-VEE= -15 V
FIGURE P29.6
Your
Chapter 29
Problems
485
FIGURE P29.7
-Vl!E=-3.17V
FIGURE P29.8
Figure P29.6 displays a DTL-to-PMOS translator.
Calculate the output voltage levels for input low
and high values corresponding to DTL. Use
Vl)(ON) = VB 1 (FA) = 0.7 V.
29.9
29.7
Show that the circuit of Figure P29.7 is a CMOSto-ECL translator.
Design a circuit that translates ECL to CMOS
levels.
29.10
29.8
Show that the circuit of Figure P29.8 is an ECL-to-
Design a circuit that translates CMOS to ECL
levels.
29.6
CMOS translator. Use VBl(ECL) = 0.75 V and
Vn(SAT) = 0.2 V.
BICMOS
not possess the required speed performance and
thus cannot be used.
On the other hand, ECL and TTL bipolar tech-
BiCMOS is a technology/logic family that combines
bipolar and CMOS devices into single integrated circuits. This relatively new technology (commercially
introduced in 1985) achieves higher speed, lower
power dissipation, and higher packing densities then
previously obtainable with either bipolar or CMOS
technologies individually. Note that CMOS has an
advantage over bipolar in the areas of lower power
dissipation, larger noise margins, and greater packing densities, while bipolar has advantages over
CMOS in faster switching speed and larger current
driving capability. Hence, by combining these two
technologies, BiCMOS offers the following advantages:
noln3ies prnvidP di3itc1I ln3ir rirrnits with high cur-
rent drive capability and hence high speed performance. However, these bipolar technologies
dissipate a great deal of power, the magnitude of
which is intolerable in some applications.
Various BiCMOS technologies have been developed in recent years by various semiconductor companies. Typical device cross-sections are shown in
Figure 30.1. In early BiCMOS technologies, bipolar
devices were combined with CMOS logic circuits.
However, performance was dominated by the individual characteristics of bipolar and CMOS devices.
Since these early approaches, two major areas of
BiCMOS have emerged. In one process, moderate
speed bipolar circuits are incorporated with high performance CMOS circuits. The selective use of bipolar
circuits on the chip leads to improved performance,
while the CMOS circuitry continues to provide low
power dissipation and large component density. In
the second process, BJTs arc optimized to produce
high performance circuitry. This technology is used
for large memo1y blocks in high-speed ECL circuits
and provides large density/low power mndom nccess
1ne111orics (RAMs) with the high speed performance
of ECL.
• Lower power dissipation than bipolar
• Improved speed in comparison to CMOS
• Larger current drive than CMOS
BiCMOS contributes these improvements, however
with the following disadvantages:
• Higher cost
• Larger fabrication cycle times, up to thirty
mask steps arc common (compared with ten
to twenty for straight bipolar or straight
CMOS)
30.1
REASON FOR BICMOS
BiCMOS technology refers to processes where bipolar and CMOS circuits are fabricated together on
a single chip. In this technology, either TTL or ECL
logic circuits are fabricated together with CMOS circuits. This merging of bipolar and CMOS devices has
been brought about because of the tradeoffs present
in each individual digital logic family. That is, CMOS
logic circuits provide high packing density and low
power dissipation, but the speed performance and
drive capability is nrnch less than that available from
bipolar logic families. In fact, in some communication systems and computer applications, CMOS does
30.2
BICMOS DEVICES
The active devices used in the BiCMOS logic family
arc NMOS and PMOS complementary MOSFETs,
along with NPN BJTs and lateral PNP BJTs (vertical
PNPs are also used in some technologies). Figure
30.1 shows the device cross sections, which consist
of buried twin well CMOS devices and BJTs. Recall
that a twin well structure is described in Chapter 16.
By using closely spaced N+ and p+ twin well structures, vc1y large packing densities arc achieved. The
486
30.2
487
NPN
PMOS
NMOS
BICMOS Devices
I,
(a)
Vertical PNP
s
E
P· substrate
(b)
lateral PNP
B
E
C
C
P• substrate
(c)
FIGURE 30.1
BiCMOS Device Cross Sections: (a) CMOS pair and vertical NPN, (b) Vertical PNP, (c) Lateral PNP
CMOS process uses a double polysilicon technique,
while the BJT process requires polysilicon emitters.
The major drawback in initiating BiCMOS was
that standard processing techniques for BJTs and
MOSFETs were totally incompatible. For example,
CMOS ICs generally begin with N-type silicon wafers, while BJTs begin with P-type silicon wafers.
Hence, conflicting device requirements exist in some
instances but some of the process steps for BJTs and
CMOS devices can be done simultaneously to reduce
the number of required steps overall. Usually the
processing steps of one technology are merged into
the process flow of the other technology using as
many identical processes for both, as possible.
J
488
Chapter 30/BICMOS
terminal through R 1, N 1 , and R2 will discharge the
load to ground and thus the output voltage is
0
~
1____: p
~1-~~
s~
VouT = 0 = Vm
30.4 BICMOS INVERTERS
WITH ACTIVE SHUNTS
A practical BiCMOS inverter with active shunts is
shown in Figure 30.3. The NPN BJTs each have a
tv10SFET in parallel vvith one junction. \A/hen either
of those MOSFETs is on, the corresponding BJT junction is shorted out. Hence, the BJTs connected in this
manner are referred to as gated diodes with an active
shunt.
Output High Voltage
FIGURE 30.2
Inverter with Resistive Shunt
30.3 BICMOS INVERTERS
WITH RESISTIVE SHUNTS
The basic BiCMOS inverter is shown in Figure 30.2.
This gate uses an ordinary CMOS inverter with a
resistive shunt bipolar driver configuration and has
full logic swing from O to VDD provided by the passive
resistors R1 and R2 . However, since this inverter uses
resistors, it is not practical for integrated circuits.
Output High Voltage
= VoH
To analyze the circuit, we first consider V1N to be low.
Under this condition, the PMOS P 1 is on and the
NMOS N 1 is cutoff. Hence, a highly conductive path
is provided by P 1 from V00 to the output terminal,
sourcing current to the base of the pull-up transistor
Qp and R1 . Since the NMOS N 1 is cutoff, the output
BJT Q 0 is also cutoff and the output voltage is high,
given by
Output Low Voltage
= VoL
When the input voltage is switched high, N 1 is on,
while P 1 is cutoff. Hence, N 1 provides sourcing current to the base of the output BJT Q 0 , which acts as
a pull-down BJT. The series path from the output
= VOH
To analyze the circuit, we first consider V1N to be low.
The NMOS transistors N 1 and N 3 are cutoff and P 1
is on, which forces N 2 on. Hence, V8 E,u is less than
one fmward active diode drop and the output transistor is off. With P 1 on, VDn is applied to the base
of Qr turning Qr on and sourcing a large current to
the output load. Hence, Qi, acts as a pull-up transistor and
Output Low Voltage - VoL
When the input switches high, P 1 goes off, N 1 and
N 3 turn on, while N 2 is also on, initially. The output
then discharges through N 3 and N 2 , with Qi, discharging through N 1 and Q 0 acts as a pull-down
transistor. When N 2 turns off, because the voltage
Vcs, 2 < VT, 2, the output voltage continues to decrease
until
VouT =
VoL
= VaE,o(FA)
Thus, the circuit of Figure 30.3 does not provide full
rail-to-rail swing, but falls short by two forward diode voltage drops.
30.5 BICMOS INVERTERS
WITH PARALLEL OUTPUT
CMOS INVERTER
Figure 30.4 displays the BiCMOS inverter that provides full rail-to-rail swing by using an additional
30.5
FIGURE 30.3
BICMOS Inverters with Parallel Output CMOS Inverter
Inverter with Active Shunt Configuration
Your
..L. C
T
our
L_
FIGURE 30.4
Full Rail BiCMOS Inverter
489
490
Chapter 3()/B!CdOS
pc1rallel CMOS inverter c1t the output. Note that this
is the only modification to the circuil of Figure 30.3.
The modified circuit provides full roil-to-rail swing.
Output High Voltage= Vcm
For the circuit of Figure 30.4, when the input goes
low, the operation is enhanced by the output Ov!OS
poir in that P 0 is on and acts JS J pull-up resistor
with the output voltage becoming
Output Low Voltage
= Vot
Similarly, for the input voltoge switched high, the
circuit of Figure 30.4 behaves in the same manner JS
Figure 30.3 except thc1t the CMOS inverter Jt the output pulls the output voltage down to ground. This
occurs since Nu is on and Jets JS il pull--down resistor. Thus, the output low voltage is
v(,1.
FIGURE 30.5
=
o
13iCMOS NANO Cate with Shunt Resistors
30.6
BICMOS NANO GATES
W 1TH KtSlSTl VE SHUNTS
Figure 30.5 displays a BiCMOS NAND gc1te with resistive shunts. The bc1sic operation of this gate is described by considering the MOSFETs first, realizing
that the BJTs perform JS output buffers.
Output High State
Considering either input V1~.,, or V 1~.B low (or both),
one (or both) of the NMOS transistors N., or N" is
off and the output BJT Q0 is cutoff. Meanwhile, at
the top of the circuit of Figme 30.5, one of the PMOS
transistors F'., or P 11 (or both) is active and a current
path exists from VDii to the bc1se of the pull-up BJT
Q1,. Thus, QI' turns on, behaving as an emitter follower and sourcing current to the load. Hence, the
output voltage Vrn:r goes high. Because of the resistor R 1, this value of the output high voltoge is
30.7
BICMOS NANO Gates with Active Shunts
491
Output Low State
Output High State
For the other output level of Figure 30.5, both inputs
are high. Then, the NMOS transistors NJ\ and N 6 are
on and supply base current to the output BJT Q0 .
Thus, Q0 is active and acts as a pull-down BJT sinking discharge current from the load. Meanwhile, with
the inputs high, the two PMOS transistors are cutoff
and thus the output voltage goes low. Because of the
resistor R2, this output low voltage is
Considering either input v,N,J\ or v,N,B low (or both),
one (or both) of the NMOS transistors NJ\ 1 or N,n is
off, while the corresponding PMOS transistor PA or
P 13 (or both) is on. Qp is then active and sources current to the output load pulling-up YouT• The output
high value, is
VouT
=0=
VoL
Output Low State
Hence, rail-to-rail logic swings are possible using
this resistive shunt BiCMOS circuit, but this is not
practical from an IC fabrication point of view.
For the low output state in Figure 30.6, both V,N,J\
and V,N,B are high. Then, NA 1, N 81 , NA 2 and NB 2 are
on, while P J\ and P 13 are off. The NMOS transistor
NoH aids in discharging the base of Qp but turns off
as the output voltage reduces and all the current
from NJ\ 2 and N 62 becomes base current to Q 0 with
the result that Q 0 acts as a pull-down transistor. This
provides advantageous switching speed at the ex-
BICMOS NAND GATES
WITH ACTIVE SHUNTS
30. 7
Figure 30.6 displays a practical Bi CMOS NAND gate,
which replaces the resistors with active MOSFETs.
t]p
I
f
B
~,v=j
'
'
..I..
T
FIGURE 30.6
Practical BiCMOS NANO Gate
492
Chapter 30/BICMOS
pc nsc of an in c rease in acti ve device co unt. The ou tput low voltage is
30.8
BICMOS DRIVERS
In BiCMOS logic circuits, basic drivers use BJTs to
drive output nodes . There are four basic types of
drivers used as shown in Figures 30.7 through 30.10.
In each circuit, MOSFETs are used as switches to
supply base current to the BJTs.
Common Collector NPN-PNP
BiCMOS Driver
Figu re 30. 7 shows the simplest BJT driver circuit that
utlizes NPN and PNP BJTs connected with a com mon collector terminal, which is the output terminal.
Considering V,N low, the input MOSFET N 1 is off and
P 1 is on . This forces Q:- -; to be cutoff and Q" to be in
saturation with
VouT
=
v l)O -
Vr:c, l'(SA T)
=
P,
II_ _
I
I
=
Gated Diode BiCMOS Driver
An improved driver is displayed in Figure 30.8. This
circuit configuration is called a gated diode driver, because each MOSFET acts as a switch between th e
base and collector of the BJTs. Wh en the switch is
on, the corresponding BJT becomes a diode.
Considering V1N low, N 1 is off and P 1 is on. Thu s,
Q 1, acts as a forward biased diode with large emitter
current ch arging the output load rapidly to
Vo 11
= ViJO - Vrn.l'(FA)
On the other hand, for V1:-.!
v [)/ /
When V1;s.: goes high, N 1 turns on and P 1 turns
off. This forces QI' off and Q ;s.: into saturation with
the output voltage
Vow
Note th at QN acts as J pull -down BJT and d isc harges
the output rapidly. However, the swing is close to,
but less than rail-to-rail. Also, since Q:-.! and Q" saturate, the switching speed from output low to high
is reduced . However, if QN and Qp are replaced with
Schottky clamped BJTs, this situation is considerably
improved. Furthern,ore, there is substantial power
dissipation, due to the drain current of N 1 that flows
for the output low state.
high, P 1 is off and
s:cc
N 1is on. Hence, QI' goes off and QN becomes a forward biased diode. The output voltage then discharges rapidly through Q:-.!· Thus, the output voltage
becomes
VccN(SA T) = Vu L
Yoo
Yoo
7
Q
r/~
I
I
~
P,
tl :-
i
-
VIN O -
-0
Yam
-·
{: Com
Q,,
"..,
N,
/
~
v. 0 _i
Yam
y:
Q,,
T
~I
N,
- - - - -- - - - - -
.
-:-
FIGURE 30.7
Basic Bi CMOS Driver
FIGURE 30.8
Gated Diode BiCMOS Driver
Com
30.8
BICMOS D1·ivers
493
YaUT
FIGURE 30.9
Emitter Follower Bi CMOS Driver
This gated diode driver shown in Figure 30.8 has a
speed improvement over that of Figure 30. 7 because
the BJTs do not go into saturation. However, the
2VrdFA).
swing is reduced to Vee
FIGURE 30.10
Modified Gated Diode BiCMOS Gate
Emitter Follower BiCMOS Driver
Another driver configuration to consider is that
shown in Figure 30.9 and referred to as an emitter
follower driver. Note that each MOSFET operates as
an inverter and these drive each BJT.
Considering Vw low in figure 30.9, Nr is off and
P1 is on. This forces QI\: on and Qp off, with a large
sourcing current available from QN. The output high
voltage increases rapidly to
Vour = Voo - Vllr,N(FA) = Vo11
On the other hand, for V1N high, P 1 is off and N 1
is on. Therefore, QN is off while Q1, is on, acting as
a pull-down BJT. A large discharge current reduces
Vm:-r rapidly as
VmlT = Vei:y(FA) = Vm
Hence, the logic swing is again VDD - 2V 8 dFA).
However, the circuit of Figure 30.9 has improved
base drive because the gate-source drive voltage is
larger. Another advantage is that the BJTs do not
saturate. Furthermore, with the source of P 1 connected to VDD along with the substrate, this circuit is
independent of the body effect, whereas the previous
two circuits are not. It should also be noted that pullup is provided by P 1and QN, while pull-down is provided by N 1 and Qp. Thus, larger currents and hence
faster switching speeds are provided. Another advantage for this circuit configuration is that each
MOSFET-BJT pair can be merged into a compact
structure that uses less chip area. This merging consists of using a common region for the base of the
BJT and the drain of the MOSFET.
Modified Gated Diode BiCMOS Driver
Figure 30.10 displays another BiCMOS driver that is
a modification of the gated diode configuration. The
circuit has two additional NMOS transistors N 2 and
N~ that provide a discharge path for the base current
of the output BJTs which are both NPNs. The gate
connection of N 2 ensures that the base of QN I is discharged, when the output goes high. On the other
hand, the gate of N 3 is connected to the input to
ensure that the base of QN 2 can discharge, when the
output switches low.
494
Chapter 30/BJCMOS
Q,,
Your= YoL
Q.
Your= YoH
.
'
V™
o----l :--··1
R,.
N,
I I
l
(a)
FIGURE 30.11
30.9
(b)
Collector-emitter Shunt Resistors to Achieve Full Swing: (a) V0 L 7 - = Vrn 1, (b) Your = Vol
FULL SWING METHODS
The BiCMOS drivers described in the previous section have reduced gate-source drive voltages due to
the partial logic swing. This logic swing can be increased to the full power supply voltage by adding
pull-up and pull-down shunt resistors between the
collector and emitter terminals of each BJT. The
speed of these circuits also is improved if the logic
swing is increased to the full power supply value.
Figure 30.1 la and b show the circuits for the output high and low states, respectively. After the BJT
Your= YoL
Q,,
Q.
Your= YoH
(a)
FIGURE 30.12
(b)
CMOS Shunt Network to Achieve Full Swing: (a) VocT = VoH,(b) Your= Vol
Chciptcr c\(l
Jt the output stops conducting, ;:idditional current
pc1sscs through the shunt resistor to pull-up the out
put ;:ill the way to V 1)1) or pull-down the output to
ground.
The rn;:iin disadvantage of this shunt resistance
technique is the use of resistors. However, the resistors can be replaced with a CMOS shunt network ;:is
shown in Figure 30.12. Note that when the input
l'rllblcms
495
MOSFET is on, the output \!OSFET with connected
gate is also on, providing a low resistance path to (or
from) the output terminal for ;:idditionc1I current.
Using the CMOS shunt network docs increase
the power dissipation, but only a small c1rnount.
However, the active shunt network provides rail-torail swing.
CHAPTER 30 PROBLEMS
30.1
For the full rail BiCMOS inverter shown in Figure
P30.1, analytically determine the critical voltages
V011 , Vo1., V11 ., V111, and V, 1• Use Vr, = 1 V, V 1r =
-1 V, k( = 20 µA/V 2 , k(. = 20 µA/V 2 , W ,/LcJ =
5, and Wp/L 1, = 2.5. Sketch the
30.2
Graphically determine the critirnl voltages V( ,11 ,
Vm, V11 , V111 , and V, 1 for the Bi CMOS inverter of
Problem 30.1.
30.3
For the practical BiCMOS NAND gate shown in
Figure P30.3, determine the critical voltages V, ll 1,
V,,1., V11 , V111, and V, 1• Use V,., = 1 V, V11 • =
-1 V, k( = 20 µA/V 2, k(. = 20 µA/V", VBI (FA) =
0.7 V, W,/L, = 5, and W 1./L 1, = 2.5. Sketch the
vrc.
vrc.
30.4
Determine the static and dynamic power dissipation of the BiCMOS inverter of Problem 30.3. Assume an operating frequency of v = 50 MHz and
a load capacitance of C1. = 0.08 pF.
Q
j~Q,
r 1:~-r
I
I
FIGURE P30.1
L_
J
l--0 Your
496
Chapter 30/BICMOS
C
LJ
I
i
I~
pB
I
FIGURE P30.3
V 00 = lOV
V 00 =5 V
l
P,
L___
I
I
Q,.
:-.1
'lVIN 0-----
I
(o.
P,
Your
~Yoo
VIN
I
f--------Q Your
Q,.
Q,
N,
N,
-·-~:i'j
-:-
FIGURE P30.5
FIGURE P30.7
Chapter 30
30.5
For the basic BiCMOS driver in Figure P30.5, determine the critical voltages V011 and Vu1.• Also,
show the method of finding V,L and V111 . Sketch
the VTC. Let V,HO(FA) = 0.7 V, V,llc(SAT) = 0.8 V,
and Vn/SAT) = 0.2 V.
30.6
Determine the static and dynamic power dissipated
in the BiCMOS inverter of Problem 30.5. Assume
an operating frequency of 11 = 25 MHz and a load
capacitance of Cr = 0.05 pF.
30.7
For the emitter follower BiCMOS driver of Figure
P30.7, calculate the critical voltages V011 and V0 L
and the logic swing. Let VBE(FA) = 0.7 V.
30.8
Determine the static power dissipation for the
driver of Problem 30. 7.
30.9
For the emitter follower BiCMOS driver of Figure
P30.9, calculate the critical voltages V0 " and V,,L
and the logic swing. Let VBJ;(FA) = 0.7 V.
30.10
Determine the static power dissipation for the
driver of Problem 30.9.
30.11
Repeat Problem 30. 9 for the driver circuit of Figure
30.12a and b.
30.12
Determine the static power dissipation for the
driver of Problem 30.11.
FIGURE P30.9
Problems
497
31
LATCHES AND
FLIP-FLOPS
In this chapter latches and flip-flops are introduced
and described in detail. These devices are basic
building blocks of sequential logic systems which are
systems for which the output voltage levels depend
upon past as well as present voltage levels. Hence,
these types of logic gates are memory elements. The
operation of sequential logic gates is such that when
new inputs are applied, the outputs respond according to the new inputs and the previous inputs. Upon
removal of the inputs, the outputs then remain unchanged.
Such memory elements are made up of the combinational logic gates NOT, AND, OR, NAND, and
NOR and feedback. Feedback is a term used to indicate that a portion of the output voltage is fed back
to the input. In addition to combinational logic gates,
CMOS latches and flip-flops are commonly constructed with the tri-state inverters and transmission
gates introduced in Chapter 25.
This chapter begins with definitions and descriptions of properties used to describe latches and flipflops. The basic digital memory element, the cross
coupled inverter latch, is then introduced and analyzed. The different types of latches and flip-flops
including RS, JK, and D types are then introduced.
Some sections of this chapter describe latch and
flip-flop configurations realized with complex logic
function AND-OR-invert gates. All sections, figures,
and examples that refer to circuit configurations realized with AOis are noted with the superscript AOI.
These sections can be skipped by the reader without
loss of continuity.
have either of two logic states, these devices are also
called bistable memory elements. The difference
between latches and flip-flops is as follows:
• a latch can change output states continuously
corresponding to input changes in any instant, whereas
• a flip-flop changes output states only at precise instants controlled by a train of equally
spaced pulses called a clock pulse train
The use of flip-flops insures that the system
components change at the correct instants. The clock
control terminal is an additional input that acts as an
enabling input only at precise instants of time.
Periodic Clock Signal
A typical square-wave clock signal is displayed in
Figure 31.1. Note that this signal is a precise string
of periodic voltage pulses that alternate between
logic level O and 1. Note further that the period of this
square wave is T and the frequency of the wave shape
is v. The relation between the period and frequency
is
1
v=T
The period T for the clock signal in Figure 31.1 is
indicated.
Transitions (Edges)
A clock pulse has two types of transitions (or ticks).
When a flip-flop is controlled by a clock pulse, either
one or the other of these transitions enable a change
in the outputs. These two types of transitions are
classified as follows:
31.1 BASIC DEFINITIONS FOR
SEQUENTIAL LOGIC GATES
1.
Single Cell Memory Elements
(Latches and Flip-Flops)
Single cell memory elements are called latches or
flip-flops. Since the output of a latch or flip-flop can
498
Low-to-high transition (L-to-H) which corresponds to a signal changing from the low logic
state to the high logic state as indicated in Figure
31.1. When this type of transition permits
change in the outputs, the logic gate is said to
be positive-edge triggered.
31.1
CLK
.
ltisic Ddinilions for SL'l]LIL'nli,1! Logic Catl's
499
high-to-low transitions (negative edge)
0
low-to-high transitions (positive edge)
FIGURE 31.1
2.
Typical Periodic Clock Signal
High-to-low transitions (H-to-L) which corresponds to a signal changing from the logic
high state to the logic low state as indicated in
Figure 31.1. When this type of transition permits
change in the outputs, the logic gate is said to
be negative-edge triggered.
Example 31.1
Triggered
Level-Triggered Versus Edge-
Consider the signal in Figure 31.2a to be a periodic
clock signal and let the signal in Figure 31.26 be the
input to three different types of latches or flip-flops,
whose outputs are shown in Figure 31.2c, d, and e.
Are the outputs in (c), (d), and (e) outputs of leveltriggered or edge-triggered latches or flip-flops?
Solution (Figure 31.2c) Level-Triggered Latch
The output signal in Figure 31.2c changes with the
input signal in (b) whenever the clock signal in (a)
is high. At times t 1, t2 , tJ, t 1,, t7, and t~ output (c) is
seen to follow the input in this manner. When the
clock signal goes low, the output signal (c) stores or
"latches" the input signal value until the next time
the clock signal goes high. Note that at time t0 the
input signal changes but the output signal in (c) does
not. At time t6 the clock signal again goes high and
the (c) output signal attains the logic value of the
input (b). The output signal shown in Figure 31.2c
demonstrates a latch that is triggered when the clock
is high and is referred to as a positive level-triggered
latch.
Solution (Figure 31.2d) Positive-Edge Triggered Flip-Flop The output signal in Figure 31.2d
is initially low. At time t the clock signal in (a) goes
low-to-high and the output signal in (d) attains the
logic value of the input signal in (b). At time 6,,, the
clock signal again goes low-to-high and the output
signal in (d) again attains the logic value of (b). Note
that the output signal in (d) never changes state
when the input signal changes state nor when the
clock goes high-to-low. Since this output signal
changes state only on the rising edge of the clock,
the signal of Figure 31.2d represents the output of a
1,
positive crfge-triggcrcrf .flip-flop.
Solution (Figure 31.2e) Negative Edge-Triggered Flip-Flop The output signal shown in Figure 31.2c is seen to change logic states only when
the clock signal goes high-to-low. The output signal
in Figure 31.2e is therefore the output of a negative
crfgc-triggcrcrf flip~f)op.
Types of Sequential Logic Circuits
There are two types of clocked digital logic systems.
These sequential logic circuits are called:
1.
synchronous logic circuits: those in which the
same clock is used to cause all logic variables to
change simultaneously, and
2.
asynchronous logic circuits: those that arc unclocked or portions of the system are either unclocked or run off independent clocks (i.e. all
variables are not clocked together)
500
Chapter 31/Latches and Flip-Flops
CLK
(a)
(b)
VLilVllL(V)
(c)
0
... t
(d)
0
---------,--►
t
(e)
0 ···---------t
•
Time Waveforms Demonstrating
Differences Between Level-triggered and Edge-triggered
Latches (Example 31.1): (a) Periodic clock signal,
FIGURE 31.2
(b) Input signal, (c) Level-triggered latch output,
(d) Positive edge-triggered flip-flop output, (e) Negative
edge-triggered flip-flop output
31.2
Latch and Flip-Flop Circuit
Symbol Convention
The symbol convention for latches and flip-flops has
been standardized. Figure 31.3 shows the specific circuit symbols used for latches and flip-flops.
31.2
Cross Coupled Inverters
501
CROSS COUPLED INVERTERS
The basic building block of digital memory circuits is
the positive feedback inverter loop shown in Figure
31.4a. This circuit consists of two inverters, with each
inverter output driving the input of the other inverter.
Inputs on Left and Outputs on Right
The circuit symbols for latches and flip-flops are usually drawn with the inputs on the left and the outputs
on the right. Figure 31.3a shows a latch symbol
where R and S are inputs and Q and Q are outputs.
Figure 31.36 shows another latch_yymbol where J,
EN, and Kare inputs and Q and Qare outputs.
Active Low Inputs
Active low latch inputs are drawn with inverting
bubbles. Figures 31.3c and d show latch symbols
where S, R, and Tare active low inputs. An inverting
bubble indicates that these three inputs are all active
low. This is similar to the gate symbol for a PMOS
transistor and output symbol for inverters, NAND
gates, and NOR gates.
Chip Clears and Presets
In integrated circuit design, it is routine to have an
input pin that clears or presets all latches simultaneously. This input is generally used after initial
power-up of the chip or during some other initialization routine. Latches and flip-flops that have
inputs connected to a chip-wide clear or preset have
these inputs drawn at the top or bottom of the symbol. Figures 31.3e and f show latch symbols with
CLEAR and PRESET inputs. These inputs are indicated at either the top or bottom of the symbol.
Edge-Triggered Inputs
Clock inputs to level-triggered latches are labeled the
same as any other inputs. Figures 31.3g and i show
positive level and negative level-triggered latches
with the clock inputs labeled as discussed previously.
Note that the negative level-triggered latch of Figure
31.3i has its active low input denoted by an inverting
bubble. Edge-triggered inputs of flip-flops are denoted with a wedge or triangle as shown in Figures
31.3h and j. The flip-flop of Figure 31.3h has a positive edge-triggered clock input. The negative edgetriggered flip-flop of Figure 31.3j has an inverting
bubble at the clock input.
Logic Analysis-Bistable
If the output of the inverter labeled I0 is in the output
low state, the input of the inverter labeled Ir is low.
The inverter I" will therefore be in the output high
state and the input of I0 will be driven high. With
the input of I0 high, then its output will be low. Thus,
I(.) in the output low state and IF in the output high
state is a stable circuit condition. This stable condition is illustrated in Figure 31.46 with Q = 0 and
Q = 1.
Likewise, if the inverter I0 is in the output high
state then the input of IF is high. With the input of
I" high, IF is in the output low state. With the output
of IF and the input of I0 low, I0 is driven into its
output high state. Thus Q = 1 and Q = 0 is also a
stable condition as illustrated in Figure 31.4c.
Considering this qualitative logic state analysis,
the positive feedback inverter loop of Figure 31.4 has
two stable states as depicted in Figure 31.46 and c.
Circuits with two stable states are referred to as bistable.
Cross Coupled Inverters
The positive feedback inverter loop of Figure 31.4a is
redrawn in Figure 31.4d with both inverters facing
the same direction. Drawn in this manner, the inverter loop is referred to as a cross coupled inverter
latch.
Voltage Analysis
To provide further understanding of the previous
logic analysis, consider the cross coupled inverter
latch redrawn in Figure 31.Sa without the feedback
connection. This configuration indicates two cascaded inverters with a single input and a single output. The voltage transfer characteristic for the noninverting output voltage 0/0 versus V1N) is plotted in
Figure 31.Sb. Now consider the output VO of the second inverter I0 to be fed back to the input of the first
inverter IF as in Figure 31.Sc. Under this condition,
502
Chapter 31/ Latches and Flip -Flo ps
RandS
are inputs
--F7-
QandQ
are outputs
- ~
(a)
SandR
are inverting
inputs
J, EN, and K
are inputs
D
(b)
T is an inverting
input and CLK
is a noninverting input
s~ '
R- ~
R CLEAR Q _
- - - ~ C LQK
- ~
-
~
S PRESETQ
(t)
(e)
~
positive edge-triggered
-
CLOCK~
~
-
C L O C K S ~-(h)
(g)
-to7-
negative level-triggered
T~I
(d)
(c)
positive level-triggered
QandQ
are outputs
-
CLOCK ~
-
(i)
FIGURE 31.3 Latch and Flip-flop Symbol Conventions:
(a), (b) Inputs are generally on the left and outputs on
the right, (c), (d) Active low inputs are drawn with
inverting bubbles, (e), (f) Clears and presets that are
negative edge triggered
- -~
C L O C K l _ ~(j)
wired to chip-reset are drawn at the top and bottom,
(g) Positive level-trigge red latch, (h) Positive edgetriggered flip-fl op, (i) Negative level-triggered flip-flop,
(j) Negative edge- tri gge red flip-flop
31.2
Cross Coupled Inverters
503
input ofir driven
by output
ofI0.
,.,,
(a}
(b)
(c)
(d)
FIGURE 31.4 Basic Digital Memory Elements: A cross
coupled inverter latch: (a) Dual inverter positive feedback
loop, (b) IQ in output low state, IF in output
high state, (c) IQ in output high state, IF in output low
state, (d) Positive feedback inverter loop drawn as cross
coupled inverters
504
Chapter 31/Latches and Flip-Flops
noninverting
VQ
VTC~
low
stable
point
(a)
, tI .
!
VOL
i
(b)
1 -o v. - - - - - - - I
V"' = VQ
~-
\
~
~~~~----vv~-~
J/"
---
during static operation V• and
VQ are each at one of the two
stable points found in (b)
output of second inverter is fed back to input of frrst inverter
(c)
FIGURE 31.5 Analysis of Cross Coupled Inverter
Latch: (a) Two cascaded inverters, (b) Voltage transfer
characteristic V0 versus V11\: superimposed over V0 = V11\:
gives two stable solutions, (c) Output V,J fed back to V11\:
gives positive feedback inverter loop of Figure 31.4
the straight line for V1;s1 = V0. must also be satisfied
and this line is also plotted in Figure 31.56. The three
intersection points of the two curves indicate that the
circuit of Figure 31.56 can statically operate at any of
these intersections. However, the middle intersection point is unstable and even the most minor
anomaly or circuit noise forces the inverter loop out
of that state and into one of the other states. Hence,
the inverter loop of Figure 31.Sc has only two stable
operating states.
The basic cross coupled inverter latch presented
in this section and Figure 31.4d is used extensively
in the following sections. This element is the basis
for latches and flip-flops.
31.3
RESET-SET (RS) LATCH
NOR Realized RS Latch
The first practical digital latch is displayed in Figure
31.6a. This circuit provides two additional inputs to
the basic cross coupled inverter latch of the previous
section and Figure 31.4d by replacing the inverters
31_3
R o - - - - ~ ~ R+_Q
~ - - ; - -0
Q
J
I
----~====--------,
~--
Q
s
s
□
R
Q
Q
state
0 0
0 1
1 0
Q
Q
unchanged
0
1
1
reset
0
set
1 1
0
0
not used
505
(c)
(b)
(a)
Reset-Set (RS) Latch
Qgoeslow
forR high
R
►
t
►
t
----------------------------------------------- ►
t
s
____......._ _ _ _ _
0------Q
Q
--..!------------------------------------------- -'-'......- - - - - ! ,
t,
(d)
FIGURE 31.6 RS Latch (NOR realization): (a) Cross coupled NOR gates, (b) Circuit symbol, (c) Truth table, (d) Time
waveforms demonstrating operation
with two-input NOR gates. The feedback connection
of the two NOR gates represents one implementation of the memory element called a reset-set latch,
or RS latch. Each NOR gate output is fed back to
one input of the other NOR gate and the remaining
NOR gate inputs are the two inputs to this RS latch.
The outputs are defined as Q and Q, the inverses of
each other. The inputs are defined as R and S which
stand for reset and set, respectively. The reset condition of R = 1 and S = 0 corresponds to Q being reset
506
Chapter 31/Latches and Flip-Flops
to 0, where;:is the set conrlition of R = 0 and S = 1
corresponds to Q being set to 1.
Figure 31.6c displays the truth table for the RS
latch. Note that the lilst row docs not allow Q and
Q to be inverses. Hence, this row cannot be used in
normal latching applications. To verify the rows of
the truth table, we analyze the circuit of Figure 31.6
using general logic analysis. The Q output of the top
NOR gate is
Q=R+Q
while the Q output of the bottom NOR gate is given
by
Q=S+Q
These output expressions are referred to as the
characteristic equations for this latch. The following
subsections verify the operation of the RS latch. The
time waveforms in Figure 31.6d illustrate the reset,
set, and latched conditions of this dynamic gcite.
Verification of Stable Condition: S = R = O
Consider the first row of the truth table, where R =
S = 0. From the characteristic equations, we h;:ive
Q= R +
Q= 0 + Q=
(Q) = Q
and
Verification of Set Condition: S
= 1 and R = 0
Next consider the third row with S = 1 zmd R = 0.
First, we obt;:iin Q, since S = 1 ;:is follows:
Q=1+Q=0
;:ind then
Q = 0 + Q = (Q) = 1
Note th;:it these outputs correspond to the set condition.
The set condition is demonstrated ;:it times t 1 and
tc, in Figure 31.6d. A previously low Q output is seen
to go high when the S input is high.
Forbidden Input Condition: S
= 1 and R = 1
Finally, considering R = S = 1, the characteristic
equations predict the O level for both the outputs as
follows:
Q=1+Q=0
;:ind
Q=1+Q=0
which mc;:ins that the two outputs are equal and are
not inverses for these inputs (R = S = 1) contra1y to
our definition. This inconsistency is eliminated by
never allowing the input condition R = S = 1.
NAND Realized RS Latch
Q=0+Q=Q
Thus, the condition R = S = 0 provides outputs that
are unchanged as indicated in the truth table.
Verification of Reset Condition:
S = 0 and R = 1
To verify the second row of the truth table for S = 0
and R = 1, first note that this is the reset condition.
Substitution into the equation for Q and Q yields
Q=1+Q=0
and thus
Q=0+Q=Q=1
which does indeed correspond to the reset condition.
The reset condition is demonstrated in Figure
31.6d, at times t:1 and t7 . At these times the input R
is mon,entarily brought high and the previously high
Q output is seen to latch the low logic state.
The RS l;:itch of Figure 31.6a was constructed by replacing the inverters in the cross coupled inverter
latch with multi-input NOR gates. Figure 31.7a
shows an alternate RS latch configuration where the
cross coupled NOR gates are replaced with cross
coupled NAND gates. For this latch, the inputs are
active low, as labeled at the schematic and symbol
inputs using S and R. That is, the latch encounters
the set condition when the S input is brought low (S
is high) and the latch is in the reset condition when
R is brought low (R is high). The circuit symbol for
this gate is shown in Figure 31.76. Inverting bubbles
arc used to represent the active low inputs.
NAND Realized RS Latch Truth Table
The truth table corresponding to the NAND realized
RS latch is shown in Figure 31. 7c. For this gate, the
unchanged output state occurs when both inputs arc
high and the unused state is when both inputs are
low. Time waveforms demonstrating operation of
31.3
Reset-Set (RS) Latch
Q
Q
0
:.~:.-
1
'1
Q
R
R
✓---
state
unchanged
1
0
1
reset
set
not used
(c)
(b)
(a)
Q
a
507
Qgoeslow
forRlow
1
0
... -'. ............................... ;.. ,;<;.,.,.,,-.';,, •. :c.,;..,, ... ,...............
s
+,...;.,+ ......................................C~-----r----t--,......---,,,.. t
t,
¼
1
0
Q
1
0
Q
l
0
................._ . . . , . ._ _ _ _ _ _!_,_......
11
i,...;;.-----.-·--------·---"""►
t
½
t..,
(ii)
FIGURE 31.7 RS Latch (NAND Realization): (a) Cross couples NAND gates, (b) Circuit symbol, (c) Truth table, (d)
Time waveforms demonstrating operation
508
Chapter 31/Latchcs and Flip-Flops
Q
R,
FIGURE 31.8 Cross Coupled NOR RS Latch with
Multiple Reset and Set Inputs
the cross coupled NANO RS latch are shown in Figure 31.7d. The truth table in Figure 31.7c can be easily verified in a manner similar to that presented for
the cross coupled NOR RS latch and is left as a
homework problem at the end of the chapter.
Additional Inputs
Additional reset and set inputs can be added to the
cross coupled NOR and NANO RS latches by using
NOR or NAND gates with more than two inputs.
Figure 31.8 shows a NOR RS latch with two reset
inputs and three set inputs. This gate operates identically to the basic RS latch presented in Figure 31.6a
with the exception that it can be reset with either of
the reset inputs and set with any of the set inputs.
Having a reset and a set input high simultaneously
is unused and should be avoided because this would
provide inconsistent outputs.
Example 31.2
NAND Realized RS Latch
with Multiple Set and Reset Inputs
Design a RS latch that has two active set inputs and
three active low reset inputs.
Solution Since the RS latch requested should have
active low inputs, it should be designed with cross
coupled NAND gates. To achieve two set inputs and
three reset inputs, use three and four input NAND
gates for the Q and Q outputs, respectively. Figure
31.9 shows such an RS latch.
FIGURE 31.9 Cross Coupled NAND RS Latch with
Multiple Set and Reset Inputs for Example 31.2
f
T'1ps, T nc
. k s,
and Gimmicks
AO!
Complex Logic AND-OR-Invert Gates
The following sections will present progressively complex digital latches designed by expanding the cross coupled NOR and NANO
RS latches. Son,e of these latches can be realized using complex AND-OR-invert logic
gates. Figure 31.10 shows circuit symbols for
three such logic gates along with the truth tables that tabulate their static operating conditions. The three logic gates represent the logic
functions
F =AB+ C
F =AB+ CD
and
F =A+ BC+ D
Operation and realization of these logic functions in TTL, ECL, NMOS, and CMOS is covered extensively in Chapters 10, 15, 22, and 24.
The circuit symbols are presented here only for
brief review and any reference to the complex
logic gates of previous chapters in the following
sections can be skipped without loss of continuity.
3'1 .3
509
Reset-Set 0-:S) Latch
A B C FAm=AB+C
1
0 0 0
A_-cJoo
B -·-
0
0
1
1
0
0
1
1
0
0
1
1
1
1
F=AB+C
C
1
0
1
0
1
0
1
0
1
0
1
0
0
0
(a)
---
A B C D FAm=AB + CD
1
0 0 0 0
0 0
B
--
C
D-
-
-
0
0
-0
0
0
0
---
- F=AB+CD
0
0
1
1
1
1
1
0
1
0
1
0
1
0
1
1
0
0
1
1
1
1
0
--··----·1
1
1
0
A B C D FAOI =AB+ CD
1
1
1
1
1
1
1
1
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
------
1
1
1
0
0
0
0
0
(b)
A B C D FAm=A+BC+D
AC
D
-- F=A+BC+D
0 0 0 0
0 0 0 1
0 0 1 0
0 0 · -1- 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
--
---
-
--
1
0
1
0 -1
0
0
0
---
A B C D FAOI =A+ BC+ D
1
1
1
1
1
1
1
1
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
--
-
0
0
0
0
0
0
0
0
(c)
Aoi FIGURE 31.10
Complex Logic AND-OR-invert Gates Useful for Latch Design: (a) F = NOT[(A AND B) OR CJ,
(b) F = NOT[(A AND B) OR (C AND D)], (c) F = NOT[A OR (BAND C) ORD]
510
Chapter 31/Litchcs ,md Flip-Flops
RS latch
steering gates
gatedR and S
are transferred to
latch when EN == 1
(b)
(a)
cross-coupled AND-OR-invert realization
EN
0
1
1
1
1
--
s
R
X
0
0
1
1
X
0
1
0
1
-----
Q
Q
~
·~
Q
0
1
0
-
state
Q
Q
Q
~-----
1
0
0
unchanged
unchanged
reset
set
not used
----·~-~
ENO-I~
R and S inputs
are active only
when EN is high
s
(c)
AO!
... ___
R
(d)
RS latch
steering gates
.........~,
~..., ...... ,,.,,.
---
---~
all NAND realization
......
w6=1
Q
(e)
FIGURE 31.11 Gated RS Latch: (a) Cross coupled
NOR gates with steering AND gates, (b) Circuit symbol,
(c) Tnith table, ' 10' (d) Cross coupled AND-OR-invert
realization, (e) All NANO realization
31.4
CatedRSL1tchl?s
511
R
l
O·
s
l
0
EN
4
1
O·
t,
Q
Qgooskiw
+
when, R goes high
and EN is high
1.
O·
~~.... '.
''
•· ..·
'
.··.
Q goes high . •
when S goes hig
and EN is high •·;.,..;...............- - - - - -
t,
(t)
FIGURE 31.11 (continued)
31.4
(f) Time waveforms illustrating operation
GATED RS LATCHES
A slight modification of the RS latch in Figure 31.6
provides an EN enable input as shown in Figure
31.11a. Such an RS latch requires two additional
AND gates. The latch is referred to as a gated RS
latch or level-triggered latch. The outputs of these
AND gates are labeled R' and S'. The circuit symbol
for this latch with the additional EN input is shown
in Figure 31.llb.
Disabled Condition (EN = o)
To analyze the circuit, first consider EN = 0. Under
this condition, both AND gates have a low input and
low outputs. Hence, the R' and S' inputs to the NOR
512
Chc1ptcr 31/LJtchcs c1nd Flif•-Flllf•S
gotes ore zero rcgordless of the stotes of Sand R ond
couse no chongc in Q and Q, os described in the
previous section.
Enabled Condition (EN= 1)
Next consider EN = 1. Under this condition, the outputs of the AND gates are
R' =RAND 1
=
R
and
S' =SAND 1 = S
ond the circuit operates as the cross coupled NOR
RS latch of the previous section. With EN high, the
Q output will go low if R' = R is high and high if
S' = S is high. If both R and S are low then the
outputs will not cl1(mge state and both R and S inputs high simultaneously should be avoided.
Truth Table and Time Waveforms
The truth table for this latch is shown in Figure
31.11c. Note that for EN low, the output remained
unchanged regardless of the states of R and S. With
EN high, the truth table resembles the truth table for
the simple cross coupled NOR latch of Figure 31.6.
Time waveforms illustrating operation of this
gated latch arc shown in Figure 31.1 lf. At time t 1,
the S input is brought high. Since the EN input is
low, the output does not change state. At time t2 , EN
is brought high, while S is still high and the output
Q is set. At time t; the R input is brought high, but
the output does not change state since the EN input
is low. When the EN input goes high at time t,,, the
output Q is reset. At time tc1 EN is brought high,
while both Rand S are low, so the output state remains unchanged. While EN is high, S and R are
individually brought high (while the other is low) at
times t]I) and t 12 • The output is set and reset, respectively, at these times.
Cross Coupled
AND-OR-Invert Realization
Am
The gated RS latch can be realized with cross coupled
AND-OR-invert gates as shown in Figure 31.11d.
AND-OR-invert gates are easily realized using TTL,
ECL, NMOS, and CMOS logic families as discussed
in Chapters 10, 15, 22, and 24, respectively.
All NAND Gate Realization
In the previous section, RS latches are designed using cross coupled NAND gates. The cross coupled
NAND RS latches of Figure 31.7a have active low S
and R inputs. If the AND gates of Figure 31.11a arc
replaced with NAND gates, the NAND outputs become S' and R'. Then, active low S' and R' connected to the Sand R inputs of cross coupled NAND
gates provide an RS latch with only NAND gates.
Figure 31 .'I 1 e shows such an all NAND RS latch with
enable input. Note that the inputs are now active
high Rand S.
Example 31.3 Gated RS Latches
with Dual Enable Inputs
Design a gated RS latch that has active reset and set
inputs only when two enable inputs are high.
Solution (All NAND Realization) In Figure
31.1 la, the EN input must be high in order for the
steering AND gates to transfer the gated R and S
inputs to the S' and R' internal nodes. Since the output of an AND gate is only high when all inputs are
high, additional enabling inputs can be added by
simple using AND gates with more than two inputs.
All enable inputs must be connected to both steering
gates. This would also hold true for the all NANO
realization in Figure 31.lle. Thus, Figure 31.12a
shows an all NAND gated RS latch with two enabling inputs named ENl and EN2. This latch remains in a steady latched condition unless both ENl
and EN2 are high and either R or S is high individually.
Solution (AND-OR-Invert Realization) An
alternate configuration is the cross coupled ANDOR-invert gate shown in Figure 31.126. Again, both
enabling inputs go to both input gates and the Rand
S inputs are active only if both ENl and EN2 are
high.
The latches in Figure 31.12a and bare functionally identical and the circuit symbol for these latches
is shown in Figure 31.12c.
Aoi
Clocked RS Latch
The RS latches presented in this section are often
used in digital circuits containing chip-wide periodic
31:i
Catt,d RS Litchcs with ;\s1'nchrnnuus CiL'c1r and l'rcsl't
513
all NAND realization
Q
gated R and S are transferred to
latch when ENI and EN2 are high
Q
(a)
cross-coupled AND-OR-invert realization
R. '.)---
ENI
O
EN2 o
H
(1
Q
-- R
- EN1
- EN2
Q-
-s
i ·~
II
AOI
(b)
(c)
FIGURE 31.12 Enabled RS Latches with Dual Enabling Inputs for Example 31,3: (a) AJI NANO realizc1tion, ,,ni (b)
Cross coupled AND-OR-invert latches, (c) Circuit symbol
clock signals such as shown in Figure 31,L The enable input will often be connected to such a clock
signal. Thus, these enabled latches arc sometimes referred to as clocked latches,
31.5 GATED RS LATCHES
WITH ASYNCHRONOUS CLEAR
AND PRESET
The inputs of the RS latches presented in section 31,3
and Figures 31,6 through 31,9 are active at all instances of tinw. That is, the outputs of these latches
respond to the inputs within the margin of the propagation delays and the inputs are not clocked simultaneously. The previous section introduced RS
latches with gated reset and set inputs. Figure 31.13J
shows an RS latch with both gated and non-gated
inputs. The inputs R and S are gated through the
steering AND gates but the CLEAR and PRESET
inputs arc connected directly to the cross coupled
NOR gates. The Rand S inputs arc only active when
EN is high, but the CLEAR and PRESET inputs arc
always active regardless of the state of EN. The nongated CLEAR and PRESET inputs Jre referred to as
asyncilronous inputs. The circuit symbol for this latch
is shown in Figure 31.136.
Truth Table
Figure 31.13c tabulates the operational states of this
latch. The table shows that the R and S inputs arc
active when the EN input is high and that the
CLEAR and PRESET inputs are Jctive regardless of
the state of EN.
514
Chapter 31/Latches and Flip-Flops
gated R and S are transferred
lo latch when EN = 1
CLEAR
asynchronous CLEAR is active
regardless of state of EN
R CLEAR Q ~-
EN
S PRESETQ -
asynchronous PRESET is
active regardless of state of EN
PRESET
(a)
(b)
cross-coupled AND-OR-invert realization
CLEAR
EN
s
9
Q
Q
state
0
Q
a
unchanged
R PRESET CLEAR
1
0 0
1
1
0
1
0
0
0
1
reset
1 0
0
0
0
set
1
0
1
X X
X X
X X
X X
0
0
1
0
0
0
0
Q
a
not used
unchanged
0
1
0
1
0
1
0
0
X
X
X
1
0
1
1
\
0
1
Q
clear
preset
Q
not used
PRESET and CLEAR are active regardless of state of EN
PRESET
(c)
AOI
(d)
FIGURE 31.13 Enabled RS Latch (synchronous Rand
S inputs) with Asynchronous CLEAR and PRESET
Inputs: (a) Additional inputs are added to cross coupled
latch and are active regardless of state of EN, (b) Circuit
symbol, (c) Truth table, /\oi (d) Cross coupled AND-ORinvert realization
Cross Coupled
AND-OR-Invert Realization
gate used in this circuit is shown in Figure 31.lOc
along with its truth table.
AOI
The cross coupled AND-OR-invert realization of the
gated RS latch with asynchronous CLEAR and PRESET is shown in Figure 31.13d. The complex logic
All NANO Realization
The gated RS latch with asynchronous CLEAR and
PRESET can be realized using only NAND gates by
31.6
Edge-Triggered Master-Slave RS Flip-Flops
515
all NAND realization
asynchronous PRESET is active
regardless of state of EN
PRESET
()
PRESET
Q
EN
-
s
CLEAR Q
Q
R
asynchronous CLEAR is
active regardless of state of EN
CLEAR.
CLEAR
(a)
EN
s
(b)
R PRESET CLEAR
1
0 0
1
1
1
0
X
X X
X
X X
X
X
X X
X X
1
1 0
1 1
1
1
1
1
1
1
0
0
Q
state
Q
-
Q
unchanged
1
0
reset
set
0
not used
unchanged
1
Q
1
1
1
1
0
1
0
1
0
Q
Q
0
1
1
clear
0
preset
0
0
not used
Cl
S and R inputs are
active when EN is high
PRESET and CLEAR inputs are
active regardless of state of EN
(c)
FIGURE 31.14 All NAND Realization of Enabled RS
Latch with Asynchronous PRESET and CLEAR inputs:
(b) Circuit symbol indicating active low PRESET and
CLEAR, (c) Truth table
(a) Circuit with active low PRESET and CLEAR,
adding inputs to the cross coupled NAND latch inside the circuit of Figure 31.lle. Figure 31.14a shows
such a circuit. Note that unlike the circuit of Figure
31.13, this circuit has active low asynchronous
CLEAR and PRESET inputs. (Recall that the basic
cross coupled NAND RS latch of Figure 31.7 has active low reset and set inputs.) The circuit symbol
shown in Figure 31.14b indicates the active low inputs with inverting bubbles.
The truth table for all NAND gated RS latch with
active low asynchronous inputs CLEAR and
PRESET is shown in Figure 31.14c. It is indicated
that the S and R inputs are active only when EN is
high and the CLEAR and PRESET inputs are active
regardless of the state of EN. Figure 31.14d shows
time waveforms that exemplify operation of the latch
in Figure 31.14a.
31.6 EDGE-TRIGGERED MASTERSLA VE RS FLIP-FLOPS
Negative Edge-Triggered RS
Master-Slave Flip-Flops
The RS latches presented in the previous sections
were all level triggered memory elements. That is,
the transfer of the inputs to the output was depen-
516
Chapter 31/Latchcs and Flip-Flops
(d)
FIGURE 31.14 (continued)
(d) Time waveforms describing operation
dent on the voltage level of the clock, the level being
either the logic high voltage or logic low voltage. Figure 31.15a is the first in a series of memory elements
to be presented in which the effect of the input is
transferred to the output at the instant the clock
changes state.
This circuit is made up of two cascaded gated RS
latches (introduced in Figure 31.lle and discussed in
section 31.4). The first stage is enabled, when the
CLK signal is high. The second stage is enabled
when CLK is low or CLK is high. Using two stages
has the effect of transferring the latched memory
31,6
Edge-Triggered Master-Slavc> RS Flip-Flops
517
slave (enabled wh,m CLK is low)
master (enabled when CLK is high)
(a)
(b)
CLK s R
0
X X
1
X )(
s X X
0 0
L
0 1
L
1 0
L
1 1
L
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
0
1
1
0
1
1
outputs
unchanged
state of master latch is
transferred to slave latch
on falling edge of CLK
(c)
FIGURE 31.15 Negative Edge-triggered RS Masterslave flip-flop: (a) Logic schematic, (b) Circuit symbol,
(c) Truth table indicating outputs change state on falling
edgc> of clock
state of the first stage to the second stage when CLK
undergoes a high-to-low transition. Thus, the outputs are triggered during a high-to-low CLK edge,
with an edge-trigger wedge or triangle and an inverting bubble to symbolize a negative edge-triggered
flip-flop.
Master-Slave, Edge-Triggered, Flip-Flop
Truth Table and Time Waveforms
Dual latch configurations where the two latches are
triggered at opposite clock levels are referred to as
flip-flops. The first latch is referred to as the master
latch and the second is referred to as the slave latch.
Since the outputs are triggered by a clock transition,
this flip-flop is referred to as being edge-triggered,
Since the outputs for this specific flip-flop are dependent upon the output high-to-low transition, it
is a negative edge-triggered flip-flop. Figure 31, 15b
shows the circuit symbol for this negative edge-triggered circuit. Note that the CLK input is indicated
The operational states for the negative edgetriggered master-slave RS flip-flop are shown in the
truth table of Figure 31.15c. This table indicates that
during the clock high-to-low transition, the operation of this flip-flop is the same as the simple cross
coupled RS latches of Figures 31.6 and 7. During the
low-to-high CLK transition and CLK at either
steady state, the outputs remain unaffected regardless of the states of the R and S inputs.
The time waveforms of Figure 31. 15d clearly
demonstrate the flip-flop operation. During the neg-
518
Chapter 31/Latchcs and Flip-Flops
R
1
s
1
0 -l...-...+'0'-=++..;;___..;;___'-'-~:.1-------.......;-..;..._.........,._ _ _ _ _
►·
t
l
CLK
1
0
·---···••f
Qu=S,
l J,...
7
½
:
~1
l
;
:
.
'
:'
I _ _ _.........,_~..-~-~-----------....--;-,......--.► t
0 _...,
0:=Rs
4
,
l
J --~'-----i'-~i
I;;
(d)
FIGURE 31.15 (continued)
(d) Time waveforms exemplifying flip-flop operation
31.6
Edge-Triggered l'vli.1sler-Sl:wc RS Fli~1-flops
519
slave (enabled when CLK is high)
master (enabled when CLK is low)
s
R
(a)
CLK
=I
Q1=
0
0
1
=>
i~
=Pl
L
--~
(b)
s
s
s
s
s
R
Q
Q
X X
X X
X X
Q
Q
Q
a
0 0
0 1
1 0
1 1
-
Q
Q
a
--~
0
1
1
1
0
·-
a
state of master latch is
transferred to slave latch
on rising edge of CLK
1
(c)
FIGURE 31.16 Positive Edge-triggered RS l'v1Jstcrsli.1ve Flip-flow: (a) Logic schematic, (b) Circuit symbol,
(c) Truth table indici.lting outputs change state on rising
edge of clock
ative edges of CLK at times t 3 and t7 the states of
the S and R inputs set and reset the Q output, respectively.
The flip-flop of Figure 31.16 is therefore positive
edge-triggered and the effect of the inputs is transferred to the outputs during the clock low-to-high
transition. The flip-flop circuit symbol, truth table,
and time waveforms exemplifying operation are
shown in Figures 31.66, c, and d.
Positive Edge-Trigger RS Master-Slave
Flip-Flops
The master-slave flip-flop of Figure 31.15 can easily
be modified to trigger the outputs on the rising edge
of the CLK input signal. Figure 31.6a displays an RS
flip-flop where the master latch is gated when CLK
is low and the slave latch is gated when CLK is high.
Asynchronous Clears and Presets
Asynchronous (non-gated) clear and preset inputs
can easily be added to the RS master-slave flip-flops
of Figures 31.15 and 16. In Figure 31.14a active low
520
Chapter 31/Latchcs and Flip-Flops
s
1
•
o-----
1
Q
(d)
FIGURE 31.16 (continued) (d) Time waveforms illustrating latch operation
asynchronous CLEAR and PRESET inputs are
added to the gated RS latch by the inclusion of additional inputs to the cross coupled NAND latch. The
same principle is used in Figure 31.17a which shows
an RS flip-flop with additional inputs added to the
cross coupled NAND latches of both the master and
slave latches. Common PRESET and CLEAR inputs
are connected to the additional inputs of both the
master and slave latches. The Q and Q flip-flop outputs are effected by these asynchronous inputs re-
31.6
Edge-Triggered Mastcr-Sbvc RS Flip-Flops
521
asynchronous PRESET goes
to master and slave and is
active regardless of state of CLK
s
Q
Q
R
CLEAR
asynchronous CLEAR goes
to master and slave and is
active regardless of state of CLK
CLK c·, .......... ;.......................................................................................................................................................,
(a)
CLK
PRESET
R PRESET Q _
..
S CLEAR Q ~
s
s
s
s
X
X
X
CLEAR
X
s
---
R PRESET CLEAR
0
0
1
1
X
0
1
0
1
X
X X
X X
X X
1
1
1
1
1
1
1
1
1
1
0
0
1
0
1
0
-
Q
Q
Q
Q
0
1
0
1
0
0
Q
Q
0
1
0
1
0
state of master latch is
transferred to slave latch
on rising edge of CLK
PRESET and CLEAR
inputs are active regardless
of state of CLK
0
(c)
(b)
FIGURE 31.17 Positive Edge-triggered Master-slave
RS Flip-flop with Active Low Asynchronous CLEAR and
PRESET: (a) Logic schematic, (b) Circuit symbol
indicating active low inputs with inverting bubbles,
(c) Truth table
gardless of the level or edge state of CLK. The circuit
symbol and truth table for this flip-flop with asynchronous inputs are shown in Figures 31.176 and c.
Time waveforms demonstrating operation of the
flip-flop of Figure 31.17 are shown in Figure 31.17d.
Aoi
Example 31.4 RS Flip-Flop with Cross
Coupled AND-OR-Invert Gates
Design a positive edge-triggered RS master-slave
flip-flop with asynchronous clear and preset inputs
using cross coupled AND-OR-invert latches.
522
Chapter 31/Latchcs and Flip-Flops
CLEAR
l
*
----....J--------- ► t
'-----'----t
(}
·· ►
t
---~--- -----',!-----------',---·►
t
- - -....... ·············--····--·--···-·--+----------1 ....................
~
O·
~
!
t10
~
ti.,
(d)
FIGURE 31.17 (continued)
(d) Time waveforms demonstrating operation
Solution Note that Figure 31.13d displays a cross
coupled AND-OR-invert gated RS latch with asynchronous CLEAR and PRESET inputs. Figure
31.18a shows two of these latches cascaded to form
a master-slave flip-flop. The master latch is enabled
when CLK is low and the slave when CLK is high.
Thus, the master-slave flip-flop of Figure 31.18a is
positive edge-triggered. The asynchronous CLEAR
and PRESET inputs are connected to both the master and slave latch. Looking back to the master-slave
flip-flops of Figures 31.15, 31.16, and 31.17, the Q
and Q outputs of the master are connected to the S
and R inputs of the slave, respectively. Examining the
AND-OR-invert realized RS latch of Figure 31.13d,
the R and S inputs are connected to the gates with
the Q and Q outputs, respectively. Thus, the con-
31.(,
Edge-Triggered Master-Slave RS Flip-Flops
523
asynchronous CLEAR goes
to master and slave and is
active regardless of state of CLK
CLEAR
asynchronous PRESET goes
to master and slave and is
active regardless of state of CLK
(a)
CLK
R CLEAR Q __
S PRESETQ.
s
R PRESET CLEAR
s
s
s
s
0 0
0 1
1 0
X
X
X X
X X
X X
X
X
1 1
X X
0
0
0
0
0
0
1
1
(b)
Aoi FIGURE 31.18
Positive Edge-triggered Masterslave RS Flip-flop with Active High Asynchronous
CLEAR and PRESET: (a) Master-slave flip-flop with cross
ncctions of the master outputs and slave inputs of
Figure 31.18a are the same as those of Figures 31.16
and 31.17.
Figure 31.186 and c show the circuit symbol and
truth table for this gate.
0
0
0
0
0
1
0
1
Q
Q
Q
Q
0
1
0
1
0
0
Q
1
Q
0
1
0
0
state of master latch is
transferred to slave latch
on rising edge of CLK
PRESET and CLEAR
inputs are active regardless
of state of CLK
0
(c)
coupled AND-OR-invert latches, (b) Circuit symbol, (c)
Truth table
Example 31.5 Master-Slave Flip-Flop with
ENable Gating Input
Design a RS master-slave flip-flop that is negative
edge-triggered and has a gating ENable input connected to both the master and slave latches.
524
Chapter 31/Latches and Flip-Flops
master and slave are disabled when EN is low
master (enabled when CLK is high
and EN is ltlgh)
slave (enabled when CLK is fow
and EN is hi.gh)
s (}· ........
................
·.
Q
.
RC····-.•·
CLK
.
.
C} ....... +·····'··················· .................................... 1
ENG
'·······················································•· . -----~----·----·- '
(a)
CLK
EN
X
0
1
1
Q
s
s
1
1
Q
7_
1
7_
7_
1
1
7_
1
S R
Q
Q
X
X
X
X
0
0
X
X
X
X
0
Q
Q
Q
Q
Q
Q
a
1
0
1
1 0
1 1
1
1
1
Q
Q
-
stearing gates of master
and slave are disabled
when EN is low
-
Q
0
state of master latch is
transferred to slave latch
on falling edge of CLK
only when EN is high
(b)
(c)
FIGURE 31.19 Example 31.5 Negative Edge-triggered
RS Master-slave Flip-flop with ENable input: (a) Circuit
showing gating ENable input connected to both master
and slave latches, (b) Circuit symbol indicating ENable
input and negative edge-triggered clock, (c) Truth table
Solution Recall the negative edge-triggered master-slave RS flip-flop of Figure 31.15. Connecting a
gating input to both steering gates of the master and
slave latches such as in Figure 31.19a provides an
ENable input for the entire master-slave flip-flop.
When EN is low, the outputs of the master and slave
steering gates are held low regardless of the states of
the S, R, and CLK inputs. When EN is high, the flipflop of Figure 31.19a operates in exactly the same
manner as the flip-flop of Figure 31.15.
Figures 31.196 and c display the circuit symbol and truth table for this flip-flop with ENable
input.
3l.6
steering gates
gatedKandJ
and feedback are
transferred to
latch when EN ::::: I
Edge-Triggered Master-Slave RS Flip-Flops
525
RS latch
EN
(b)
(a)
~
EN
J K S' R'
Q
Q
state
0
X X 0 0
0 0 0 0
0 1 0 1
1 0 1 0
1 1 Q Q
Q
Q
Q
Q
0
1
1
Q
0
unchanged
unchanged
reset
set
toggle
---
1
1
1
1
Q
J and K inputs
are active only
when EN is high
(c)
FIGURE 31.20
Basic JK Latch: (a) Gated RS latch with outputs fed back to inputs, (b) Circuit symbol, (c) Truth table
cross-coupled AND-OR-invert realization
all NAND realization
steering gates
RS latch
K'
EN
D---i
AOI
(d)
FIGURE 31.20 (continued)
(e)
· 1"' (d) Cross coupled AND-OR-invert realization, (e) Cross coupled NAND realization
526
Chapter :ll/L1tches and Flip-f-lops
J
4
-------l,--------------•F···'···'·'~-·► t
¼
K
nI
L
.
0
tm
;--·►
t
tu
EN
1
"",
0
-----------i--·►
ti
Q
t
tu
Qgoeslow
. when K goe-s high
1
-----------.-,i,-.,,;....andEN ishlgh
0
·································-··········-~·····--·~-~------------..-,J,;.~,,,c-···-·►
Qto
when
EN
J,
are high
' Q goes
whenJ g
l .
t
t;. '
i
andEN
(f)
FIGURE 31.20 (continued)
31.7
(f) Time waveforms illustrating JK latch operation
JK LATCH
The JK latch is Jn extremely important gate and is
simply a slight modification of the RS latch. Since
the RS latch has J problem with the R = S = 1 input
st.:ite by giving inconsistent outputs, the JK btch is
used to eliminate this problem. Figure 31.20a displays the circuit for a JK latch with an ENable input.
This JK latch is made up of two three-input AND
g.:itcs and an RS latch. The following analysis will
show that feeding back the Q and Q outputs replaces
the unused RS-latch input combination with a toggle
state. The JK latch logic symbol is shown in Figure
31.20b. The truth table for the JK lJtch is displayed
in Figure 31.20c. Note from the truth thJt Q and Q
hJve no inconsistent states for Jny cornbinJtion of
inputs. Also, the reJder should reJ\ize the outputs Q
.:ind Q in Figure 31.20a for cJch combinJtion of in-
31.7
puts is determined by first finding the Rand S values
for the given EN, J, and K values. Of course, in row
1 of the truth table, the values of J and K do not
matter since EN = 0, and therefore Q is unchanged.
For all other rows EN = 1, and the values of J and
Kare important. Verification of these rows is accomplished directly from the circuit of Figure 31.20a.
Unchanged State (J = 0 and K = 0)
For J = K = 0, R' = S' = 0, and Q is unchanged.
Reset Condition (J =0 and K = 1)
Next for J = 0 and K = 1, from the circuit
S'
= J· Q = 0 · Q = 0
and
R' = K · Q = l · Q = Q
Thus, if Q = 1, then R' = 1 and S' = 0 and Q becomes 0. On the other hand, if Q = 0, then R' = 0
and S' = 0, Q does not change state, and thus Q
remains 0. Hence, this is the reset condition.
Set Condition (J = 1 and K = 0)
for J = 1 and K = 0, from the circuit the internal S'
and R' become
J. Q = Q
S'
=
R'
=K·Q=
and
0
Note that for Q = 1, S' = R' = 0 and Q remains 1.
For Q = 0, S' = 1 and R' = 0. Hence, J = 1 and
K = 0 is the set condition and Q becomes 1.
Toggle Condition (J
Finally, when J = K = 1,
S'
=
JI< Latch
527
which is the set condition and Q changes to 1. On
the other hand, when Q = 1 initially, then
S' = 0
and
R' = l
which is the reset condition and Q changes to 0.
Thus when J = K = 1, the output Q (and therefore
Q) changes state (or toggles) as indicated in the truth
table.
Cross Coupled
AND-OR-Invert Realization
ADI
JK latches are easily realized using AND-OR-invert
logic gates. Figure 31.20d shows the cross coupled
AND-OR-invert JK latch. Note that this is simply the
logic circuit of Figure 31.20a with each AND-NOR
pair replaced by complex AND-OR-invert logic
gates.
All NAND Realization
JK latches can be realized entirely with NAND gates
in a fashion similar to that achieved with the various
RS latch configurations. Figure 31.20e displays the
all NAND JK latch configuration. The cross coupled
NOR latch of Figure 31.20a is replaced with cross
coupled NAND gates. Since the cross coupled
NAND latch has active low, with S' and R' inputs,
the steering AND gates of Figure 31.20a are replaced
with steering NAND gates. Note that the Q output
is fed back to be NANDed with the J input resulting
in the active low S' internal signal. Likewise, the Q
output is fed back to be NANDed with the K input
to drive the internal R' signal.
= 1 and K = 1)
J. Q = Q
JK Latch with Asynchronous
Clear and Preset
Example 31.6
Design a JK latch with asynchronous clear and preset
inputs.
and
R'
=K·Q=Q
Thus, when Q = 0 initially, S' and R' become
S' = 1
and
R' = 0
Solution (All NAND Realization) In section
31.5, asynchronous clear and preset inputs were
added to RS latches by including additional inputs
directly to the cross coupled latch (see Figures 31.13a
and 31.14a). The all NAND JK latch of Figure 31.20e
is modified in Figure 31.21a to include additional inputs in the cross coupled NAND latch. These inputs
528
Cha pte r 31 / L<1tches an d Fli p- Flops
gated J and K and feedback
are transferred to the crosscoupled latch when EN = 1
PRESET
asynchronous PRESET is active
regardless of state of EN
?
PRESET
I
J PRESET Q _
EN
-
K CLEAR Q -
asynchronous CLEAR is
active regardless of state of EN
(a)
EN
J K
1
1
1
1
0 0
0
X
X
X
0
1
1
X
X
X
X
S' R'
1 1
1 1 0
0 0 1
1 Q Q
X X X
X X X
X X X
X X X
(b)
PRESET CLEAR
1
1
1
1
1
1
1
1
1
1
1
Q
Q
Q
Q
0
1
1
Q
Q
Q
Q
0
0
1
0
1
1
0
0
0
0
0
-
0
1 __
J and K inputs are active
( only when EN is high
I
, PRESET and CLEAR inputs are
,'. active regardless of state of EN
(c)
FIGURE 31 .21 Exa mpl e 31 .6 JK Latch w ith Ac ti ve Low Asynch rono us PRESET a nd CLEAR inputs: (a) All NANO
realiza ti on, (b) Circuit symbol, (c) Truth ta ble
act as asynch ro n ous PRESET a nd CLEAR in puts.
The circuit symbol for this la tch is sh own in Fi gure
31.21c is le ft as a hom ework exercise .
Toggle Oscillations
Careful examination o f the JK latches o f this sec ti on
indicate a n inh ere nt p ro blem is observed whe n both
the J and K inputs a re high simulta neously. As d iscussed in the preced ing ana lysi s, wh e n both inputs
are hi gh, th e JK latch is in the toggle sta te. If both
inputs rem ain hi gh after th e Q a nd Q outputs toggle,
the outputs wi ll na tu ra lly toggle aga in since the JK
latch is still in th e in put toggle sta te. Tha t is, th e Q
a nd Q ou tputs w ill toggle re pea tedl y (oscill ate) as
lo ng as th e J a nd K inputs rema in hi gh. Th is osc il la tion probl e m is all evia ted by using th e edge- trig gered maste r-slave ]K fli p - fl op presented in the fo llowin g secti o n .
31.8
EDGE-TRIGGERED MASTER-
SLA VE JK FLIP-FLOPS (JKFF)
The oscillatin g toggle s ta te of th e JK lntch c;J n be
eliminated by usin g a master-slave JK flip - fl op. Reca ll from section 31.6 th a t the outpu ts o f maste rs lave fli p- fl ops respond to th e sta te of th e inputs on
31.8
Edge-Triggered Master-Slave JK Flip-Flops GKFF)
master (enabled when CLK is low)
529
slave (enabled when CLK is high)
set input
Q
reset input
(a)
J K
Q
Q
0
X X
Q
Q
1
X X
X X
Q
0 0
Q
1
0
1 0
1
1
0
1 1
Q
Q
CLK
7_
(b)
s
s
s
s
0
Q
·-
Q
Q
Q
state of master latch is
transferred to slave latch
on rising edge of CLK
(c)
FIGURE 31.22
Positive Edge-triggered Master-slave JK Flip-flop: (a) Outputs of slave are fed back to inputs of master,
(b) Circuit symbol, (c) Truth table
the rising or falling edge of a clock signal. Figure
31.22a shows an edge-triggered master-slave JK flipflop. The Q and Q outputs of the slave latch are fed
back to be NANDed with the K and J inputs of the
master latch. For this particular flip-flop, the master
latch is enabled when CLK is high. Thus, this is a
positive edge-triggered JK flip-flop.
The circuit symbol for this flip-flop is shown in
Figure 31.226. Note that the clock input is labeled
with the edge-triggered wedge.
JK Flip-Flop Truth Table
The truth table for the JK flip-flop of Figure 31.22a
is shown in Figure 31.22c. This table shows the outputs remain unchanged when the CLK signal is constant or undergoing its high-to-low transition. When
the CLK signal is in its low-to-high transition, the
Q and Q outputs react to the J and K inputs in a
fashion similar to that of the JK latch of the preceding
section.
530
Ch,1ptcr 31/L:itchcs il!ld flip-flops
PRESET
.J
K
CLEAR
CLK
(a)
CLK J K PRESET CLEAR
-i_ 0 0
1
1
-i_ 0 1
1
1
-i_
1
1
1 0
-i_
1
1
1 1
-----·
(b)
t--------·----
Q
Q
-
Q
Q
0
1
1
Q
Q
- - - -----~
0
--
X
X X
1
1
Q
Q
X
X
X
X X
X X
X X
1
0
1
0
1
1
1
0
0
0
state of master latch
is transferred to
slave latch on falling
edgeofCLK
0
1
PRESET and CLEAR
inputs are active
regardless of state
ofCLK
(c)
Example 31.7 JK Flip-Flop with
Asynchronous PRESET and CLEAR Inputs
Design a negative edge-triggered JK flip-flop with
asynchronous PRESET and CLEAR inputs.
Solution (All NAND Realization) Figure 31.23a
shows a master-slave JK flip-flop with additional inputs added to each of the cross coupled NAND
latches. Connecting the new inputs of the master
and slave latches together provides active low
PRESET and CLEAR inputs. The outputs of both
the master and slave latches will react to the
PRESET and CLEAR inputs regardless of the state
of the CLK signal.
Since a negative edge-triggered flip-flop is requested, the master latch is enabled when CLK is
high and the slave latch is enabled when CLK is low.
31.8
531
Edge-Triggered Master-Slave JK Flip-Flops CTKFF)
master (enabled when CLK is low)
slave (enabled when CLK is high)
Q
CLKv
t
1
'·········································· - - - - - - - - - - - - - - - - - - - - - -
ENv·····'······················
---------~-----·-····················································.1
(a)
0
-
CLK
EN
X
0
1
0
1
1
1
1
7-.
-
(b)
s
s
s
s
1
1
1
J
K
X--X
XX
X X
X X
0 0
0 1
1 0
1
,
Q
Q
1
Q Q
Q
Q
··Q
1
0
Q
Q
Q
----
Q
Q
Q
Q
0
-
----
stearing gates of master
and slave are disabled
when EN is low
state of master latch is
transferred to slave latch
on rising edge of CLK
(c)
FIGURE 31.24 Example 31.8 Positive Edge-triggered
Master-slave JK Flip-flop with Gating ENable Input:
The circuit symbol for this latch is shown in Figure 31.23b. The PRESET and CLEAR inputs are
drawn with inverting bubbles. The edge-triggered
clock input is drawn with both an inverting bubble
and an edge-triggered clock wedge.
The truth table describing operation of this flipflop is shown in Figure 31.23c.
(a) All NAND realization, (b) Circuit symbol, (c) Truth
table
Example 31.8 JK Flip-Flop with Additional
ENabling Input
Design a positive edge-triggered master-slave JK
flip-flop with an additional ENable input connected
to both the master and slave latches.
Solution Figure 31.24a shows the flip-flop of Figure 31.22a with an additional ENable input con-
t>o~"~?~n
Q
D C ······
□·-
...__ _. .S_.
; :. =;~ + Q c Q
(b)
D
0
1
R S
1 0
0 1
1
0
(d)
(c)
FIGURE 31.25 Basic D Latch: (a) Cross coupled NOR ga te reali za tion, (b) Circu it symbol, (c) Truth table, (d) Cross
co upled NANO gate realization
D
1.
~
, ----+-----+----►
t,'
tl.
t.
Q
1
t
¼
1 Qis low
\Vhen D is low
•
·t,
Q
.·
!
1
0
n~
t,
Qi!!high /
w:hen I) is high
_ _....-.,---
' ··· ·'·..j _ I I
t,
(e)
532
•
t
Tl.kl
steering gates
Edge-Triggered Master-Slave JK Flip-Flops (JKFF)
533
RS latch
D
--fool~ · ·
gated Dis
transferred to
latch when EN = 1
(b)
(a)
cross-coupled AND-OR-invert realization
EN
D
Q
Q
0
X.
Q
a
1
0
0
1
1
1
1
0
~-~
.\ D input is active
only when EN is high
j
(c)
AO/
steering gates
RS latch
j',Ur,Q
EN
c..;.••··+······································"
(d)
all NAND realization
R-~Dic,Q
(e)
FIGURE 31.26 Gated D Latch: (a) Cross coupled NOR
gates with steering AND gates, (b) Circuit symbol, (c)
Truth table, ' 1" 1 (d) Cross coupled AND-OR-invert
realization, (c) NAND realization
534
Chapter 31/Latches and Flip-Flops
D
A
1
0
II
I
i
·►
i
t.
t1
t
EN
A
I
··1
'
0
_l__---+---~-- ► t
..J
½
Q
t;,
Q goes low
when D goes low
and EN is high
A
1
0
½
Q
1
J
4
~
\
~
½
~
~ ~
II
jf
ofD is iatchOO _ /
when EN goes low
v,Jm,
(f)
FIGURE 31.26 (continued)
(f) Time waveforms illustration operation
nected to both steering NAND gates of the master
and slave latches. The J and K inputs will have no
effect on the Q and Q outputs (as well as the QM
and QM master latch outputs) unless the EN input
is high. When EN is high, operation of this flip-flop
is identical to that of the Figure 31.22 JK flip-flop.
31.9
BASIC DATA (D) LATCH
Basic D Latch Cross Coupled
NOR Realization
Figure 31.25a displays a new type of latch called a
data latch, or D latch. This latch consists of a cross
coupled NOR RS latch and an additional inverter,
has a single input D, and complementary Q and Q
outputs. The circuit symbol for this latch is shown in
Figure 31.256. The single input labeled D is fed directly to the cross coupled NOR gate S input and the
inverted D is fed to the cross coupled NOR gate R
input. As will be seen in the following analysis, the
Q output of this latch is equal to the input D.
Analysis
Figure 31.25c displays the truth table for the D latch.
Note that the internal R = D and S = D signals are
included. Examine the first line of this truth table,
:,Jy
ltisic Dc1l,1 (D) L1lch
535
all NAND realization
steering gates
RS latch
D
EN1
EN2
(b)
(a)
cross-coupled AND-OR-invert realization
AO/
···O
Q
-0
Q
(C)
Latches with Dual ENabling Inputs: (a) NAND realization, (b) Circuit symbols, ' 1" 1 (c) Cross coupled
AND-OR-Invert realization
FIGURE 31.27
when D = 0, R = 1 and S = 0. This corresponds to
the reset condition of the simple RS latch presented
in section 3.13 and Figure 31.6. Thus, D = 0 results
in the RS latch reset condition and
~=
o}
Q=l
D=O
Likewise, when D = 1, R = 0 and S = 1. This corresponds to the RS latch set condition. Hence, for
D = 1
~
=
1}
Q=O
0=1
This simple analysis shows that
Q=D
and
Q=D
Basic D Latch Cross Coupled
NAND Realization
Identical operation can be achieved with cross coupled NAND gates as shown in Figure 31.25d. The
cross coupled NAND RS latch of section 31.3 and
Figure 31.7 has active low set Sreset R inputs. Hence,
D is fed to the reset input and the D is fed to the set
input. This is indicated in the shaded portion of the
Figure 31.25c truth table. The operation of the cross
coupled NAND embodied D latch of Figure 31.25d
is therefore identical to the cross coupled NOR realization of Figure 31.25a.
536
Chapter 3]/Latchcs and Flip-Flops
asynchronous PRESET is active
regardless of state of EN
PRESET
C
t
PRESET
D PRESET Q _
ENCLEAR Q -
asynchronous CLEAR is
active regardless of state of EN
f'.J ;r,:4. R
CLEAR
(a)
(b)
EN
D
Q
Q
state
0
X
1
1
Q
a
1
0
1
1
1
X
1
1
1
0
1
0
X
X
X
1
0
0
1
latch
store O
store 1
clear
0
1
1
0
0
0
0
0
X
X
PRESET CLEAR
1
preset
not used
D inputs is active
;, when EN is high
1.
/
PRESET and CLEAR inputs are
active regardless of state of EN
(c)
FIGURE 31.28
(c) Truth table
D Latch with (active low) Asynchronous Clear and Preset: (a) NAND realization, (b) Circuit svrnbol,
Dynamic Operation
Addition of Steering Gates
Figure 31.25e displays time waveforms illustrating
the basic D latch which is identical for Figures 31.25a
and 31.25d. When the D input is high, the output Q
is high and the output Q is low. Conversely, when
D is low, the Q output is low and the Q output is
high.
The obvious drawback of the basic D latch is its
inability to actually store digital information. This
section was presented as a prelude to the discussion
of the following section, which presents the gated
data latch.
Figure 31.26a displays the insertion of steering gates
between the D and D signals and the cross coupled
NOR gates of the Figure 31.25a D latch. This is analogous to the gated RS latch of Section 31.4 and
Figure 31.11. The gated latches include the addition
of an ENable input connected to two steering AND
gates. These additions control when the effect of the
inputs is transferred to the outputs. As with the gated
RS latch, the steering gates prevent the transfer of
the input signal to the cross coupled latch until the
ENable input is brought high. When the ENJ.nput
is high, the internal signals R' = D and S' = D and
the Q and Q outputs will respond to the value of D.
Upon the high-to-low edge of EN, R' = S' = 0 and
the cross coupled NOR gates will latch the current
Q and Q logic states. Figure 31.26b shows the circuit
symbol for this gated D latch and Figure 31.26c displays the truth table describing the operation.
31.10
GATED DATA (D) LATCH
This section introduces several gated D latches which
are the basic element of digital registers. Figure 31.26
displays the first of these gated D latches.
3110
Gcitcd Dcitci (D) Latch
CLEAR
A
0 ...
PRESET
4
0
t,,
))
"··-►
t
►
t
·►
t
t.,
-
-i
l
0
t,
EN ½
t, t,,j}
tl4
t"
~
1
····'····
i
0
Q
t,
t)
¼
tu
'
·•
i t'°
1
0
t
=-=~-~~w,w,•~,.,,~•••.,•••• ...
Q
I:,
½
t"
ti, tl<
t15
i--""""'f····•·l'---l· '
0
tss
(d)
FIGURE 31.28 (continued)
(d) Time waveforms illustrating operation
' '
'
►
t
537
538
Chapter 31/Latches and Flip-Flops
Q
D
(a)
EN=l
0
-
EN
D
Q
Q
0
X
Q
Q
1
0
0
1
1
1
1
0
(b)
(c)
EN=O
(d)
(e)
FIGURE 31.29 Tri-state Embodied D Latch:
(a) Circuit, (b) Circuit symbol, (c) Truth table, (d) EN
= 1 enabled input, (e) EN = 0 enables positive feedback
loop (i.e. latched state)
Cross Coupled
AND-OR-Invert Realization
Q output states are latched. Changes in D that occur
while EN is low do not effect the cross coupled latch
logic states. Note, at times t10 and t11 D changes
twice while EN is high and the output logic states
respond to both changes.
AOI
Figure 31.26d shows the corresponding cross coupled AND-OR-invert realization of the gated D
latch. This configuration has replaced the separate
AND and NOR gates with complex AOI logic gates.
NAND Realization
Figure 31.26e shows the all NAND gated RS latch of
Figure 31.12a vvith an additional inverter to implement the gated D latch function.
Dynamic Operation
Figure 31.26f displays time waveforms illustrating
the operation of gated D latches. At times t2 and t5
the ENable input undergoes low-to-high transitions
and the outputs attain Q = D and Q = D. At times
t3 and t6 EN goes high-to-low. At this time Q and
Example 31.9 Data Latch
with Dual Enable Lines
Modify the gated D latches of Figures 31.26e and d
to include dual ENable inputs.
Solution (NAND Realization) To include multiple enable lines, add additional inputs to the steering
NAND gates as shown in Figure 31.27a. This D latch
shows steering NAND gates with three inputs with
enable inputs EN1 and EN2 connected to both steering gates. The circuit symbol for this gate is shown
in Figure 31.27b.
D
l
0
t,,
tj
EN
1
0
¾
Q
Q goes low
,,,- when D goes low
amt EN is high
t3
Q goes high
when D goes
amfEN is hg1
~
/
~ value of D is latched .... ---~
when EN goes low
(f)
FIGURE 31.29 (continued)
(f) Time waveforms illustrating operation
Solution (AND-OR-Invert Realization) Figure 31.27c shows the D latch of Figure 31.26d with
additional inputs added to the ANDing portion of
the AOL Operation of the D latches of Figures 31.27a
and c is identical.
AOI
Example 31.10 Gated D Latches with
Asynchronous Clears and Presets
Add asynchronous clear and preset inputs to the
gated D latch of Figure 31.26e.
Solution Figure 31.28a displays the gated D latch
of Figure 31.26e with asynchronous PRESET and
CLEAR inputs. This is analogous to section 31.5 and
Figure 31.14 in which asynchronous clear and preset
inputs arc added to the gated RS latch by including
additional inputs to the cross coupled NAND gates.
Since the D latch also employs cross coupled NAND
gates, these are active low PRESET and CLEAR inputs.
Figure 31.28b shows the circuit symbol for the D
latch with two enables. The truth table describing
operation of this latch is shown in Figure 31.28c.
Time waveforms describing operation of this gate are
shown in Figure 31.28d.
The lotches and flip-·flops described thus far hove
all been constructed using configurotion of NOR
540
Chapter 31/Latchcs and Flip-Flops
EN,1---
~
i Tp
D
f----t----~
Q
EN
QCLEAR
CLEAR
asynchronous CLEAR is
active regardless of state of EN
(a)
EN
D
X
0
-- ,~
1
0
CLEAR
Q
Q
state
0
Q
Q
latch
store O
store 1
clear
1-------1---
1
1
0
0
X
X
1
0
1
1
0
0
1
---
\
(b)
D input active
when EN is high
_,)
-------------- CLEAR input is active
regardless of state of EN
(c)
FIGURE 31.30
gates, NAND
That is, they
combinational
introduces D
verters.
Tri-state Embodied D latch with Asynchronous CLEAR: (a) Circuit, (b) Circuit symbol, (c) Truth table
gates, inverters, and complex AOis.
have been realized entirely with
logic gates. The following section
latches designed with tri-state in-
31.11 TRI-STATE EMBODIED GATED
DATA (D) LATCHES
Design of latches and flip-flops in CMOS offers the
opportunity to include tri-state inverters and transmission gates. Figure 31.29a displays a gated D-latch
designed with tri-state inverters. Both the input D
and output Q are connected to the input of the inverter IQ through tri-state inverters. The additional
inverter IEN inverts the EN gate signal. This latch has
the same circuit symbol (Figure 31.296) and realizes
the same truth table (Figure 31.29c) as described in
the following simple analysis.
Input Enabled Condition
The data input D is connected to a tri-state inverter
TD which is clocked when the gate signal EN is high.
11,is situation is depicted in Figure 31.29d. The output of TD is reinverted by the inverter I<_i so the output
Q = D. Thus, EN high is the input enabled condition. This verifies the second and third lines of the
Figure 31.29c truth table.
Latched Condition
When EN is brought low, TD is disabled and the tristate inverter Tr- is enabled. This creates a positive
feedback inverter loop as shown in Figure 31.29e
forcing Q and Q to be inverses of each other and
independent of D. This verifies the remaining first
line of the Figure 31.29c truth table.
Hence, the circuit of Figure 31.29a is clearly a D
latch identical in operation to the logically realized
D latch of the preceding section. Time waveforms
illustrating operation of this latch are shown in Figure 31.29d for completeness.
31.11
Tri-State Embodied Gated Data (D) Latches
541
CLEAR
-
---'--4------------',---J--""+~~4---~;_;c.c;,C,:~{..-.r,,.
0
EN
0 ...
t
t.
t,
---,.;.+~-~~+-------4----~--------~~~;;,.,c..;.~;.....t,
Q
(d)
FIGURE 31.30 (continued)
(d) Time waveforms illustrating operation
Tri-State Inverter Mux
Examining Figure 31.29a, the reader may note that
the inverter IE~ and the two tri-state inverters are
simply a 2:1 multiplexor. The gate signal EN selects
either D or Q to drive the input of the inverter IQ.
This tri-state realized mux was presented in Example
25.8 and Figure 25.18. The reader should review that
example at this time to provide further understanding of the tri-state embodied D latch.
Tri-State Embodied D Latch
with Asynchronous Clear
The tri-state embodied D latch of Figure 31.29a can
be modified to include either an asynchronous clear
or set. Figure 31.30a shows a D latch where the inverter IQ has been replaced with a NOR gate NQ.
The second input of the NOR gate provides an asynchronous CLEAR that is active regardless of the
state of the EN gating signal. If CLEAR is low, then
the NOR gate inverts the output of the active tristate inverter. When CLEAR is high, the output of
the NOR gate is low regardless of the logic level of
EN or D. If EN is low so that the feedback tri-state
inverter TF is active, the positive feedback inverter
(see Figure 31.29e) will latch Q = 0.
Figure 31.306 shows the circuit symbol with the
asynchronous CLEAR drawn at the bottom of the
symbol. The truth table listing the operational states
of the D latch is displayed in Figure 31.30c. Time
waveforms illustrating operation of the D latch are
shown in Figure 31.30d. Note that at times t5 and t13
CLEAR is brought high and Q goes low regardless
of the state of EN.
542
Chapter 31/Latchcs and Flip-Flops
g-
I TF
-
T
D
Q
I
[
SET
NQ
.,.,....,
~.:u.~..1.
asynchronous SET is active
regardless of state of EN
(a)
D
EN
SET
0
X
1
- - - -~ · - - - 1
1
0
Q
Q
Q
Q
--
1
1
1
0
1
X
X
0
1
state
- - - ~·
1
0
0
(b)
latch
--- --'\>' D'mputs 1s
. active
.
store O
.
when
EN
is
high
store 1
j
set
-------- SET input is active
regardless of state of EN
(c)
FIGURE 31.31
Truth table
Tri-state Embodied D latch with (active low) Asynchronous SET: (a) Circuit, (b) Circuit symbol, (c)
D
master latch
slave latch
D
Q
D
Q
a
EN
a
Q
CLK
CLK
lax
(b)
(a)
-
D
Q
0
X
Q
Q
1
X
X
Q
Q
a
s
7_
0
0
1
7_
1
1
0
CLK
Q
Q
state of master latch is
transferred to slave latch
} on falling edge of CLK
(c)
FIGURE 31.32 Negative Edge-triggered Master-slave
D Flip-flop: (a) Master latch is enabled when CLK goes
high, slave latch is enabled when CLK goes low,
(b) Circuit symbol, (c) Truth table
31.12
Edge-Triggered Master-Slave D Flip-Flops
543
D
0 ...;---!i~-:.........-c.-:.........-....;;..,.~--------...,L-J.----!---l----• ► t
t, tij
CLK
Q
t.
(d)
FIGURE 31.32 (continued)
(d) Time waveforms illustrating operation
Tri-State Embodied D Latch
with Asynchronous Set
The D latch of Figure 31.30a can easily be modified
to include an (active low) asynchronous SET instead
of CLEAR by replacing the NOR gate with a NAND
gate. Figure 31.31a shows such a latch. If the input
labeled SET is high, then the NAND gate inverts the
output of either tri-state inverter that is enabled. If
SET is low then the output of the NAND gate is high
regardless of the states of D and EN. Thus, the second NAND input acts as an active low asynchronous
SET. The circuit symbol for this latch is shown in
Figure 31.31b. The truth table listing the operational
states is shown in Figure 31.31c.
31.12 EDGE-TRIGGERED
MASTER-SLAVE D FLIP-FLOPS
The D latches of the previous section are easily modified to realize edge-triggered master-slave D flipflops.
Negative Edge-Triggered D Flip-Flop
Figure 31.31a shows two D latches and an inverter
in a master-slave configuration. The circuit symbol
for this flip-flop is shown in Figure 31.32b. The first
D latch is ENabled when CLK is high and the slave
latch is enabled when CLK is low. The input D is
latched by the master latch when CLK is high and
the state of the master latch is transferred to the slave
latch on the falling edge of the CLK signal. The truth
table for this flip-flop is shown in Figure 31.32c. Figure 31.32d shows time waveforms illustrating operation of the D flip-flop.
Positive Edge-Triggered D Flip-Flop
The D flip-flop of Figure 31.31a is easily modified to
realize a positive edge-triggered flip-flop. Figure
31.32a shows the flip-flop of Figure 31.31 with the
CLK and CLK signals driving the slave and master
latches, respectively. This results in a positive edgetriggered flip-flop as described in the truth table and
time waveforms of Figures 31.33c and d.
Unlike RS and JK latches and flip-flops, D
544
Chapter 31/Latchcs and Flip-Flops
master latch
D
slave latch
r,[>otc~l:N :1 ~ ~:N :1~
CLK o-
1-
-·· -
-
- ~ -
Q
I
- I
(a)
(b)
CLK
D
Q
n
V
Q
X
X
0
1
Q
"
1
L
~-__r
__r
"
Q
Q
Q
-
Q
Q
~
0
1
1
0
}
state of master latch is
transferred to slave latch
on rising edge of CLK
(c)
(d)
FIGURE 31.33 Positive Edge-triggered Master-slave D
Flip-flop: (a) Master latch is enabled when CLK is low,
slave latch is enabled when CLK is high, (b) Circuit
symbol, (c) Truth table, (d) Time waveforms illustrating
operation
31.12
Example 31.12 Toggling D Flip-Flop
Design a D flip-flop which toggles the output state
with every negative clock edge.
Example 31.11 D Flip-Flop
with Synchronous Clear
Design a negative edge-triggered D flip-flop with an
edge-triggered CLEAR input.
Solution AD flip-flop that toggles its output state
with every negative clock edge is realized by a simple
modification of the D flip-flop of Figure 31.33. Remove the D input of the flip-flop and feed back the
inverting Q output of the slave latch to the D input
of the master latch as shown in Figure 31.35. When
CLK goes high the Q output is latched by the master
latch. Upon the negative edge of CLK, the state of
the master latch is fed to the slave latch. This operation repeats for each clock period and thus the flipflop of Figure 31.35a toggles output state upon every
negative clock edge.
Note that D latches without asynchronous
Solution The D flip-flop of Figure 31.32 is a negative edge-triggered flip-flop. An edge triggered
clear input can be added by placing a two-input
NOR gate between the data input of the flip-flop and
the D input of the master latch as shown in Figure
31.34a. Both inputs to the NOR gate effect the flipflop outputs on the negative edge of the CLK signal.
If the input labeled CLEAR is high, the output of the
NOR gate is low regardless of the state of the other
input. Thus, the additional input indeed acts as an
edge triggered clear input.
D
D
Q
_ EN
Q
I
CLKo
1
CLK
I
[>o
545
When the CLEAR input goes low, the NOR gate
acts as an inverter to the data input. The data input
is therefore labeled D. The circuit symbol and truth
table for this flip-flop are included in Figure 31.346
and c.
latches and flip-flops simply store the logic state of
the input data signal. The D flip-flops of Figures
31.32 and 31.33 can be modified to include additional
functionality by including some type of combinational logic at the D input of the master latch. The
following two examples demonstrate this principle.
CLEAR o-~
Edge-Triggered Master-Slave D Flip-Flops
Q
Q
Q
EN
bB
~
(a)
CLK
(b)
-
Q
Q
D
CLEAR
0
1
X
X
X
Q
X
Q
s
X
X
Q
Q
777-
0
0
1
0
1
X
0
0
1
1
0
1
a
a
-
(c)
FIGURE 31.34 Example 31.11 Negative Edge-triggered D Flip-flop with Synchronous CLEAR: (a) Circuit, (b) Circuit
symbol, (c) Truth table
546
Chapter 31/Latches and Flip-Flops
CLEAR
:t
I
1
t,
"' t
DX
0
~-----------------► t
CLK
1.
4
0
1
(d)
FIGURE 31.34 (continued)
D
Q
Q
(d) Time waveforms illustrating operation
D
Q
EN
Q
Q
CLK
CLK
Q
CLK
Q
0
Q
Q
1
s
Q
Q
Q
Q
7_
Q
Q
Icu
(a)
FIGURE 31.35 Toggling Master-slave Flip-flop of
Example 31.12: (a) D flip-flop with inverted slave latch
(b)
(c)
output fed back to master latch input, (b) Circuit symbol,
(c) Truth table
Chapter 31
D
~----~EN
Q
D
Q
Q
EN
Q
54 7
Q
CLEAR
CLEAR
CLK o-
Problems
-J>o-C_L_K_ _+~
CLEAR
FIGURE 31.36 Toggling Master-slave Flip-flop with Asynchronous CLEAR; flip-flop CLEAR is connected to the
CLEARs of both the master and slave latches
CLEAR or PRESET inputs have been used. As a
result, the initial condition of this flip-flop is unpredictable. Normally, D latches with either an asynchronous CLEAR or PRESET connected to chip reset are used so that the flip-flop will have a known
initial condition. Figure 31.36 shows the flip-flop of
Figure 31.35 using D latches with asynchronous
CLEAR inputs connected to a single flip-flop
CLEAR input.
D flip-flops with many types of logic functionality are possible. Several variations of D flip-flops
are presented in the homework exercises.
CHAPTER 31 PROBLEMS
31.1
What is the difference(s) between a latch and a flipflop?
31.2
Identify edge A and edge B of Figure P31.2 as positive or negative.
31.3
Figure P31.3 shows the CLocK and output signal
of a flip-flop. Does this represent the output of a
rising or falling edge-triggered flip-flop?
31.4
What is the difference between synchronous and
asynchronous logic elements?
31.5
Analyze the inverter loop of Figure P31.5. Is this
configuration capable of storing stable digital information?
CLK
:
Q
0
---------1...____._____.___I►
---'---I
1
FIGURE P31.3
IF
CLK
'
1
0
Q
edge A
~ rf
FIGURE P31.2
Q
- t
FIGURE P31.5
t
548
VIN
Chapter 31/Latches and Flip-Flops
0-
FIGURE P31.6
IN,
~.
n
1~!
~
IN,
Q,
FIGURE P31.10
IN. ~
~~ Q,
.
I
l---r Q,
.-L__/ _j
'
IN, ~
FIGURE P31.7
Q,
31.6
31.7
31.8
Graphically analyze the node voltages of the cascaded inverters of Figure P31.6. If the output voltage VO is fed back to the input Vlc--1, does this circuit
have any stable voltage points? Are there any unstable solutions? In determining the voltages, assume any logic family for the inverters. (Hint: see
Figure 31.5).
Analyze the cross coupled NOR gates of Figure
P31.7. Construct the truth table listing the operational states of this circuit.
Analyze the cross coupled NAND gates of Figure
P31.8. Construct the truth table listing the operational states of this circuit.
IN,~
0
IN,
FIGURE P31.11
31.9
Analyze the cross coupled gates of Figure P31.9.
Construct the truth table listing the operational
states of this circuit. Docs this circuit perform any
useful function?
31.10
Analyze the cross coupled gates of Figure P31.10.
Construct the truth table listing the operational
states of this circuit. Does this circuit perform any
useful function?
31.11
Analyze the cross coupled gates of Figure P31.11.
Construct the truth table listing the operational
Q,
IN
~---,-------0
Q,
Q,
IN, o-------FIG URE P31.8
FIGURE P31.12
---0
Q,
IN,
FIGURE P31.9
Q,
FIGURE P31.13
Chapter 31
549
Problems
s
EN o-
RO-···
FIGURE P31.17
31.14
Analyze the cross coupled gates of Figure P31.14.
Construct the truth table listing the operational
states of this circuit. Does this circuit perform any
useful function 7
31.15
Can a cross coupled NOR RS latch have multiple
reset and set inputs like the circuit of Figure
P31.15 7
31.16
Can a cross coupled NAND RS latch have multiple
set and reset inputs like the circuit of Figure
P31.16?
31.17
\!\That is the difference between the latches of Fig·
ure P31.8 and P31.17 7
31.18
Analyze the latch of Figure P31.17. Draw the truth
table listing the operational states of this circuit.
SJ
FIGURE P31.15
states of this circuit. Does this circuit perform any
useful function?
31.12
31.13
Analyze the cross coupled gates of Figure P31.12.
Construct the truth table listing the operational
states of this circuit. Does this circuit perform any
useful function 7
Analyze the cross coupled gates of Figure P31.13.
Construct the truth table listing the operational
states of this circuit. Does this circuit perform any
useful function 7
AOI
31.19 Do the latches of Figures P31.17 and P31.19
perform the same logic function 7
AOI
31.20
Draw the latch of Figure P31.19 in CMOS.
31.21
What is the difference between the latches of Fig·
ures P31.17 and P31.217
31.22
What function do the INA and IN 8 inputs of Figure
P31.22 pcrform 7
31.23
Modify the RS latch of Figure P31.17 to include
asynchronous CLEAR and PRESET inputs. Arc
these inputs active high or active low7
s;
S,o-b,-oQ
~
EN
R,'-01---oQ
R.
r
R,
FIGURE P31.16
·--0
s
0--
FIGURE P31.19
Q
550
EN2
Chapter 31/Latches and Flif1-Flops
o---l-J
FIGURE P31.21
0
IN.
FIGURE P31.22
FIGURE P31.28
Q
R
I~
CLK o ~ : FIGURE P31.30
- - - - - ~ I N ~ •_ _
__J
Chapter 31
Problems
551
CLEAR
s
PRESET
CLKn--_____L_ _ _ _ _ _ _ _ _ _ _____,
AOI
FIGURE P31.32
31.24
Compare the solution of Problem 31.23 with the
latch of Figure P31.22. Are there any operational
differences?
31.25
Add asynchronous CLEAR and PRESET inputs to
the latch of Figure P31.17. Are these new inputs
active high or low?
Draw the truth table describing the operation of the
latch of Problem 31.25.
Aoi 31.27 Add asynchronous CLEAR and PRESET inputs
to the latch of Figure P31.19. Are these new inputs
active high or low?
Figure P31.32 properly connected to the slave latch
inputs?
31.35
Ao,
What is the function of the flip-flop of Figure
P31.28?
31.29
Modify the flip-flop of Figure P31.28 so that it is a
positive edge-triggered circuit.
31.30
Is the flip-flop of Figure P31.30 positive or negative
edge-triggered?
31.31
What is the function of the INA and IN 8 inputs of
the flip-flop in Figure P31.30? Specify INA and IN 8
as active high or active low inputs.
Modify the RS flip-flop of Figure P31.32 so that
neither the master or slave latch is enabled unless
an additional input EN is high.
31.36
31.26
31.28
Modify the RS flip-flop of Figure P31.30 so that
neither the master or slave latch is enabled unless
an additional input EN is high.
31.37
Draw the truth table listing the operational states
for the latch of Figure P31.37.
31.38
Modify the latch of Figure P31.38 so that it is not
enabled unless a second enable input EN2 is also
high.
Draw the truth table listing the operational
states for the flip-flop of Figure P31.32.
Aoi
31.32
Aoi
31.33
Aoi
31.34
Compare the flip-flops of Figures P31.30 and
P31.32. Are there any operational differences?
Are the master latch outputs of the flip-flop of
FIGURE P31.37
552
Chapter 31/Latches and Flip-Flops
INA
0
K
J
Q
EN
ioQ
J
AUi
K
II
FIGURE P31.38
IN.
FIGURE P31.41
Draw the truth table listing the operational
states for the latch of Figure P31.38.
Aoi
31.39
Aoi
31.40
Compare the latches of Figure P31.37 and